Abstract: Among other things, one or more systems and techniques for transition time evaluation of a circuit are provided herein. In some embodiments, a comparator is configured to receive a circuit signal from the circuit. The circuit signal is evaluated by the comparator based upon one or more control voltages to create one or more voltage waveforms. In some embodiments, the one or more voltage waveforms have substantially similar slopes. A time converter, such as a time-to-current converter or a time-to-digital converter, is used to evaluate the one or more output waveforms to determine a transition time, such as a rise time or a fall time, of the circuit. In some embodiments, the one or more output waveforms are used to reconstruct a transition waveform representing a waveform of the circuit signal.

Abstract: In a method for determining a frequency of an input signal, a first count value is determined by counting clock edges of a reference clock signal while the input signal corresponds to a first level value. Further, a second count value is determined by counting clock edges of the reference clock signal while the input signal corresponds to a second level value. The frequency of the input signal is determined as a function of the first and the second count value.

Abstract: A frequency/timing measurement apparatus includes a reference source having a reference source output terminal. At least one target source has a target source output terminal. The at least one target source is communicatively coupled to the reference source. A frequency timing measurement block has a first input terminal electrically coupled to the reference source output terminal. A second input terminal is electrically coupled to the target source output terminal and at least one output terminal. The frequency timing measurement block is configured to perform a noise shaping technique to reduce measurement error attributable to a phase noise that is correlated between the reference source and the target source, and to provide a reduced correlated noise measurement at the at least one output terminal. A method to reduce correlated noise is also described.

Abstract: Some embodiments of the present invention may include a DPLL circuit comprising a firmware. The firmware may comprise a re-sampled NCO phase detector capable of receiving a reference clock timing signal and a VCXO clock timing signal. The re-sampled NCO phase detector may comprise a resampler capable of receiving phase output and the VCXO clock timing signal and resampling the phase output; and a subtractor capable of receiving the resampled phase output and subtracting the resampled phase output from a calculated mean value of the phase output. The firmware may further comprise a frequency detector capable of receiving the reference clock timing signal and the VCXO clock timing signal; and a multiplexer capable of switching between the re-sampled NCO phase detector and the frequency detector dependent upon a frequency lock status.

Abstract: A frequency/timing measurement apparatus includes a reference source having a reference source output terminal. At least one target source has a target source output terminal. The at least one target source is communicatively coupled to the reference source. A frequency timing measurement block has a first input terminal electrically coupled to the reference source output terminal. A second input terminal is electrically coupled to the target source output terminal and at least one output terminal. The frequency timing measurement block is configured to perform a noise shaping technique to reduce measurement error attributable to a phase noise that is correlated between the reference source and the target source, and to provide a reduced correlated noise measurement at the at least one output terminal. A method to reduce correlated noise is also described.

Abstract: Signal-integrity measurement systems and methods utilizing unique time-base generation techniques for controlling the sampling of one or more signals under test. A time-base generator made in accordance with the present disclosure includes a phase filter and modulation circuitry that generates a rapidly varying phase signal as a function of the output of a sigma-delta modulator. The phase filter filters unwanted high-frequency phase components from the rapidly varying phase signal. The filtered signal is used to clock one or more samplers so as to create sampling instances of the signal(s) under test. The sampling instances are then analyze using any one or more of a variety of techniques suited to the type of signal(s) under test.

Abstract: Magnetically latching and releasing a voice coil actuator for controlling electrical switchgear. The voice coil actuator includes a voice coil magnet disposed on a common longitudinal axis with respect to a voice coil assembly. A coil of the voice coil assembly exerts a magnetic force on the voice coil assembly, thrusting the voice coil assembly towards the voice coil magnet. At least one pair of latching members mounted to the voice coil assembly creates a permanent magnet circuit between the latching members and the voice coil magnet. The permanent magnet circuit maintains the position of the voice coil assembly relative to the voice coil magnet, even when power to the coil is removed. This latch can be released by applying a current in the coil or by applying an external, physical force to a member coupled to the voice coil assembly.

Abstract: Events discovered by an automatic measurement subsystem in the trace of a DSO are visited using a set of event navigation controls. In a TIME Mode the controls operate to display the first of those events, display the next event after the one currently displayed, display the previous event before the one currently displayed, and, display the last event. In a SEVERITY Mode the controls operate to display the best of those events, display the next best event relative to the one currently displayed, display the next worst event before the one currently displayed, and, display the worst event. The sets of navigation controls may be a mode control menu accompanied by four stylized arrow shaped buttons within a GUI that are clicked on by an operator using a mouse. One set of arrow shaped button can serve both modes, or different sets of buttons can serve each respective mode.

Abstract: A method and system acquires a set of samples of a periodic signal at a constant sample rate in a primary memory, calculates a variance between the set of samples and an ideal set of samples to create a variance data set, stores the variance set into a secondary memory, concatenates each variance data set to create a concatenated data set, statistically processes the concatenated data set, and presents the statistically processed data.

Abstract: A method and a device for testing an embedded phase-locked loop (PLL) circuit are disclosed. A first clock signal of a first frequency is provided to an embedded phase-locked loop (PLL) circuit to be tested by a tester, so as to generate a PLL clock signal by the embedded PLL circuit in response to the first clock signal of the first frequency. The PLL clock signal is inputted to a test circuit along with a second clock signal of a second frequency. Then, the PLL clock signal is sampled with the second clock signal of the second frequency to generate a first sampled signal. The second frequency has a first correlation with the first frequency. Whether the embedded PLL circuit is in a normal operation condition is determined according to the first sampled signal.

Abstract: Measurements for an eye diagram of a signal of interest are placed in a data structure that is examined to locate an eye opening of interest. The eye opening of interest has already been, or is subsequently, normalized into figure of merit units related to the operational voltage and timing requirements of the data receiver for that signal. The locations within the normalized eye opening may be taken as center locations for trial symmetric shapes that start out small and are enlarged until they first include locations not part of the normalized eye opening. The center of a largest such shape is mapped back into the units of the original eye diagram as optimum sampling parameters for data analysis equipment that uses the receiver to sample the signal once per unit interval to discover logical value. An alternative is to repeatedly remove the ‘outer layer’ of the normalized eye opening until only one location remains.

Abstract: A digital storage oscilloscope that has a port for receiving a signal, having an embedded clock signal, and a processor, configured by software to recover the embedded clock signal from the signal. In a preferred embodiment, the processor implements a digital PLL to recovered embedded clock signal. In a further preferred embodiment the processor uses the recovered embedded clock signal to generate an eye diagram that graphically portrays jitter in the data signal.

Abstract: A system for determining the phase and magnitude of an incident signal relative to a cyclical reference signal, includes a sampler for sampling the incident signal. Autoranging circuitry is responsive to the reference signal and determines the frequency f of the reference signal and sets the sampling rate sr of the sampler. A processor, responsive to the sampler, computes a single point DFT v of the sampled incident signal responsive to the frequency of the reference signal and determines the phase &thgr; and magnitude |v| of the incident signal relative to the reference signal in response to the single point DFT.

Abstract: A method for lowering the spurious output of a sample and hold phase detector includes the steps of charging a ramp node (502) to a first voltage level after a sample period (606) has occurred. After the ramp node (502) is charged to the first voltage level, the ramp node is charged to a second voltage level during period (610). By precharging the ramp node (502) during the hold period (614), it reduces any leakage current in the SH switch (514), which minimizes any voltage drift thereby improving the spurious performance of the SH phase detector (500).

Abstract: A system for determining the phase and magnitude of an incident signal relative to a cyclical reference signal, includes a sampler for sampling the incident signal. Autoranging circuitry is responsive to the reference signal and determines the frequency f of the reference signal and sets the sampling rate sr of the sampler. A processor, responsive to the sampler, computes a single point DFT v of the sampled incident signal responsive to the frequency of the reference signal and determines the phase &thgr; and magnitude |v| of the incident signal relative to the reference signal in response to the single point DFT.

Abstract: A phase meter precisely measures the phase of two signals with very different frequencies by using a sampler, permuter and a matched filter. The phase meter includes a sampler that samples the fast clock with the slow clock; a permuter that permutes the samples based on the frequencies of the fast and slow clocks; and a matched filter that sums sequences of the samples and generates maximum and minimum phase positions. The maximum and minimum phase positions indicate transition times in the fast clock. The filter can take the average of the minimum and maximum values to determine the phase of the fast clock at the middle point of a cycle. The phase meter can also be used with an interval counter to precisely adjust the transition count used by the interval counter to detect a number of cycles in the interval, and to account for partial cycles that fall within the interval.

Abstract: A phase meter measures the phase of a first signal with respect to a second signal, where the first and second signals have different frequencies and the frequency of the first signal is higher than the frequency of the second signal. The phase meter samples the first signal using the second signal to produce a plurality of samples, where each sample has a sample phase and value. The phase meter permutes the plurality of sample phases to place their phase positions in phase order, and determines, for each permuted sample phase if the sample phase is within a phase range corresponding to a predetermined phase bin. If the sample is within a phase range for a phase bin, a bin counter for that bin in incremented. The phase of the faster signal is determined based on the counts in each of the phase bins.

Abstract: A method for lowering the spurious output of a sample and hold phase detector includes the steps of charging a ramp node (502) to a first voltage level after a sample period (606) has occurred. After the ramp node (502) is charged to the first voltage level, the ramp node is charged to a second voltage level during period (610). By precharging the ramp node (502) during the hold period (614), it reduces any leakage current in the SH switch (514), which minimizes any voltage drift thereby improving the spurious performance of the SH phase detector (500).

Abstract: The present invention relates to a process for determining harmonic oscillations of a fundamental component of an electrical signal, wherein the signal is sampled with a sampling frequency corresponding to a multiple of the fundamental component's frequency. The sampled values of the signal are subjected, after analog-to-digital conversion, to a discrete Fourier transformation to determine the harmonic oscillations. The sampling is performed with a non-integer multiple of the frequency of the fundamental component and the discrete Fourier transformation is performed while the frequency resolution is increased over several periods of the fundamental component to determine the harmonic oscillations.

Abstract: A phase detector determines a phase error value dependent on the relative phase between a local oscillator signal, used for the system clock, and an input signal received over a PR (a, b, b, a) channel. The error value is used to lock the phase and frequency of an input signal to the phase and frequency of the clock in a phase-lock loop (FIG. 1, not shown). The input signal is sampled at regular intervals in accordance with the local oscillator signal, and the sampled values provided on a line 10. A threshold slicer 22 selects an ideal sample value for a sampling point by comparing the sampled values with thresholds received on threshold inputs 23 to 26. A subtracter 32 determines a difference value which corresponds to a difference between the ideal sample value and the actual sample value for that sampling point. A subtracter 28 and a delay register 29 operate to determine the sense of change to the ideal sample value from a ideal sample value for a preceding sampling point.