Abstract: A device of measuring a duty cycle includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The control circuit is coupled to the resistor-capacitor circuit, and configured to acquire an ON-time according to the first voltage, the second voltage and the third voltage. The ON-time is a time interval during which the reference signal is in the first state.

Abstract: This load connection state detection circuit includes a PNP type transistor whose emitter is connected to a power source terminal, a NPN type transistor where the emitter thereof is connected to the power source terminal, the collector thereof is connected to the base of the PNP type transistor, and the base thereof is connected to the collector of the PNP type transistor, and a diode inserted between the collector of the PNP type transistor and an external antenna load, wherein the diode is configured to perform temperature compensation for the base voltage of the NPN type transistor and prevent currents from flowing from the external antenna load to the PNP type transistor and the NPN type transistor.

Abstract: A phase comparator (4) for detecting a phase difference between a first signal and a second signal, a first oscillating circuit (1) for supplying the phase comparator with a reference signal as the first signal, and a DDS (8) as a second oscillating circuit for outputting a signal according to an output of the above-mentioned phase comparator are provided. As for a filter-thickness measuring device using the PLL circuit as a frequency measurement circuit, a crystal oscillator (11) which is made of quartz etc. and connected to the first oscillating circuit is accommodated in a vacuum chamber (C). It is arranged that the frequency measurement circuit which constitutes the PLL circuit measures a film thickness of the film forming material based on a change of a natural frequency of a piezoelectric crystal, the change being caused by the film forming material deposited on the piezoelectric element in the vacuum chamber.

Abstract: A method for high-resolution timing measurement includes a first oscillator generating a first clock with a first frequency. A second oscillator generates a second clock with a second frequency. A delay pulse generator generates a delayed pulse from the second clock. An oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the first frequency. A sampling module samples the delayed pulse at the first frequency. A counter generates a digital counter value by counting a number of samples made by the sampling module.

Abstract: A signal monitoring system includes a conversion circuit and a controller coupled to the conversion circuit. The conversion circuit converts a reference input to a reference output based on a real-time level of a trim reference and converts a monitored signal to an output signal. The controller calibrates the output signal according to the reference output and according to a predefined reference. The predefined reference is determined by the reference input and by a pre-trimmed level of the trim reference.

Abstract: A frequency measuring circuit and a semiconductor device having the frequency measuring circuit include a divided and shifted clock signal generator, a delayed clock signal generator and a phase detecting unit. The divided and shifted clock signal generator divides a frequency of a clock signal input from an exterior to output a frequency-divided clock signal, and delays the frequency-divided clock signal by a time proportional to a period of the clock signal to output a shifted clock signal. The delayed clock signal generator delays the frequency-divided clock signal by a fixed time to generate a plurality of delayed clock signals. The phase detecting unit receives the plurality of delayed clock signals and the shifted clock signal and detects a phase difference between each of the plurality of delayed clock signals and the shifted clock signal to output a plurality of phase detecting signals that represent information related to a frequency of the clock signal.

Abstract: A personal alerting device and method for detecting an approaching sound source includes a sound detector for detecting environmental sounds and for providing an electrical signal to a sound analyzer. The sound signal is analyzed to determine a baseline sound pattern comprising a plurality of distinct sounds corresponding to sounds emitted from a reference sound source. The distinct sounds in the baseline sound pattern may have substantially the same amplitude and time interval. The sound signal is monitored and compared against the baseline sound pattern to determine whether a target sound pattern is present in the sound signal, the target sound pattern corresponding to sounds emitted by the approaching sound source. When it is determined that the target sound is present in the sound signal, one or more of an audible, visual and tactile alert may be emitted to provide warning of the approaching sound source.

Abstract: An integrated circuit for high-resolution timing measurement includes a delay pulse generator, the first oscillator to generate the first clock with the first frequency, the second oscillator to generate the second clock with the second frequency, an oscillator tuner, a sampling module, a counter, wherein the delay pulse generator generated a delayed pulse from the second clock, the oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the second frequency, the sampling module samples the delayed pulse at the first frequency, the counter generates a digital counter value by counting a number of sampling by the sampling module, and a time width of the delayed pulse can be calculated by the digital counter value. The second oscillator can be a tunable ring oscillator with one or more coarse tune stages and one or more fine-tune stages.

Abstract: An integrated circuit for controlling a DC motor is disclosed. The integrated circuit includes at least one digital position and speed circuit (DPS) for providing measurements of speed, position, and direction of the motor, the DPS being in signal communication with the motor for receiving a pair of signals having a quadrature relationship; and at least one programmable gain amplifier (PGA) electrically coupled to the motor, the PGA being configured to receive a feedback signal indicative of current flowing through the motor and to apply a second signal to the motor for adjusting the speed of the motor; and at least two analog-to-digital converters (A/D), one A/D being used to quantize the output of the PGA for an off-chip processor; and another A/D to provide motor reference position from an analog sensor, such as a potentiometer; and at least two digital-to-analog converters (D/A), one D/A used to set the motor voltage; and another D/A used to set the motor current limit.

Abstract: A digital circuit is disclosed for detecting clock activity in an integrated circuit (IC) device. In one implementation, a clock detection circuit can include two flip flops. A first flip flop detects activity on the clock being tested (e.g., the flip flop is set when a positive clock edge is detected). A second flip flop is coupled to the output of first flip flop and is operable by an enable signal to sample the output of the first flip flop. The output of the second flip flop is asserted as active, when a positive clock edge occurs between the release of the reset signal on the first flip flop and the assertion of the enable signal on the second flip flop. In some implementations, one or more additional flips can be interposed between the first and second flips to control metastability.

Abstract: An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, including a latch for comparing the arrival time of the signal of interest to the reference clock, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, a middle stage, and a last stage, a voltage controller in signal communication with the middle stage of the delay chain for controlling the delay of the arrival time of the reference clock while permitting the first and last stages of the delay chain to retain a full voltage swing independent of the delay.

Abstract: The invention is directed to a digital phase detector that comprises a splitter and phase shifter to receive a signal of a device under test and produce a first signal that is substantially identical to the received signal and a second signal that is phase shifted relative to the first signal. A first analog-to-digital channel processes the first signal to produce an in-phase and quadrature signals. The second signal is processed by a second analog-to-digital channel to produce a second set of in-phase and quadrature signals. The two sets of in-phase and quadrature signals are used to determine a phase difference between the signal of the device under test and a local oscillator signal associated with the two analog-to-digital channels. The invention is further directed to a direct digital synthesizer that is capable of use within the digital phase detector and in other applications.

Abstract: Delay-locked loops, signal locking methods and devices and systems incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively couples to an external clock signal and to an internal test signal. The phase detector adjusts a delay line based upon the phase differences of a feedback signal and the external clock signal. The timer circuit switches the internal test signal into the forward delay path and measures the time of traversal of the internal test signal around the forward delay path and the feedback delay path and generates a time constant for configuring the phase detector's update period. The phase detector is thereafter able to stabilize at an improved rate.

Abstract: A test signal to be supplied to a driver section when the driver section is subjected to an operation test is generated by a test circuit. In the test circuit, the test signal can be generated by a burn-in control circuit in accordance with a clock signal TESTCK supplied from an outside source.

Abstract: The invention is directed to a digital phase detector that comprises a splitter and phase shifter to receive a signal of a device under test and produce a first signal that is substantially identical to the received signal and a second signal that is phase shifted relative to the first signal. A first analog-to-digital channel processes the first signal to produce an in-phase and quadrature signals. The second signal is processed by a second analog-to-digital channel to produce a second set of in-phase and quadrature signals. The two sets of in-phase and quadrature signals are used to determine a phase difference between the signal of the device under test and a local oscillator signal associated with the two analog-to-digital channels. The invention is further directed to a direct digital synthesizer that is capable of use within the digital phase detector and in other applications.

Abstract: Method and apparatus for determining delay of a circuit. A clock signal is provided to a variable delay and then to the circuit. The clock signal obtained from the circuit is provided to a data register, such as a flip-flop, as a clock input. The clock signal is provided to the flip-flop as a data input. Output of the data register is provided to a controller to incrementally adjust phase shift until the data input and clock input are substantially aligned in phase. All incremental adjustments in phase shift are counted to provide an indication of delay of the circuit.

Abstract: A device for identifying a wire break between an electrical connection of a digital output and a load includes an evaluation module connected to the electrical connection and a voltage limiter module also connected to the electrical connection for co-determining a voltage value which is present at the evaluation module in the event of the wire break.

Abstract: A frequency measuring device can measure the frequency of a noisy power system at high speed. The system voltage is measured at timings obtained by equally dividing one reference-wave period. Voltage vectors are calculated which have tip ends, each voltage vector consisting of a real part of a first measured voltage and an imaginary part of another voltage measured at timing 90 degrees before the first measured voltage. The length of a chord connecting tip ends of adjacent voltage vectors is calculated. A voltage root-mean-square value is calculated from voltages measured between two timings spaced from each other by the one reference-wave period. Chord lengths obtained between two timings spaced from each other by the one reference-wave period are summed. Based on the total of the chord lengths and the voltage root-mean-square value, there is calculated a phase angle between two adjacent voltage vectors, from which the system frequency is calculated.

Abstract: A method for testing a core power distribution system for an integrated circuit chip which includes arranging a plurality of experiments for an integrated circuit chip, performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances, generating a schmoo diagram for each of the plurality of experiments, and analyzing the schmoo diagrams to determine whether the core power distribution system functions is acceptable at a particular frequency.

Abstract: An electronic meter includes a sensing circuit for sensing voltage and current values of a waveform, an analog-to-digital converter for converting the sensed voltage and current values to digital voltage and current values, a digital filter for delaying one or both of the digital voltage and current values to compensate for a phase shift error in the sensing circuit, and a computation circuit for computing one or more parameters of the waveform in response to the phase compensated voltage and current values. The electronic meter may be calibrated by applying to the meter a test waveform having a known phase shift, measuring the phase shift using the electronic meter, determining a phase shift error based on the difference between the known phase shift and the measured phase shift and determining digital filter coefficients to produce a digital filter delay that corresponds to the phase shift error.

Abstract: A circuit for measuring absolute spread in capacitors implemented in planary technology. A charge pump supplying a charge current to an internal capacitor (Cint) is used, the voltage across the internal capacitor (Cint) being coupled through a comparator for comparing the voltage with first and second threshold levels. A bistable multivibrator reverses the direction of the charge current, to charge the internal capacitor (Cint) when the voltage decreases below the second threshold level, and to decharge the internal capacitor (Cint) when the voltage increases above the first threshold level. The charge current is determined by a reference voltage that is provided across an external resistor (Rext), the first and second threshold levels defining a voltage range being proportional to the reference voltage. An output signal of the bistable multivibrator is coupled to frequency measuring means to compare the repetition frequency thereof with a reference frequency.

Abstract: A wireless alternating current phasing voltmeter multimeter that uses modular wireless based components in order to provide indications of highly desirable parameters of interest, such as AC voltage, phase rotation, and the number of degrees difference between phases. The use of wireless technology eliminates the cable customarily used to interconnect the test probes and the metering circuitry, which may effectively eliminate the concern regarding the distance separating the power lines that are to be tested. The wireless alternating current phasing voltmeter multimeter has two base modules, but, because of the flexibility of the design, modifications can be readily incorporated into the present invention modules that allow for numerous operational and functional permutations to be implemented in order to meet an individual user's needs including the use of one of the modules as a hand-held base module that can be remotely located away from the electrical power lines (or test points).

Abstract: An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

Abstract: A general method is provided to achieve frequency conversion in an all-digital frequency conversion device that produces an output signal having a selectable phase and frequency that is substantially synchronous with the input signal to be converted. A multiplicity of time-shifted signals is generated, and appropriate ones are selected to set and reset an output signal. An apparatus, computing system, and software product that implement the present invention are also provided.

Abstract: A servo controller for correcting a read position of a head when reading data recorded on a recording medium. In accordance with the amplitude ratio of data signals read from each segment of a servo section defined on a recording medium, the servo controller generates an AGC signal corresponding to the next segment before reading the next segment. The data signal read from a phase detection segment of the servo section is amplified to an amplitude greater than the predetermined determination range. The amplified data signal is converted to a two-value digital signal in accordance with the determination range. The phase used during servo control is calculated in accordance with the digital signal.

Abstract: According to an embodiment of the present invention, an input signal is provided to an oscillator, which creates a count signal with a greater frequency than the input signal. The input signal triggers the oscillator to oscillate depending on the value of the input signal. The oscillator output is provided to a counter, which counts the number of oscillations undergone by the oscillator during a single period of the input signal or a number of periods of the input signal, whichever is desired. Since the oscillator frequency is greater than the frequency of the input signal, the oscillator effectively acts like a clock to time the input signal; the counter effectively acts to record the ‘time’ measured by the oscillator (clock). More formally, the counter generates a count value based upon the width of the input signal pulses. The counter output is provided to a decoder, which interprets the count generated by the counter.

Abstract: A circuit switching device or circuit breaker with integrated self-test enhancements is disclosed having separable contacts operable under processor control to control power to a circuit responsive to at least one of a plurality of fault conditions and operable according to a method for testing, including the steps of: controlling the switching device during a sampling cycle, to input one or more operating parameters sensed in the circuit to an A/D converter for measurement wherein the operating parameters enable detection of the fault conditions; determining whether to read a select one of the operating parameters from an output of the A/D converter into a first memory; and reading pre-determined parameter values from a second memory into the first memory during the sampling cycle instead of the operating parameters read from the A/D converter if a self-test has been invoked during the sampling cycle.

Abstract: A phasing and indicator arrangement is provided for switchgear or the like that responds to electrical sources and provides voltage indicator functions, phasing determinations, and self-test features. Phasing provisions are responsive to two or more voltage sensors proximate respective electrical sources to provide an output that represents the phase difference, i.e. time relationship, between the electrical sources as an alternating-current voltage measurable by a voltmeter. The output is relatively independent of the voltage of the electrical sources. The indicator arrangement is operable in a test mode to test the integrity of one or more voltage indicators while clearly identifying that the indicator arrangement is in a test mode. In a preferred arrangement, the indicator arrangement in the self-test mode is powered by a photocell.

Abstract: The present invention provides a wide band IQ splitting apparatus suitable for using in a spectrum analyzer. A quadrature oscillator 30 generates a pair of quadrature signals. An amplitude and phase adjuster 32 receives the quadrature signals and adjusts the balances of the amplitude and the phase between them. An analog splitter 20 mixes an analog IF signal with the pair of quadrature signals for splitting the analog IF signal into analog I and Q signals. First and second analog to digital converters 22 and 24 convert the analog I and Q signals into digital I and Q signals, respectively. A control and processing circuit detects the imbalances of the amplitude and phase between the digital I and Q signals for controlling the amplitude and phase adjuster 32. The amplitude and phase adjuster 32 is previously calibrated. For this first calibration, the analog splitter 20 receives a first calibration signal instead of the analog IF signal.