Abstract: A multiplexer includes a common terminal, a first acoustic wave filter having a first frequency band as a pass band, and having a first input/output terminal connected to the common terminal, a second acoustic wave filter having a second frequency band higher than the first frequency band as a pass band, and having a second input/output terminal connected to the common terminal, an inductance element, and a first capacitance element. The first acoustic wave filter has a parallel resonator of which one end is connected to the first input/output terminal and another end is connected to a ground electrode, and the first input/output terminal is connected to the common terminal via the inductance element, and the first capacitance element is connected between a signal path between the one end of the parallel resonator and the inductance element, and a ground electrode.

Abstract: A timing detection device includes a draw back amount acquiring unit and a detecting unit. The draw back amount acquiring unit is configured to acquire a draw back amount of a received signal with respect to a peak value of the signal. The detecting unit is configured to detect the timing at which the draw back amount acquired by the draw back amount acquiring unit has exceeded a constant value as the timing at which a value of the signal is switched.

Abstract: An industrial process device for monitoring or controlling an industrial process includes a first input configured to receive a first plurality of samples related to a first process variable and a second input configured to receive a second plurality of samples related to a second process variable. Compensation circuitry is configured to compensate for a time difference between the first plurality of samples and the second plurality of samples and provide a compensated output related to at least one of the first and second process variables. The compensated output can comprise, or can be used to calculate a third process variable. The third process variable can be used to monitor or control the industrial process.

Abstract: A high frequency delay circuit operable to output a high frequency signal delayed for a desired delay time. The high frequency delay circuit includes: a variable delay circuit operable to receive a reference signal of which a frequency is lower than the high frequency signal, and to output a delay reference signal delayed from the reference signal for the desired delay time in advance; and a multiplier operable to generate the high frequency signal, of which a frequency is a frequency of the delay reference signal multiplied by a predetermined value, and to output the generated high frequency signal at timing according to a phase of the delay reference signal.

Abstract: A semiconductor integrated device provided with a non-scan block being supplied with an input signal and supplying an output signal, and a selector, into which the input signal and the output signal of the non-scan block are input and which selects one of these signals as an externally output signal and outputs it. The selector is controlled such that it selects the input signal of the non-scan block when a scan test is performed and selects the output signal of the non-scan block when a scan test is not performed. Thus, during the scan test it is possible to control the input signal and observe the output signal of the scan block.

Abstract: Two reference voltages and two differential receivers are used to detect low-to-high and high-to-low transitions on an input signal and set a received signal output. One reference voltage is set near but under the electrical high voltage level and the other is set near but above the electrical low voltage level. The reference voltage that is closest to the input signal is designated as the active reference voltage. When the input signal crosses the active reference voltage digital value of the received signal output is changed. When the input signal then crosses the inactive reference voltage, the inactive reference voltage is made the active reference voltage. A dead-time is then waited where input signal crossings of the active reference voltage are ignored. After the dead-time, input signal crossings of the active reference voltage will change the received signal output.

Abstract: A test configuration and a method for testing a digital electronic filter, include feeding back an output of the filter to an input in such a manner that a digital output signal from the filter is applied to the input as a test signal. The test signal is applied to the filter and a response signal is fed back to the input as the next test signal.

Abstract: A pre-conditioner for enabling high-speed time interval measurements in an ATE system having a relatively low-bandwidth pathway between a UUT and a timer/counter includes a frequency divider and a D flip-flop located near the UUT. The frequency divider receives a first input signal from the UUT and produces a first output signal having a frequency equal to 1/N times the frequency of the first input signal. The first output signal connects over the low-bandwidth pathway to a first channel of the timer/counter. The first output signal also connects to the D input of the D flip-flop. The pre-conditioner receives a second input signal from the UUT that drives the CLOCK input of the D flip-flop. The Q output of the D flip-flop supplies a second output of the pre-conditioner. The second output connects over the low-bandwidth pathway to a second channel of the timer/counter.

Abstract: A method and system for partial scan testing of integrated circuits is disclosed. The invention includes determining at least one failed functional block during testing of the integrated circuit. The failed functional block is then logically isolated from the remaining non-failing functional blocks. Scan testing of the remainder of the non-failing functional blocks then occurs to determine the integrity of the remainder of the integrated circuit. The data coming out of the failing functional block is not allowed into the other functional blocks as input data. The invention allows the integrated circuit to be used and sold at a reduced functionality for applications not requiring the failed functional block(s).

Abstract: A method of testing an analog, or mixed analog and digital, circuit designed for operation at a clock frequency multiplexes a plurality of low frequency stimulus signals using a high frequency clock to produce a circuit input signal, applies the input signal to the circuit to obtain a circuit output signal; samples the circuit output signal synchronously with the high frequency clock at a frequency equal to the clock frequency divided by the number of the low frequency signals; stores the samples and measures properties of the signal samples to determine properties of the output signal of the circuit.

Abstract: A testing device for testing dynamic characteristics of an electronic circuit using serial transmissions. The circuit includes a multiplexing device and a demultiplexing device for implementing a serial link in the component or circuit. The testing device includes a transmitter for transmitting binary signals to the multiplexing device, a receiver for receiving binary signals from the demultiplexing device, and a link for selectively providing a coupling between the transmitter and the receiver. Additionally, a clock generator delivers a first clock signal to the transmitter and a second clock signal, which has a different frequency than the first clock signal, to the receiver. In one preferred embodiment, the clock generator includes a single programmable-frequency oscillator and a variable delay circuit. The programmable-frequency oscillator delivers the first clock signal and the variable delay circuit delays the first clock signal to deliver the second clock signal.

Abstract: An apparatus includes connectors and a circuit. Each connector is capable of receiving and coupling a different voltage regulator module to a circuit board. The circuit is coupled to the connectors to form a multiple phase voltage regulator system out of the voltage regulator modules that are received by the connectors. The circuit establishes the number of phases of the multiple phase voltage regulator system based on the number of voltage regulator modules that are received by the connectors.

Abstract: A method and circuitry for an undisturbed scannable state element. A scannable state element, implemented in a scan chain for testing an integrated circuit, includes both a dual-ported flop circuit and a shadow flop circuit. The dual-ported flop circuit includes both a master cell and a slave cell, while the shadow flop includes only a master cell, and utilizes the slave cell of the dual-ported flop. During scan shifting, scan data is shifted through the shadow flop and the slave cell of the dual-ported flop, bypassing the master cell. Since the data output of the dual-ported flop originates in the master cell, the state of the data in the dual-ported flop is not disturbed by the scan. Scan data may also be latched into the master cell from the scan chain or from the master cell into the scan chain through a scan data output in the slave cell.

Abstract: A signal-testing device used with a tester for testing a first signal and a second signal includes a selected signal generator receiving first signal and second signal for generating a selected signal the state of which is changed when first signal and second signal are in specific states, and a signal selector for selectively outputting one of first and second signals in response to the selected signal state. The present invention also provides a signal-testing method including steps of a) generating a selected signal having a plurality of pulses in response to a first signal and a second signal, b) obtaining a plurality of time differences between times when two inter-adjacent respective pulses respectively reach a specific voltage, c) obtaining a plurality of absolute values between two inter-adjacent respective time differences, and d) obtaining a phase difference by dividing by 2 an average value of the absolute values.