Abstract: A hardware controller of a device under test (DUT) communicates with a PCIe controller to fetch test data and control test execution. The hardware controller also communicates with a JTAG/IEEE 1500 component to set up the DUT into various test configurations and to trigger test execution. For SCAN tests, the hardware controller provides a high throughput direct access to the on-chip compressors/decompressors to load the scan data and to collect the test results.

Abstract: Systems and techniques are described for producing a synthesized IC design that includes design-for-testability (DFT) circuitry. A register-transfer-level (RTL) representation of an IC design can be received, wherein the RTL representation includes functional logic. Next, DFT logic can be added to the RTL representation, and DFT placement guidance for placing the DFT logic can be generated. Synthesis can be performed on the RTL representation to obtain the synthesized IC design, wherein during synthesis, (1) the functional logic and the DFT logic can be placed, wherein the DFT logic is placed based on the DFT placement guidance, (2) scan chains can be inserted and placed, and (3) the DFT logic can be electrically connected with the scan chains.

Abstract: The present disclosure, related to the technical field of fingerprint identification, discloses a ramp wave generation circuit, a digital-to-analog conversion circuit, and a fingerprint identification system. The ramp wave generation circuit comprises: an integrating circuit, configured to output a ramp wave signal; a signal regulation circuit, comprising a feedback control loop and a transconductance amplifier connected in series, wherein the feedback control loop monitors the ramp wave signal output by the integrating circuit, and outputs a regulation control signal to the transconductance amplifier, the transconductance amplifier corrects, according to the regulation control signal, a ramp wave signal output by the integrating circuit within a next period; and a voltage generation circuit, configured to respectively output a reference voltage signal to the integrating circuit and the signal regulation circuit.

Abstract: A method to detect a gas absorption line that includes alternately transmitting and sweeping two radio frequency (RF) signals through an absorption cell, wherein the two RF signals are transmitted at different frequencies separated by a range and are swept across a span of frequencies in a microwave and millimeter wave regions of a frequency spectrum. Receiving the RF signals by a receiver and analyzing the received signals by a closed loop system for relative absorption by a gas due to an absorption line of the gas in the span of the swept frequencies. Detecting the absorption line of the gas when the two RF signals straddle the gas absorption line and the relative absorption by the two RF signals is equal.

Abstract: A capacitance sensing circuit comprises a capacitive device having a capacitance, the device initially being at a first voltage level. The capacitance sensing circuit is capable of applying one or more pull-up currents to the device during one or more corresponding pull-up periods of time, for changing the first voltage level into one or more corresponding pull-up voltage levels; applying a measurement current to the device; and measuring a measurement period of time, during which one of the pull-up voltage levels changes into a second voltage level. A method of sensing a capacitance of a capacitive device comprises applying a first voltage to the device; applying one or more pull-up currents during corresponding pull-up times, for changing the first voltage into corresponding pull-up voltages; applying a measurement current; and measuring a time, during which one pull-up voltage changes into a second voltage.

Abstract: A capacitance-sensing device including a current-to-voltage converter and an analog-to-digital converter is described. A sense element is coupled to an input of the current-to-voltage converter. The current-to-voltage converter is configured to convert current changes in the coupled sense element to an output voltage and to maintain a constant voltage at the input. The analog-to-digital converter is configured to convert the output voltage generated by the current-to-voltage converter to a digital value.

Abstract: A capacitive touch sensing device by detecting induced electric field includes a differential amplifier, a resistor and a signal judgment circuit. The differential amplifier is electrically connected to a touch sensor. The resistor is electrically connected to a first input end and a second input end of the differential amplifier. The signal judgment circuit is electrically connected to an output end of the differential amplifier. As the touch sensor receives an induced electric field signal, the induced electric field signal is amplified by the differential amplifier and the signal judgment circuit determines whether the amplified induced electric field signal is a touch input.

Abstract: Systems provide for a test system for capacitors in a digitally controllable oscillator (DCO). The system includes: capacitor toggling logic configured to switch on and off a selected one of the capacitors at a modulation frequency; a tone generator configured to generate a tone; a mixer configured to receive the tone and an output carrier signal from the DCO while the capacitor toggling logic is switching the selected one of the capacitors on and off and to output an intermediate frequency signal having FM sidebands based on the modulation frequency and relative capacitor size; and an evaluation circuit configured to evaluate a frequency deviation associated with the selected one of the capacitors based on at least one of the FM sidebands.

Abstract: Methods and apparatus to detect voltage conditions of power supplies are disclosed. An example power supply monitor to detect fault conditions in a power supply includes a capacitive element communicatively coupled to the power supply, the capacitive element being configured to change state between a collapsed state and an open state in response to the power supply having a first voltage associated with a first fault condition of the power supply; a detector communicatively coupled to the capacitive element to detect a voltage spike generated from the state change of the capacitive element; and a signal generator to generate a fault signal in response to the voltage spike to indicate the power supply being in the first fault condition.

Abstract: A method is provided to improve the usability of Design-For-Testability Synthesis (DFTS) tools and to increase the design process productivity. The method comprises receiving a list of testability and design impact analysis functions, to be performed on the circuit, also referred to as a device under test (DUT). The impact analysis leads to the creation of logical transformations, which can be selected by a user with one or more available transformation methods from a list including, but not limited to, boundary scan test logic insertion, scan test logic insertion, memory BIST (built-in-self-test) logic insertion, and logic BIST logic insertion, and scan test data compression insertion logic insertion.

Abstract: A galvanically isolated signal conditioning system includes a signal conditioning circuit on an integrated circuit chip; a flying capacitor; and a galvanically isolating MEMS switching device on an integrated circuit chip for selectively switching the flying capacitor from across a pair of input terminals in one state to across the input terminals of the signal conditioning circuit in another state.

Abstract: A detecting fixture for detecting a capacitor with leakage current among a capacitor group in parallel connection includes a reference voltage generator, an impedance converter, a comparator and a display unit. Wherein, the reference voltage generator is used for outputting a first voltage, the impedance converter is used for converting the impedance of the capacitor group in parallel connection into a second voltage and the comparator is respectively coupled with the outputs of the reference voltage generator and the impedance converter for comparing the first voltage with the second voltage. The display unit is coupled with the output of the comparator, wherein the second voltage is altered by heating a capacitor among the capacitor group in parallel connection and the comparator outputs a voltage difference in response to the altered second voltage, so that the display unit is able to indicate whether or not the corresponding capacitor has leakage current.

Abstract: A circuit to characterize the matching of energy-storage components is provided. The circuit includes a linear resistor and a power source. The circuit is electrically connected to two serially connected energy-storage elements, for example, a pair of capacitors. The matching between the two capacitors can be evaluated by measuring the slopes of a function relating the input and the output voltageof the circuit.

Abstract: The electronic monitoring circuit for monitoring one of a group of series-connected capacitor units in an intermediate circuit in order to detect short-circuiting of one of the capacitor units includes a device for deriving a reference voltage (14) from an intermediate-circuit voltage (L(+), L(?)) applied across the series-connected capacitor units (1, 2), a device for generating a control signal consisting of a voltage difference between the reference voltage (14) and a junction voltage at a junction (13) between two capacitor unit (1, 2) and a device for generating an error signal when said voltage difference falls below or exceeds an activation threshold voltage thus indicating that one of the capacitor units (1,2) has been short-circuited. The activation threshold voltage corresponds to a breakdown voltage of a zener diode provided in the monitoring circuit.

Abstract: Transistors (12a, 12b) turn on and off with mutually opposite phase input signals. Capacitors (16a, 16b) discharge when the transistors (12a, 12b) turn on, and capacitors (16a, 16b) are charged by constant current from constant current sources (18a, 18b) when the transistors (12a, 12b) turn off. As a result, a gradually rising voltage is obtained at the positive input ends of comparators (14a, 14b) while the input signals are L. By comparing this with fixed voltages of reference sources (20a, 20b), signals having rise timing shifted from input signals by 90° are obtained. The outputs of the comparators (14a, 14b) are mutually shifted by 180°, and at the rise of these outputs, an RS flip-flop (22) is set and reset so that signals delayed in phase by 90° with respect to the input signals are obtained at its outputs.