Abstract: A logic inverter with over-current protection according to one embodiment includes a transistor, an input signal line coupled to a gate terminal or base region of the transistor, an output signal line coupled to a drain terminal or collector region of the transistor, a power supply line coupled to the drain terminal or collector region of the transistor, and a feedback resistor between a source terminal or emitter region of the transistor and ground.

Abstract: Each of a plurality of inverters includes: a first transistor having one end connected to a first terminal; and a second transistor having one end connected to a second terminal and the other end connected to the other end of the first transistor. The first transistors included in the inverters located at either odd-number orders or even-number orders counted from an input terminal side of an inverter chain circuit become conductive when a pre-charge signal has a first state to pre-charge the other end of the first transistors, and become non-conductive when the pre-charge signal has a second state.

Abstract: A circuit includes E-mode transistors with gate-source junction, a D-mode transistor with gate-source junction. A component generates a voltage drop between the source of the D-mode transistor and the drain of an E-mode transistor provided as a signal output. A connection is made between this drain of the E-mode transistor and the gate of the D-mode transistor, and a signal input at the gates of the E-mode transistors.

Abstract: A semiconductor integrated circuit includes an n-channel spin FET including one of a magnetic tunnel junction and a magneto-semiconductor junction, the n-channel spin FET including a gate terminal to receive an input signal, a source terminal to receive a first power supply potential, and a drain terminal connected to an output terminal, a p-channel FET including a gate terminal to receive a clock signal, a source terminal to receive a second power supply potential, and a drain terminal connected to the output terminal, a subsequent circuit connected to the output terminal, and a control circuit which turns on the p-channel FET to start charging the output terminal, then turns off the p-channel FET to end the charging, and supplies the input signal to the gate terminal of the n-channel spin FET.

Abstract: A radiation hardened inverter includes first and second electrical paths between an input terminal and an output terminal. A first PFET is disposed in the first electrical path, and a bipolar junction transistor (BJT) is disposed in the second electrical path. The first PFET is configured to convert a low level signal at the input terminal to a high level signal at the output terminal, and the BJT is configured to convert a high level signal at the input terminal to a low level signal at the output terminal. The radiation hardened inverter includes a second PFET disposed in the second electrical path. The second PFET is configured to provide a path for bleeding excess current away from the BJT. The radiation hardened inverter also includes a current limiting PFET disposed in the second electrical path. The current limiting PFET is configured to limit current flowing into a base of the BJT. The radiation hardened inverter is free-of any NFETs.

Abstract: Circuitry for preventing damage to differentially coupled input JFETs in an integrated circuit amplifier includes first (J2) and second (J4) differentially coupled input JFETs. A first input signal (Vin+) is applied to a gate of the first input JFET (J2), and second input signal (Vin?) is applied to a gate of the second input JFET. Needed amounts of drain current are supplied to the first and second input JFETs. A separator JFET (J1) having a drain coupled to a source of the first input JFET and a source coupled to the source of the second input JFET is operated to control an amount of electrical isolation between the drain and source of the separator JFET so as to limit an amount of reverse bias voltage across a gate-source junction of one of the first and second input JFETs to a value less than a gate-source junction breakdown voltage of that the first and second input JFETs.

Abstract: A flat display device may include a plurality of electrodes arranged in one direction, a first transistor coupled between the plurality of electrodes and a first power source for supplying a first voltage, and a gate driving circuit for supplying a driving voltage to a gate of the first transistor through a push-pull circuit including second and third transistors coupled between second and third power sources for respectively supplying second and third power sources, wherein a resistance formed between the second transistor and the second power source is greater than that formed between the third transistor and the third power source.

Abstract: Circuitry for preventing damage to bipolar transistors in integrated circuit amplifier circuitry during slew-limited operation includes first and second transistors, each having first, second, and third electrodes, a first one of the first and second electrodes of the first transistor being coupled to receive a first signal, and a first one of the first and second electrodes of the second transistor being coupled to receive a second signal.

Abstract: A low power high-speed design for integrated circuits using BiCMOS processes is disclosed. The design uses a first stage including bipolar transistor pairs configured as inputs and drivers for an output. A second CMOS stage is coupled to the first stage in a series-gated configuration and receives clock or data inputs. A third stage is coupled to the second stage and is configured as a current source. The combination results in circuits that can operate at conventional supply voltages of 1.8 volts.

Abstract: An inverter circuit that includes a FET input transistor having a gate, a source, a drain and a FET output transistor having a gate, a source and a drain. The circuit further includes first and second power lines and a constant current source. No transistor other than the input and output transistors is coupled between the input and output terminals. Also, a Bipolar inverter circuit, a FET NAND/AND function circuit, a Bipolar NAND/AND function circuit, a FET differential circuit and a Bipolar differential circuit using the inverter circuit as a building block.

Abstract: The circuit configuration for converting logic levels has a bipolar input stage and a CMOS output stage. The bipolar input stage is equipped to process ECL and CML logic levels. The CMOS-logic output stage is equipped to supply trailing CMOS gates having CMOS logic levels. A difference amplifier includes bipolar transistors, which are connected to a common emitter current source and to separate collector current sources. An input-output feedback CMOS inverter is connected to one of the collectors, and the output of the inverter is coupled to an output node.

Abstract: A logic product circuit having a plurality of transistors arranged in a matrix; a plurality of input terminals; and a single output terminal. The transistors in each column are connected in a line, forming a transistor array, the transistor arrays are connected in parallel between the output terminal and the ground, each of the input terminals is connected to the inputs to the transistors in all the columns, and the transistors to which each input terminal is connected are arranged in different rows.

Abstract: A circuit (100) for generating configurable device signatures is disclosed. The circuit (100) includes a combinatorial logic section (102) that receives a number of information signals, and according to the logic of the information signals, activates one of a number of configuration signals (CONFIG0-CONFIGn). The configuration signals (CONFIG0-CONFIGn) are received by a signature option section (200). The signature option section (200) includes a number of conductive options (210-0 to 210-n and 212) that enable a unique signature (SIG0-SIG15) to be generated in response to each of the configuration signals (CONFIG0-CONFIGn). In the preferred embodiment, the conductive options (210-0 to 210-n and 212) are configured by way of a final metallization layer option.

Abstract: A logic circuit contains a first transistor with a logic signal supplied to the base and having its collector connected to an output node. A second transistor has a collector connected to the emitter of the first transistor and an emitter connected to a reference potential, in which the collector current supplied to the first transistor corresponds to the level of the control signal supplied to the base. A p-channel insulated gate field-effect transistor is connected between the power supply and the output node, and a first bias circuit supplies a bias voltage to the gate of the p-channel insulated gate field-effect transistor as the load. An n-channel insulated gate field-effect transistor is connected between the power supply and the output node and parallel to the p-channel insulated gate field-effect transistor as the load, and a second bias circuit supplies a bias voltage to the gate of the n-channel insulated gate field-effect transistor.

Abstract: A TTL input stage for negative supply voltage systems is described herein which obviates the need for a positive supply and a level shifter. In one embodiment, a first JFET current source, the emitter/collector of a PNP bipolar transistor, and a second JFET current source are connected in series between a control input and a negative supply voltage. The base of the bipolar transistor is connected to ground. At a control input of 2V.sub.be above ground, the PNP transistor has a V.sub.be drop across its emitter/base junction, and each of the identical JFETs has a V.sub.be drop across it. An NPN bipolar transistor, having its base connected to the source of the second JFET and its emitter connected to the negative voltage, is turned on by the V.sub.be drop across the second JFET to provide the output of the TTL input stage. In one embodiment, the TTL input stage is a control circuit for turning an output MOSFET on and off.

Abstract: A differential input buffer operable at power supply voltages below 3.0 V comprises first and second field effect transistors connected between a power supply and a current source as a differential pair in receiving input and input bar signals. Using enhancement mode field effect transistors and heterojunction bipolar transistors for a current source, a power supply voltage Vcc as low as 2 V is possible for circuit operation.

Abstract: A single chip IC includes a bipolar logic, a complementary metal-oxide semiconductor (CMOS) logic, and a level translator which interfaces the bipolar logic with the CMOS logic. The single chip IC comprises a MOS transistor logic, provided in the bipolar logic, for receiving a control signal which controls an operation of the bipolar logic. The control signal issues from the CMOS logic and bypasses the level translator and is applied to the MOS transistor logic.

Abstract: A BiCMOS logic circuit having greater drive and speed at low voltage is provided. The logic circuit includes a switching device which allows the pull-down device of the logic circuit to be driven directly by an input signal without first having to switch a MOS device. The switching device conducts current between the input terminal of the logic device and the pull-down device when the output signal equals a certain value.

Abstract: A novel, high-performance BiCMOS Output Driver. The Output Driver comprises a first pull-up means for pulling high the output of the Output Driver and a pull-down means for pulling low the output of the Output Driver. The first pull-up means includes a bipolar transistor. Coupled in parallel with the first pull-up means is a MOS transistor wherein the gate of the MOS transistor is electrically isolated from the base of the bipolar transistor.

Abstract: A BiMIS circuit has first and second input terminals; first and second output terminals; a first bipolar transistor having a collector receiving a first potential, an emitter connected to the first output terminal, and a base connected to the second output terminal; a second bipolar transistor having a collector connected to the first output terminal and an emitter receiving a reference potential; a first MIS transistor circuit including MIS transistors, connected to the base and the collector of the first bipolar transistor and the first input terminal, and turned on or off depending on a potential of the first input terminal; and a second MIS transistor circuit including MIS transistors, connected to the base of the first bipolar transistor, the second input terminal and the base of the second bipolar transistor, and turned on or off depending on a potential of the second input terminal.

Abstract: An ECL output buffer circuit is constituted by an output buffer circuit main portion and its control circuit. In the output buffer circuit main portion, an output from a differential switch is input to the base of a bipolar transistor (emitter follower). The emitter of the bipolar transistor is connected to an output terminal. A ground potential is applied to the collector of the bipolar transistor. One end of the channel conductive path of a MOS transistor is connected to the base of the bipolar transistor. The other end of the channel conductive path is connected to a power-supply terminal via a constant-current source. The control circuit controls the ON/OFF operation of the MOS transistor and the output level of the bipolar transistor. When the output buffer circuit main portion is to be set in a standby state, the control circuit performs control to set the MOS transistor in an ON state and set the output of the bipolar transistor at low level.

Abstract: A BiCMOS non-inverting buffer circuit (40) with small fan-in capacitance and excellent bipolar output drive. The circuit is ideal for buffering CMOS logic gates from excessive fan-out loads. The circuit also is less complex and more silicon efficient than present buffer circuit implementations, it provides improved transient saturation charge clamping and one buffer macro in an ASIC library can provide extended drive capability to all CMOS logic gates in the library.

Abstract: An ECL-to-CMOS buffer having a single-sided delay comprises an ECL logic gate, a level converter, a plurality of series connected inverters, and a NOR gate. The ECL logic gate receives an ECL level input signal, and provides complementary intermediate level logic signals. The level converter receives the intermediate level logic signals and provides a CMOS level output signal. The NOR gate receives the CMOS level output signal, via the series connected inverters, at an input terminal after a predetermined delay. One of the intermediate level logic signals is also received by the NOR gate at a second input terminal. The CMOS level output signal is delayed for a predetermined time in a low-to-high transition, with no unwanted delay in a high-to-low transition.

Abstract: The logic ensures a smallest achievable propagation delay, lowest achievable supply voltage and low power consumption. Silicon or GaAs can be used. The gain of each gate is preferably low. A local supply voltage E depends on temperature and is provided for each gate or plurality of gates fabricated on a single chip. The main supply voltage V-, whose variations are insignificant, may be as small as -1 V or -0.5 V if bipolar transistors or FETs are used respectively. An inverter may comprise merely one transistor with the source coupled to E. A or a second transistor is coupled between the drain of the first transistor and ground. A binary input voltage is applied to the gate of the first transistor. A binary output voltage appears at the drain and is independent of temperature. An n-input NOR gate is established simply by adding n-1 transistors in parallel with the first transistor.

Abstract: A BiMOS amplifier device includes one stage which can function as both a level-shift and buffer stage and an amplifier stage. The amplifier includes first and second bipolar transistors having their bases connected to first and second input terminals, respectively, having their collectors connected to a point of first potential, and having their emitters connected to the sources of first and second MOS transistors, respectively. The drains of the first and second MOS transistors are connected through respective impedance means to a point of second potential. The gate of each of the MOS transistors is connected to the drain of the other MOS transistor. An output terminal is connected to the drain of at least one of the MOS transistors.

Abstract: A CMOS gate circuit constituting the input stage of a semiconductor logic circuit includes a p channel MOS transistor supplied with current from a first power supply potential Vdd for charging an output signal line to a high level potential, a diode provided between MOS transistor and output signal line, an n channel MOS transistor supplied with current from a second power supply potential Vss responsive to an input signal (Vin) for discharging the potential of output signal line, and a diode provided between MOS transistor and output signal line. An input signal potential applied to input stage has its logic amplitude set to be Vdd-Vf to Vf. Vf represents the forward voltage of the diodes and the second power supply potential is set to be ground potential GND. The input signal potential has its logic amplitude limited, current flows through the diodes in its steady state, and, therefore, the logic amplitude of the signal potential Vout of output signal line becomes Vdd-Vf to Vf.

Abstract: A TTL-CMOS output stage for an integrated circuit includes a bipolar transistor and a MOS transistor series connected between the power supply and ground, their common point forming the output terminal of the TTL-CMOS output stage. A first switching control input channel includes an inverter whose input forms the input terminal of the stage and whose output is connected to the gate of the MOS transistor via a resistor. A second switching control input channel includes a second inverter controlled by the first inverter and whose output is connected to the base of the bipolar transistor by means of a second resistor. The resistors make it possible to limit the transient current and the mean current supplied by the bipolar transistor.