Abstract: An EL display panel including: a pixel array section in which EL display elements whose light emission state is controlled by an active matrix driving system are arranged in a form of a matrix; a first writing control line driving section and a second writing control line driving section configured to drive each writing control line from both sides of the pixel array section; and a first power supply line driving section and a second power supply line driving section configured to drive a power supply line disposed along a direction of a horizontal line from both sides of the pixel array section, the first power supply line driving section and the second power supply line driving section being respectively arranged between the first writing control line driving section and the pixel array section and between the second writing control line driving section and the pixel array section.

Abstract: The present invention relates to semiconductor integrated circuitry, and in particular to such circuitry where one or a plurality of similar or identical operating units are each operable to carry out an operation dependent on a reference signal. One example of such an operating unit is a sub-ADC unit of analogue-to-digital converter (ADC) circuitry, which employs one or more such sub-ADC units to convert samples of an input analogue signal into representation digital values. Where there are a plurality of sub-ADC units, they may each convert samples of an input analogue signal into representative digital values. They may also operate in a time-interleaved manner so that their conversion rate (from sample to digital value) can be lower than the overall sample rate by a factor of the number of sub-ADC units.

Abstract: Radio-frequency (RF) amplifier having active gain bypass circuit. In some embodiments, an amplifier can include a first amplification path implemented to amplify a signal, and having a cascode arrangement of a first input transistor and a cascode transistor to provide a first gain for the signal when in a first mode. The amplifier can further include a second amplification path implemented to provide a second gain for the signal while bypassing at least a portion of the first amplification path when in a second mode. The second amplification path can include a cascode arrangement of a second input transistor and the cascode transistor shared with the first amplification path. The amplifier can further include a switch configured to allow routing of the signal through the first amplification path in the first mode or the second amplification path in the second mode.

Abstract: According to some implementations, a power amplifier (PA) includes a common emitter configured to receive a radio-frequency (RF) signal. The PA also includes a carrier amplifier coupled to the common emitter to form a carrier cascode configuration, a collector of the carrier amplifier provided with a first supply voltage. The PA further includes a peaking amplifier coupled to the common emitter to form a peaking cascode configuration, a collector of the peaking amplifier provided with a second supply voltage greater than the first supply voltage.

Abstract: A layout pattern of a static random access memory, including a first inverter and a second inverter constituting a latch circuit. A first inner access transistor, a second inner access transistor, a first outer access transistor and a second outer access transistor are electrically connected to the latch circuit, wherein the first outer access transistor has a first gate length, the first inner access transistor has a second gate length, and the first gate length is different from the second gate length.

Abstract: Described herein are apparatus, system, and method for improving output signal voltage swing of a voltage mode transmitter (Tx) driver. The Tx driver may use a single power supply which is the same as the power supply of the core processor. The apparatus comprises: a voltage mode driver coupled to an output node; a switching current source, coupled to the output node, to increase voltage swing of a signal on the output node, wherein the signal is driven by the voltage mode driver; and a bias generator to bias the switching current source.

Abstract: A level-shift circuit that operates stably is provided. The level-shift circuit has a function of boosting a first signal having an amplitude voltage between a first voltage and a second voltage to a second signal having an amplitude voltage between a third voltage and the second voltage. The level-shift circuit includes first to eighth transistors. Gates of the third and seventh transistors are electrically connected to a wiring for transmitting a third signal for controlling the amounts of current flowing into one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, one of a source and a drain of the fifth transistor, and one of a source and a drain of the sixth transistor.

Abstract: An EL display panel including: a pixel array section in which EL display elements whose light emission state is controlled by an active matrix driving system are arranged in a form of a matrix; a first writing control line driving section and a second writing control line driving section configured to drive each writing control line from both sides of the pixel array section; and a first power supply line driving section and a second power supply line driving section configured to drive a power supply line disposed along a direction of a horizontal line from both sides of the pixel array section, the first power supply line driving section and the second power supply line driving section being respectively arranged between the first writing control line driving section and the pixel array section and between the second writing control line driving section and the pixel array section.

Abstract: According to some implementations, a power amplifier (PA) includes a common emitter configured to receive a radio-frequency (RF) signal. The PA also includes a carrier amplifier coupled to the common emitter to form a carrier cascode configuration, a collector of the carrier amplifier provided with a first supply voltage. The PA further includes a peaking amplifier coupled to the common emitter to form a peaking cascode configuration, a collector of the peaking amplifier provided with a second supply voltage greater than the first supply voltage.

Abstract: Disclosed are exemplary embodiments of systems and methods for limiting DC voltage. In an exemplary embodiment, a DC voltage limiting circuit generally includes a current supply portion configured to receive a voltage input signal and provide a voltage output signal. A protective portion of the circuit is configured to limit or halt, at least temporarily, operation of the current supply portion based on a magnitude of the voltage input signal. A voltage level control portion is configured to limit the voltage output signal to a predetermined voltage level. In some embodiments, the DC voltage limiting circuit is provided in a climate control system controller.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: The invention relates to a buffer circuit for a receiver device including a transconductance stage and an output stage coupled in parallel to output stages of other channels of the device. The output of the transconductance stage is connected to a base of a bipolar transistor in the output stage. A switch is connected between the base of the bipolar transistor and the emitter of the bipolar transistor. A controller is arranged to switch the buffer circuit from a switch-off mode to a switch-on mode and back. In switch-off mode the switch is switched on, so as to connect the base and the emitter of the bipolar transistor.

Abstract: Apparatuses and methods are disclosed, including an apparatus that includes a first differential amplifier to amplify a difference between an input signal and a reference signal, and a second differential amplifier to amplify the difference between the input signal and the reference signal. The apparatus may further include an inverter circuit to receive an output signal of the first differential amplifier and another inverter circuit to receive an output signal of the second differential amplifier. The apparatus may include an output circuit to combine the outputs of the inverter circuits. The inverter circuits may each include an inverter and a shunt resistance. Additional apparatuses and methods are described.

Abstract: Electronic circuit arrangement for processing binary input values x?X of a word width n (n>1), with a first, second and third combinatory circuit components configured to process the binary input values x to form first, second and third binary output values. The arrangement further includes a majority voter element configured to receive the binary output values and provide a majority signal based on the received binary output values. The second and third combinatory circuit components are designed, as regards faults during processing of the binary input values x in the first combinatory circuit component, to process binary input values of a true non-empty partial quantity X1 of the quantity of binary input values X in a fault-tolerant manner and process binary input values of a further non-empty partial quantity X2 of the quantity of binary input values X different from the true non-empty partial quantity X1 in a fault-intolerant manner.

Abstract: The present invention relates to electronic driver circuits, and more particularly, to low power electronic driver circuits having low manufacturing costs. The present invention is a circuit design that utilizes two transistor types that can be manufactured together thereby reducing the number of processing steps and masks and resulting in lower cost.

Abstract: Configurable analog input circuits are provided. An analog input circuit may include a plurality of configurable input channels, at least one analog-to-digital converter, and at least one processor. Each input channel may include a plurality of switches utilized to select a type of input signal received via the input channel and a set of input terminals selectively utilized to correspond with the selected type of input signal. The at least one analog-to-digital converter may be configured to convert, for each of the plurality of input channels, the selected type of input signal into a digital output. The at least one processor may be configured to control operation of the plurality of switches associated with each of the plurality of configurable input channels.

Abstract: The present invention relates to electronic driver circuits, and more particularly, to low power electronic driver circuits having low manufacturing costs. The present invention is a circuit design that utilizes two transistor types that can be manufactured together thereby reducing the number of processing steps and masks and resulting in lower cost.

Abstract: A low power high-speed design for integrated circuits using BiCMOS processes is disclosed. The design uses a first stage including bipolar transistor pairs configured as inputs and drivers for an output. A second CMOS stage is coupled to the first stage in a series-gated configuration and receives clock or data inputs. A third stage is coupled to the second stage and is configured as a current source. The combination results in circuits that can operate at conventional supply voltages of 1.8 volts.

Abstract: A semiconductor device 1000 may include first and second switch elements 1000A and 1000B formed in first and second element forming regions 16a and 16b of a SOI layer 10a, respectively. The first and second switch elements 1000A and 1000B form a BiCMOS inverter circuit, and each includes a field effect transistor and a bi-polar transistor. A first p-type body region 50a is electrically connected to an n-type source region 120. The first p-type body region 50a is electrically connected to a first p-type base region 220. A second n-type body region 54a is electrically connected to a second n-type collector region 430. A p-type drain region 330 is electrically connected to a second p-type base region 420.

Abstract: The circuit configuration for converting logic levels has a bipolar input stage and a CMOS output stage. The bipolar input stage is equipped to process ECL and CML logic levels. The CMOS-logic output stage is equipped to supply trailing CMOS gates having CMOS logic levels. A difference amplifier includes bipolar transistors, which are connected to a common emitter current source and to separate collector current sources. An input-output feedback CMOS inverter is connected to one of the collectors, and the output of the inverter is coupled to an output node.

Abstract: A logic product circuit having a plurality of transistors arranged in a matrix; a plurality of input terminals; and a single output terminal. The transistors in each column are connected in a line, forming a transistor array, the transistor arrays are connected in parallel between the output terminal and the ground, each of the input terminals is connected to the inputs to the transistors in all the columns, and the transistors to which each input terminal is connected are arranged in different rows.

Abstract: A logic circuit performs a predetermined logic operation by supplying charge to an external load or pulling out charge therefrom according to a combination of the states of a plurality of externally inputted binary signals. The logic circuit includes a first transistor for supplying charge through an output terminal to the external load and a second transistor for pulling out the charge from the load through the output terminal. One of the first and second transistors is constituted by a MOS field-effect transistor having a drain connected to the output terminal. The MOS field-effect transistor has a source receiving an inverse signal inverse to a signal combined for logic operation with an input signal inputted to a gate of the MOS field-effect transistor. The number of the series transistors is reduced, resulting in an increase of the current capacity and in a reduction of the layout area.

Abstract: A logic circuit performs a predetermined logic operation by supplying charge to an external load or putting out charge therefrom according to a combination of the states of a plurality of externally inputted binary signals. The logic circuit includes a first transistor for supplying charge through an output terminal to the external load and a second transistor for pulling out the charge from the load through the output terminal. One of the first and second transistors is constituted by a MOS field-effect transistor having a drain connected to the output terminal. The MOS field-effect transistor has a source receiving an inverse signal inverse to a signal combined for logic operation with an input signal inputted to a gate of the MOS field-effect transistor. The number of the series transistors is reduced, resulting in an increase of the current capacity and in a reduction of the layout area.

Abstract: There is described a BiCMOS switch circuit which allows a low voltage CMOS signal to control a bipolar current source or sink circuit. The circuit includes a current mirror circuit, drawing a constant current through a first bipolar transistor. The collector of that transistor is connected firstly through a second bipolar transistor to a circuit output, and secondly through a CMOS transistor to a positive voltage supply. Depending on an input control signal supplied to the gate of the CMOS transistor, that device can be switched on or off. When the CMOS transistor is switched off, the constant current through the first bipolar transistor is drawn through the circuit output. When the CMOS transistor is switched on, the constant current through the first bipolar transistor is drawn through the CMOS transistor, and the output current is zero.

Abstract: An output driver circuit for coupling a logic circuit to load includes an input node, an output node for coupling to the load and a pull down switch which discharges the output node in response to a signal received at the input node. A current sink circuit includes a feeder transistor which provides current to the control terminal of the pull down switch to render the pull down switch conductive when the voltage at the output node exceeds a first threshold value between a logic high and a logic low. The feeder transistor is charged by a first charging path having a first impedance by which it takes a first time period to render the pull down switch conductive, the first impedance providing a low standby current when the voltage at the output node is below about the first value.

Abstract: A logic circuit contains a first transistor with a logic signal supplied to the base and having its collector connected to an output node. A second transistor has a collector connected to the emitter of the first transistor and an emitter connected to a reference potential, in which the collector current supplied to the first transistor corresponds to the level of the control signal supplied to the base. A p-channel insulated gate field-effect transistor is connected between the power supply and the output node, and a first bias circuit supplies a bias voltage to the gate of the p-channel insulated gate field-effect transistor as the load. An n-channel insulated gate field-effect transistor is connected between the power supply and the output node and parallel to the p-channel insulated gate field-effect transistor as the load, and a second bias circuit supplies a bias voltage to the gate of the n-channel insulated gate field-effect transistor.

Abstract: A CML-CMOS conversion circuit according to this invention includes: a differential circuit in which resistance is connected as load; a first current mirror circuit made up from an n-channel MOS transistor connected to one output of the differential circuit; a second current mirror circuit made up from an n-channel MOS transistor connected to the other output of the differential circuit; a third current mirror circuit made up of two p-channel MOS transistors connected in series to the first current mirror circuit and the second current mirror circuit; and a CMOS inverter that takes as input the output signal of the second current mirror circuit and that outputs a signal at CMOS logic amplitude.

Abstract: A tristate buffer comprises an output block having a pair of NPN bipolar transistor and nMOS transistor between the source line and ground line and connected to each other at the output terminal of the tristate buffer. The tristate buffer has a base potential control block for discharging the base of the NPN transistor and to couple the base to the output terminal of the tristate buffer during an initial stage of the high-impedance state. After the initial stage of the high-impedance state, the base and output terminal are disconnected from each other. A reverse bias overvoltage occurring in the base-to-emitter P-N junction and a current flow during the high-impedance state are eliminated.

Abstract: A BiMOS integrated circuit includes a bipolar transistor for output pull-up; a BiMOS hybrid gate buffer section which comprises a MOS transistor for output pull-down which is longitudinally connected to the bipolar transistor, and a MOS transistor for base drive which comprises an output which is connected a base of the bipolar transistor to drive the base and a gate which is connected to an input; and a logical section which comprises at least a CMOS gate, the logical section having an output which is connected to the input; wherein the base drive MOS transistor has an input capacitance less than that of the output pull-down MOS transistor.

Abstract: First and second inverting stages and first and second decoding stages form in combination a decoder circuit, each of NAND gates of the first and second decoding stages and each of inverters of the first and second inverting stages are implemented by bi-MOS circuits, respectively, and the bi-MOS circuit for the NAND gate and the bi-MOS circuit for the inverter are a high-speed large-current consumption type and a low-speed small-current consumption type so that the decoder circuit achieves a high switching speed without sacrifice of power consumption.

Abstract: A quasi-complementary BICMOS circuit (46) having a clamp circuit that automatically discharges the base-collector of a pull down bipolar transistor (16) when the transistor's (16) collector voltage equalizes its base voltage. The action is immediate and does not depend on the performance of a feedback circuit to provide the timing of the arrival of the clamp signal. The clamp circuit reduces the amount of shallow saturation and quickly discharges shallow saturation after the pull down transition. The degree of shallow saturation is controllable by size selection of the clamp transistor (48). The clamp circuit also discharges the transistor's (16) base voltage to ground potential.

Abstract: A rectifying transfer gate circuit includes first and second field effect transistors and one diode. The source of the first field effect transistor is coupled to a first input node and the gate thereof is coupled to a second input node. Meanwhile, the source of the second field effect transistor is coupled to the second input node and the gate thereof is coupled to the first input node. The diode is coupled between the common drain of the first and second field effect transistors and an output node, so as to increase the speed of the operation in the application circuit utilizing the above rectifying transfer gate circuit.

Abstract: A BiCMOS logic circuit having greater drive and speed at low voltage is provided. The logic circuit includes a switching device which allows the pull-down device of the logic circuit to be driven directly by an input signal without first having to switch a MOS device. The switching device conducts current between the input terminal of the logic device and the pull-down device when the output signal equals a certain value.

Abstract: A Bi-CMOS circuit includes a first bipolar, a second bipolar transistor and a CMOS control unit for performing switching controls of the first and second bipolar transistors on the basis of an input signal applied to an input terminal and for controlling an output signal output via the output terminal on the basis of the input signal. A turn-OFF unit temporality couples the base of the first bipolar transistor to a low-potential side power supply line on the basis of a current flowing in said control means when the first bipolar transistor is turned OFF, so that the first bipolar transistor can be rapidly turned OFF.

Abstract: In order to provide a high speed, stable and low voltage swing logic gate highly applicable to a low-cost BiCMOS process, a BiCMOS logic circuit of the disclosed invention has a pair of MOS transistors, the gates of which are supplied with complementary logic input signals, and the sources of which are coupled together and are supplied with a constant current. The constant current source used may include a bipolar transistor controlled by a reference voltage. Additionally, the constant current source may be a current mirror. The BiCMOS logic circuit of the disclosed invention has a complementary logic output signal. The voltage swing of the complementary logic output signal are determined by the reference voltage and resistance ratio of resistors in the circuit, so that the output voltage swing is independent of power supply fluctuation or temperature change.

Abstract: An ECL stage has its current consumption adapted to its operation speed. For this purpose, the load resistor and the bias current source are adjustable so that the product of the current value of the source by the resistor value is substantially constant.

Abstract: A semiconductor integrated circuit memory device has at least two logic blocks, each logic block including at least two logic units and each logic unit having a number of metal oxide semiconductor field effect transistors (MOS FET's) integrated therein. Bipolar transistors for driving the MOS FET's are selectively arranged between the logic blocks and/or the logic units so as to shorten a critical path of a logic block. The memory device may include a word driver circuit having a bipolar transistor connected to MOSFETs in an address decoder and memory cells of the memory device. The memory device may also include a sense circuit having a bipolar transistor for high speed discharge of a bit line, as well as an output buffer including a bipolar transistor for reducing signal transmission delays in driving a bus.

Abstract: A current switch apparatus includes a bipolar transistor controlled by a reference voltage, a MOS transistor controlled by a logic signal, and a constant current source connected to the bipolar transistor and the MOS transistor.

Abstract: A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5 V. The logic circuit includes a bipolar transistor having a base and its collector-emitter current path coupled between a first power source terminal and an output terminal, together with at least one field effect transistor having its gate responsive to an input signal applied to an input terminal and its source-drain current path coupled between the first power source terminal and the base of the bipolar transistor. A semiconductor switch means is also provided which is responsive to the input signal applied to the input terminal for performing ON/OFF operations complementary to the ON/OFF operations of the bipolar transistor and which has a current path between its paired main terminals coupled between the output terminal and the second power source terminal.

Abstract: A logic circuit has at least one first differential stage made of bipolar transistors operating in linear mode. The first differential stage is connected in a branch of a second differential stage biased by a current source. The second stage and the current source are made of MOS transistors.

Abstract: Architecture for a programmable logic device is described which can operate at substantially faster clock rates than present programmable logic devices. The PLD uses BiCMOS circuit elements to make use of the speed advantages of bipolar technology while also enjoying the limited power consumption of CMOS technology.

Abstract: The semiconductor IC device has a circuit arrangement in which one or more of the circuits, such as on a single substrate, include a totem-pole series connection of bipolar transistors which are driven by arrangements of complementary MOS circuits in a manner such that high-speed logic/switching operation is effected. Arrangements of circuits can also be effected in which the totem-pole series connection is constituted by a PNP transistor, on the power source terminal side, and an NPN or NMOS transistor on the ground or pull-down side thereof. With such configurations, the output signal swing at low operating voltages can be maximized while achieving the same with reduced propagation delay time and low power consumption. The device can also be implemented by circuitry employing capacitance bootstrapping effect as well as IIL (I.sup.2 L) design schemes.

Abstract: The device has, on a single substrate, plural internal circuits, plural input circuits for receiving external input signals and outputting the same to the internal circuit, and plural output circuits for receiving signals outputted from the internal circuits and externally outputting the same, in which at least one of the circuits includes a totem-pole output stage of a first NPN bipolar transistor, on the power supply terminal side, and a second NPN bipolar transistor, on the ground side; a first differentiator circuit for providing pulsing action to the base of the first NPN transistor; a pair of series-connected PMOS transistors for controllably driving the second NPN transistor; and feedback MOS transistors for quickening turn-off of the output stage transistors. The circuit can be effected with a second differentiator circuit in place of the series-connected pair of PMOS transistors.

Abstract: A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

Abstract: An extra large number-of-input complex logic circuit, employed inside a microprocessor for performing a large number of controls and arithmetic operations, is constructed utilizing N(N.gtoreq.2) number of a unit logic circuit each comprising M(M.gtoreq.1) input CMOS logic circuits and one bipolar transistor, whereby respective outputs are integrated to produce one output in response to M.times.N number input signals to provide a high speed, high density integration and low power consumption microprocessor.

Abstract: A BiNMOS inverter and a BiCMOS inverter are utilized. The BiNMOS inverter uses first and second power sources. A potential of the second power source is greater than that of the first power source. The BiNMOS has a first bipolar transistor whose collector being connected to the first power source and whose emitter being connected to an output node, and a first P-type field effect transistor group having at least one P-type field effect transistor through which a drain-source current channel consists of the base of the first bipolar transistor and the second power source based on an input signal transmitted to at lease one input node.

Abstract: The present invention provides BICMOS level shifter having pull-up and/or pull-down transistors at pull-up and/or pull-down portions, which perform a switching operation in response to a reference signal of a stable voltage level, and a BICMOS data output buffer employing the BICMOS level shifters as respective pull-up and pull-down control circuits. Thereby, it is possible to attain low power consumption, high drive capability and high speed operation by bipolar transistors and is also possible to cope with unstable signals.

Abstract: In a push-pull type logic apparatus including a push-pull buffer formed by two bipolar transistors, a control circuit for turning ON one of the bipolar transistors and turning OFF the other, and a voltage clamp circuit for clamping the voltage of the base of at least one of the bipolar transistors, a clamp releasing circuit is provided for releasing the clamp operation of the voltage clamp circuit when the corresponding bipolar transistor is turned ON. Also, a MOS transistor is connected between the collector and emitter of the corresponding bipolar transistor and is turned ON when the corresponding bipolar transistor is turned ON.

Abstract: In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

Abstract: An integrated circuit includes a bipolar logic stage and a CMOS logic stage. The bipolar logic stage includes a common emitter line positioned along a central axis, and a set of bipolar signal drive blocks arranged along the central axis. Each of the bipolar signal drive blocks includes a bipolar transistor with an emitter connected to the common emitter line. Each of the bipolar signal drive blocks further includes an emitter-base reverse voltage protection device. The CMOS logic stage includes a plurality of CMOS logic blocks connected to the set of bipolar signal drive blocks. The CMOS logic blocks are arranged in a compact configuration that is substantially perpendicular to the central axis. The CMOS logic stage performs logical operations on a set of input signals to generate a set of intermediate signals that are driven by the set of bipolar signal drive blocks onto the common emitter line.