Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

Abstract: A radiation hardened single board computer (SBC) includes a processor; static random-access memory (SRAM); non-volatile memory; a field programmable gate array (FPGA); and board-level physical layer interfaces.

Abstract: A system for servicing a request in a distributed computing environment includes a plurality of computing devices configurable to implement a first compute instance group. The first instance group includes a first plurality of compute instances of a provider network. One or more of the computing devices is configured to implement a first network device that is configured to receive a first service request from a client directed to an application and to provide the first service request to each of the first plurality of compute instances. The application is run on each of the first plurality of compute instances.

Abstract: Devices and methods are presented for supplying logic gate signals with a data-independent delay. The method provides a logic gate comprising a pull-up network connected to a pull-down network. The method supplies binary level digital data input signals to the pull-up network and pull-down network, which may be either single-ended or complementary. The pull-up network and pull-down network regulate current through the logic gate with a delay and impedance independent of the data signals. As a result, the logic gate supplies binary level digital logic output signals in response to the data input signals, with a uniform delay. For example, the logic gates may be one of the following: NOR gate, NAND gate, AND gate, or OR gate.

Abstract: Provided is an integrated circuit or the like capable of rapidly correcting erroneous data write and making contents of the RAMs that are in the multiple modular redundancy coincident in a case where a logic circuit performs the erroneous data write to the RAMs while operating logic circuits and RAMs at a high speed. In order to solve the problem, the integrated circuit including logic circuits and RAMs for which data write and data read are performed by the logic circuits includes a multiple modular redundancy logic circuits, a plurality of RAMs respectively connected to the multiple modular redundancy logic circuits, and a RAM access correction unit which compares access signals from the multiple modular redundancy logic circuit to the RAMs to detect an erroneous data write and corrects an error of the RAM.

Abstract: Various embodiments of a robust double node upset tolerant latch in which all internal and external nodes are capable of recovering the previous value after a single event upset are disclosed.

Abstract: Devices and methods are presented for supplying logic gate signals with a data-independent delay. The method provides a logic gate comprising a pull-up network connected to a pull-down network. The method supplies binary level digital data input signals to the pull-up network and pull-down network, which may be either single-ended or complementary. The pull-up network and pull-down network regulate current through the logic gate with a delay and impedance independent of the data signals. As a result, the logic gate supplies binary level digital logic output signals in response to the data input signals, with a uniform delay. For example, the logic gates may be one of the following: NOR gate, NAND gate, AND gate, or OR gate.

Abstract: An object of the invention is to provide a majority circuit which may be manufactured cheaply and easily and may process necessary majority functions for calculation in an interaction model. The majority circuit according to the invention simplifies the processing of the majority function by using a bitonic sort circuit to round the sum of input signals to a power of 2.

Abstract: A plurality voter circuit is disclosed. The plurality voter circuit includes an input array, an output, a control unit, a priority unit and a bypass unit. The output includes an element of the input array with the highest plurality in the input array, which is an output of the bypass unit. The input array is loaded into the control unit and the bypass unit. In addition, the control unit, the priority unit and the bypass unit are electrically connected.

Abstract: Circuits and methods for determining a majority vote from a plurality of inputs. An example circuit includes a voting input stage, a transfer stage, and an accumulating stage. The voting input stage includes at least three input switched capacitors. The transfer stage includes transfer switched capacitors corresponding to the input switched capacitors. The transfer switched capacitors charge a voting capacitor corresponding to each input switched capacitor during a state of a clock signal. The accumulating stage includes accumulating switched capacitors connecting the voting capacitors in series. The accumulating switched capacitors cause the charges of the voting capacitors to be accumulated during an alternate state of the clock signal. The accumulated charge of the voting capacitors represents a majority vote of the input switched capacitors.

Abstract: Embodiments of methods, apparatuses, devices and/or systems for simplifying tree expressions, such as for pattern matching, are disclosed.

Abstract: A register structure in an integrated circuit includes a first register element to store a first copy of data, a second register element to store a second copy of the data, and storage cells to store copies of a parity value of the data. The register structure also includes parity computing circuitry, coupled to the first and second register elements, to generate respective parity values of the first and second copies of the data. The register structure further includes a selection circuit to select between the first and second copies of the data based on a comparison of the respective parity values of the first and second copies of the data to a majority value of the copies of the parity value stored in the storage cells.

Abstract: A prefetch buffer and prefetch method. In one embodiment, the prefetch buffer has a main buffer embodied as a direct-mapped cache, and the prefetch buffer includes: (1) an alias buffer associated with the main buffer and (2) a prefetch controller associated with the main buffer and the alias buffer and operable to cause the alias buffer to store potentially aliasing cachelines of a loop body instead of the main buffer.

Abstract: An integrated circuit device includes a first signal line for distributing a first signal. The first signal line includes a plurality of branch lines, and a leaf node is defined at an end of each branch line. First logic is coupled to the leaf nodes and operable to generate a first status signal indicative of a collective first logic state of the leaf nodes of the signal line corresponding to the first signal.

Abstract: The disclosure relates generally to sequential state elements (SSEs), triple-mode redundant state machines (TMRSMs), and methods and systems for testing triple-mode redundant pipeline stages (TMRPSs) within the TMRSMs using triple-mode redundant SSEs (TMRSSEs). The SSEs, TMRSMs, TMRPSs, and TMRSSEs may be formed as integrated circuits on a semiconductor substrate. Of particular focus in this disclosure are SSEs used to sample and hold bit states. Embodiments of the SSEs have a self-correcting mechanism to protect against radiation-induced soft errors. The SSE may be provided in a pipeline circuit of a TMRSM to receive and store a bit state of a bit signal generated by combinational circuits within the pipeline circuit. More specifically, the SSEs may be provided in a TMRSSE configured to perform self-correction. Also disclosed are methods for using the TMRSSE to test redundant pipeline stages of the TMRSM.

Abstract: An electronic logic circuit uses areal capacitive coupling devices coupled together to process a set of data inputs. Each areal capacitive coupling device can be configured such that a floating gate potential of such device can be altered to at least a first state or a second state in response to receiving an input signal from the set of data inputs, which is coupled electrically to the floating gate. A majority function logic circuit (and other similar circuits) can be interconnected this way using far fewer gates than with a conventional CMOS implementation. Selective logic gates can also be enabled or disabled by configuring them effectively as memory devices.

Abstract: Spin torque magnetic integrated circuits and devices therefor are described. In an example, a spin torque magnetic device for a logic circuit includes a majority gate structure. An output is coupled to the majority gate structure. Three inputs are also coupled to the majority gate structure.

Abstract: An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained in a data word to be transmitted from the memory cells is greater than a threshold number. The digital flag generator circuit includes a first digital stage including a first plurality of binary logic circuits. Each of the binary logic circuits is configured to receive a subset of the data word.

Abstract: Electronic circuit arrangement for processing binary input values x?X of a word width n (n>1), with a first, second and third combinatory circuit components configured to process the binary input values x to form first, second and third binary output values. The arrangement further includes a majority voter element configured to receive the binary output values and provide a majority signal based on the received binary output values. The second and third combinatory circuit components are designed, as regards faults during processing of the binary input values x in the first combinatory circuit component, to process binary input values of a true non-empty partial quantity X1 of the quantity of binary input values X in a fault-tolerant manner and process binary input values of a further non-empty partial quantity X2 of the quantity of binary input values X different from the true non-empty partial quantity X1 in a fault-intolerant manner.

Abstract: The asynchronous circuit includes a fork having at least two branches, each branch being connected to a logic gate so that the logic gate receives as input a branch-ending signal. It further includes a circuit for branching the branch-ending signal at the level of each logic gate to form a branched signal, and a blocking circuit comprising a Muller gate and receiving as input at least one branched signal, the blocking circuit being configured to prevent the propagation of an output signal when the branch-ending signals are in different logic states.

Abstract: A field device for determining or monitoring a process variable in process automation. The field device includes: sensor, which works according to a defined measuring principle; and a control/evaluation unit, which conditions and evaluates measurement data delivered by the sensor along at least two equal valued measuring paths as a function of a safety standard required in a particular safety-critical application. The control/evaluation unit is embodied, at least partly, as a reconfigurable logic chip, with a plurality of partially dynamically reconfigurable, function modules. The control/evaluation unit so configures the function modules in the measuring paths as a function of the defined safety-critical application, that the field device is correspondingly designed to the required safety standard.

Abstract: Electronic apparatus and fabrication of the electronic apparatus that includes detection of the majority of values in a plurality of data bits may be used in a variety of applications. Embodiments include application of majority bit detection to process data bits in a device for further analysis in the device based on the results of the majority bit detection. In an embodiment, such further processing in a memory device after majority bit detection may include data bit inversion prior to outputting the data from the memory device.

Abstract: Data words from a parallel communication channel are interleaved to two majority vote blocks that operate out of phase, using a divided clock signal that has half the clock frequency of the clock signal associated with the parallel communication channel. As one majority vote block evaluates a data word and outputs a result, the other majority vote block is in pre-charge mode awaiting the next data for evaluation.

Abstract: A processor based system with at least one processor, at least one memory controller and optionally other devices having bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.

Abstract: A method for protecting an electronic circuit having at least one output against external radiation includes functionally duplicating the electronic circuit and linking the outputs of the electronic circuit and the duplicated electronic circuit to homologous inputs of at least functionally equivalent combinatorial or sequential elements. The homologous outputs of all the combinatorial or sequential elements are linked together. The electronic circuit can be duplicated multiple times.

Abstract: This disclosure describes voting circuits where an output is generated based on a plurality of inputs. A first plurality of logic paths connects the output to a high voltage. Each logic path of the first plurality of logic paths includes two transistors. A second plurality of logic paths connects the output to the low voltage. Each logic path of the second plurality of logic paths comprises two transistors. Based on N or N?1 of the inputs agreeing, the output is driven to either the low voltage or the high voltage via a subset of logic paths of the first and second plurality of logic paths.

Abstract: A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.

Abstract: A system and method for radiation-tolerant level shifting are disclosed. In some embodiments, an integrated circuit may include a plurality of level shifters, where each of the plurality of level shifters configured receive a same logic level in a first voltage domain and to output candidate logic levels in a second voltage domain, and where at least one of the candidate logic levels subject to being different from another one of the candidate logic levels. The integrated circuit may also include a voting circuit coupled to the plurality of level shifters, where the voting circuit is configured to evaluate the candidate logic levels and output a selected logic level based, at least in part, upon the evaluation.

Abstract: A system for protecting an input/output (I/O) pin of an integrated circuit device (IC) from single event transients is disclosed. The system includes a first delay circuit that is configured to delay a clock signal from the clock source by a first predetermined amount of time, and a second delay circuit that is configured to delay the clock signal by a second predetermined amount of time. The system further includes a first register that is clocked by the clock signal, a second register that is clocked by the clock signal delayed by the first predetermined amount of time, and a third register that is clocked by the clock signal delayed by the second predetermined amount of time. The system also includes voter circuits, where each voter circuit is configured to receive a first data signal from an output of the first register, a second data signal from an output of the second register, and a third data signal from an output of the third register.

Abstract: A semiconductor device according to a first aspect of the present invention includes: a first circuit that outputs a first output value having a majority of output values received from N (N is three or more odd numbers) pieces of data hold circuits receiving a same input value; and a second circuit that outputs a second output value which is less than the majority of output values received from the N pieces of the data hold circuits.

Abstract: This disclosure describes voting circuits where an output is generated based on a plurality of inputs. A first plurality of logic paths connects the output to a high voltage. Each logic path of the first plurality of logic paths includes two transistors. A second plurality of logic paths connects the output to the low voltage. Each logic path of the second plurality of logic paths comprises two transistors. Based on N or N?1 of the inputs agreeing, the output is driven to either the low voltage or the high voltage via a subset of logic paths of the first and second plurality of logic paths.

Abstract: Electronic circuit arrangement for processing binary input values x?X of a word width n (n>1), with a first, second and third combinatory circuit components configured to process the binary input values x to form first, second and third binary output values. The arrangement further includes a majority voter element configured to receive the binary output values and provide a majority signal based on the received binary output values. The second and third combinatory circuit components are designed, as regards faults during processing of the binary input values x in the first combinatory circuit component, to process binary input values of a true non-empty partial quantity X1 of the quantity of binary input values X in a fault-tolerant manner and process binary input values of a further non-empty partial quantity X2 of the quantity of binary input values X different from the true non-empty partial quantity X1 in a fault-intolerant manner.

Abstract: New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.

Abstract: The present disclosure relates to methods and systems for data tag control for quantum dot cellular automata (QCA). An example method includes receiving data, associating a data tag with the data, communicating the data tag along a first wire-like element to a local tag decoder, reading instructions from the data tag using the local tag decoder, communicating the instructions to a processing element, communicating the data along a second wire-like element to the processing element, and processing the data with the processing element according to the instructions. A length of the first wire-like elements and a length of the second wire-like element are approximately the same such that communication of the instructions and the data to the processing element are synchronized.

Abstract: A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.

Abstract: A method of ACM acquisition/confirmation of a plurality of logic signals SI(i) combines a loop for the single confirmation processing for all the sampled signals, with a sequential sampling of these signals. On each sampling, the confirmation loop processes the current sampled signal SI(i), in order to decide on the updating of an output register Qs(i) with the current sampled state Sk, depending on whether or not it is confirmed, either that this state is not to be confirmed, or that this state is to be confirmed, and that the associated confirmation duration ? has elapsed.

Abstract: Self Restoring Logic (SRL) provides for SEU tolerance in high speed circuits. An SRL cell is designed to be stable in one of two internal states. Upon an SEU event, the SRL cell will not transition between the internal stable states and recover from an SEU. SRL circuits are realized with SRL storage cells driving succeeding SRL storage cells directly or through combinational logic such that the corruption of any one internal state variable in the driving SRL cell and it's the associated combinational output logic can affect at most one internal state variable of the succeeding SRL cell. An SRL circuit does not allow propagation of single SEU faults.

Abstract: A redundancy scrubber. The novel scrubber includes fault detection logic for detecting if a circuit has been upset and a mechanism for automatically rewriting data to the circuit when an upset is detected. In an illustrative embodiment, the scrubber corrects for upsets in a circuit comprised of a plurality of redundant circuits, each redundant circuit including a data port for receiving data and a load enable port for controlling when the redundant circuit should load new data. The fault detection logic processes the outputs from each of the redundant circuits and outputs a fault detect signal indicating whether an upset has been detected in one or more of the redundant circuits. The fault detect signal is coupled to the load enable ports, forcing the redundant circuits to immediately reload with corrected data from a voter or with new incoming data when an upset is detected.

Abstract: A semiconductor device according to a first aspect of the present invention includes: a first circuit that outputs a first output value having a majority of output values received from N (N is three or more odd numbers) pieces of data hold circuits receiving a same input value; and a second circuit that outputs a second output value which is less than the majority of output values received from the N pieces of the data hold circuits.

Abstract: Outlier detection methods and apparatus have light computational resources requirement, especially on the storage requirement, and yet achieve a state-of-the-art predictive performance. The outlier detection problem is first reduced to that of a classification learning problem, and then selective sampling based on uncertainty of prediction is applied to further reduce the amount of data required for data analysis, resulting in enhanced predictive performance. The reduction to classification essentially consists in using the unlabeled normal data as positive examples, and randomly generated synthesized examples as negative examples. Application of selective sampling makes use of an underlying, arbitrary classification learning algorithm, the data labeled by the above procedure, and proceeds iteratively.

Abstract: A circuit for handling single event upsets includes a plurality of digital clock manager circuits. A plurality of counters are respectively coupled by their inputs to the outputs of the digital clock managers and a reset controller is coupled to the outputs of the counters. The reset controller is configured to determine an expected value of the counters. In response to an output value of one of the counters being less than the expected value, the reset controller triggers a reset of the digital clock manager coupled to the input of the one of the counters. In response to an output value of one of the counters being greater than or equal to the expected value, the reset controller continues operation without triggering a reset of a digital clock manager.

Abstract: A current mode logic voter circuit includes three two-input split NOR gates. Each two-input split NOR gate receives a corresponding pair of input signals and generates a pair of first output signals responsive to the input signals. A three input split NOR gate is coupled to the two-input split NOR gates to receive the first output signals and generates a second pair of output signals responsive to the first output signals from the two-input split NOR gates. The two and three-input split NOR gates can be formed from current mode logic buffer circuits, and in one embodiment in the three-input split NOR gate the buffer circuits are hardened.

Abstract: A majority voting Viterbi decoder includes a branch metric calculator (BMC) for measuring a difference between a received symbol and a reference symbol and outputting branch metrics from the difference; an add-compare-selection (ACS) unit for determining an optimal path using the branch metrics; a survival path memory unit for outputting decoded symbols by performing decoding based on the optimal path; and a majority voting unit for determining a final decoded symbol by performing majority voting for the decoded symbols output from the survival path memory unit. Accordingly, by adding the majority voting unit, a decoding depth can be reduced without the loss of an encoding gain required in a system, and by reducing the decoding depth, miniaturization is possible, power consumption can be reduced, and a processing delay in a memory can be minimized.

Abstract: A device is disclosed in one embodiment that has multiple identical sets of programmable functional elements, programmable routing resources, and majority voters that correct errors. The voters accept a mode input for a redundancy mode and a split mode. In the redundancy mode, the programmable functional elements are identical and are programmed identically so the voters produce an output corresponding to the majority of inputs that agree. In a split mode, each voter selects a particular programmable functional element output as the output of the voter. Therefore, in the split mode, the programmable functional elements can perform different functions, operate independently, and/or be connected together to process different parts of the same problem.

Abstract: A device is disclosed in one embodiment that has multiple identical sets of programmable functional elements, programmable routing resources, and majority voters that correct errors. The voters accept a mode input for a redundancy mode and a split mode. In the redundancy mode, the programmable functional elements are identical and are programmed identically so the voters produce an output corresponding to the majority of inputs that agree. In a split mode, each voter selects a particular programmable functional element output as the output of the voter. Therefore, in the split mode, the programmable functional elements can perform different functions, operate independently, and/or be connected together to process different parts of the same problem.

Abstract: A method of ACM acquisition/confirmation of a plurality of logic signals SI(i) combines a loop for the single confirmation processing for all the sampled signals, with a sequential sampling of these signals. On each sampling, the confirmation loop processes the current sampled signal SI(i), in order to decide on the updating of an output register Qs(i) with the current sampled state Sk, depending on whether or not it is confirmed, either that this state is not to be confirmed, or that this state is to be confirmed, and that the associated confirmation duration ? has elapsed.

Abstract: Asynchronous nanoelectronic circuits that operate according to principles of quasi-delay insensitive design are described. Circuit or logic elements comprising n-type devices are fabricated in a first n-plane, p-type devices are fabricated in a p-plane, and connections are formed in a routing plane of a compute tile. A state-holding element comprising a selected one of a C-element, a precharge function-block, and a read-write register is described. The state-holding element can hold a value of an output of a logic element during a time when the output is disconnected from a reference voltage. Isochronic forks having an adversary path designed to make state transitions safe are explained.

Abstract: A current mode logic voter circuit includes three two-input split NOR gates. Each two-input split NOR gate receives a corresponding pair of input signals and generates a pair of first output signals responsive to the input signals. A three input split NOR gate is coupled to the two-input split NOR gates to receive the first output signals and generates a second pair of output signals responsive to the first output signals from the two-input split NOR gates. The two and three-input split NOR gates can be formed from current mode logic buffer circuits, and in one embodiment in the three-input split NOR gate the buffer circuits are hardened.

Abstract: A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.

Abstract: A system and method for hardening dynamic logic against single event upset is described. A precharge circuit is hardened and then connected to two pull down networks. The two pull down networks are redundant and, under normal operating conditions, provide substantially the same outputs when receiving substantially the same inputs. The two outputs are then voted to provide an output that is hardened against single event upset. Alternatively, the two outputs may be connected to a next stage of dynamic logic circuits or other circuitry for evaluation.