Reliability Patents (Class 326/9)
  • Patent number: 10572619
    Abstract: A logic element includes a logic block, a clock generator, a clock assigner and at least one sampling element. The logic block implements a logic function on input data to obtain a plurality output data signals. The output data signals are sampled by respective clock signals. The clock generator generates phase-shifted clock signals from a reference clock signal. The clock assigner assigns differing ones of the phase-shifted clock signals to respective output data signals. The sampling element(s) sample the output data signals in accordance with the respective assigned phase-shifted clock signals.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: February 25, 2020
    Assignee: Bar-Ilan University
    Inventors: Itamar Levi, Osnat Keren, Alexander Fish
  • Patent number: 10042788
    Abstract: In a first system among first and second systems being a duplexed system as a path to a storage device, in a first SAS expander including a first port directly coupled to a storage device, buffer-on signifying that buffering is to be performed by the first SAS expander is configured with respect to the first port. In the second system, in a second SAS expander including a second port directly coupled to the same storage device, buffer-off signifying that buffering is not to be performed by the second SAS expander is configured with respect to the second port. By selecting any of the first system and the second system as a path of a command, whether or not the command is to be buffered by the first or second SAS expander directly coupled to a storage device serving as a destination of the command is determined.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: August 7, 2018
    Assignee: HITACHI, LTD.
    Inventors: Yuki Kotake, Tomohisa Ogasawara, Toru Ando, Hidechika Nakanishi, Yukiyoshi Takamura
  • Patent number: 9875165
    Abstract: A system and method of using a baseboard management controller (BMC) to detect a fault on a communication bus. The BMC is connected to and monitors the operation of the communication bus. The BMC automatically detects a communication bus hang and reports bus hang to the host. The BMC attempts to access the communication bus. If the BMC can access the communication bus, the BMC then resets all of the devices connected to the communication bus. The BMC then attempts to contact components connected to the devices. If a component is not accessible via its communication device, the BMC blocks the channel used by the component and reports that information. Once the BMC detects that the component has been removed, the BMC attempts to recover the channel via the I2C/SM bus for use by the computer network.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: January 23, 2018
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chih-Chia Huang, Hao-Yu Chan, Te-Hsien Lai, Tsai-I Yen
  • Patent number: 9590626
    Abstract: Apparatus for identifying stable physically unclonable function (PUF) cells includes an array of PUF cells, a bias control circuit, and a selector circuit. The bias control circuit has a plurality of bias control lines that apply one or more bias control signals to each PUF cell in the array of PUF cells. The selector circuit selects a subset of the PUF cells in the array of PUF cells based on whether outputs of the PUF cells in the array of PUF cells change in response to application of the bias control signals. A corresponding method is also disclosed.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: March 7, 2017
    Assignee: Altera Corporation
    Inventor: Bruce B. Pedersen
  • Patent number: 9450585
    Abstract: An apparatus for selecting a plurality of input signals from a plurality of y signals in a device has a switching matrix with a plurality of n to 1 mulitplexers, wherein each n to 1 multiplexer is assigned to a different input set of n of the y signals wherein a subset of less than n input signals of each set of input signals of each of the n to 1 multiplexers is also a subset of input signals of another n to 1 multiplexer.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: September 20, 2016
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Kevin Lee Kilzer, Sean Steedman, Jerrold S. Zdenek, Vivien N. Delport, Zeke Lundstrum, Fanie Duvenhage
  • Patent number: 9356770
    Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 31, 2016
    Assignee: STMicroelectronics International N.V.
    Inventors: Abhishek Chowdhary, Vivek Uppal, Alok Kaushik, Sajal Kumar Mandal, Tapas Nandy, Sanjeev Chopra
  • Patent number: 9041428
    Abstract: A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: William V. Huott, Kevin W. Kark, John G. Massey, K. Paul Muller, David L. Rude, David S. Wolpert
  • Patent number: 9030227
    Abstract: A multi-chip package may include first and second integrated circuit dies that are each partitioned into multiple logic regions. The logic regions of the first and second dies may be coupled via interconnects. Each integrated circuit die may include at least one spare logic region. Multiple logic groups may be formed with each logic group including logic regions from the first and second integrated circuit dies and the interconnects that couple those logic regions. The logic groups may be evaluated to identify defective logic groups. In response to identifying a defective logic group, the defective logic group may be repaired by configuring the first and second integrated circuit dies to stop using the defective logic group and to use a spare logic group. The spare logic group may include spare logic regions of the first and second dies that are coupled by spare logic region interconnects.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: May 12, 2015
    Assignee: Altera Corporation
    Inventor: David Cashman
  • Patent number: 9013207
    Abstract: In some embodiments, provided is a processor chip including self deactivation logic to deactivate the processor chip after a threshold of qualified events have been monitored.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventors: Yuri I. Krimon, David I. Poisner, Reinhard R. Steffens
  • Publication number: 20150091607
    Abstract: A sequential logic circuit comprising a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a first logical state, and to comprise a latched state upon the clock signal received thereby comprising a second logical state, and a second latch component comprising a data input arranged to receive an input signal, a data output operably coupled to an output of the sequential logic circuit and arranged to output a current state of the second latch component and a clock input arranged to receive a clock signal; the second latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a second logical state, and to comprise a latched state upon the clock signal received thereby c
    Type: Application
    Filed: May 30, 2012
    Publication date: April 2, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Michael Priel, Leonid Fleshel, Anton Rozen
  • Patent number: 8994406
    Abstract: A digital cell for performing a logic operation on a logic input to produce a logic output, includes an evaluation block and a sense-amplifier block, both configured to receive input signals representative of the logic input, and to detect when the logic input and/or input signals validly encode at least one bit. The digital cell is configured to alternate between an evaluate state and a reset state. Upon the digital cell being in the reset state and the detection, the digital cell is switched from the reset state to the evaluate state in which the evaluation block generates a difference in its output signals, and the sense-amplifier block amplifies the difference so that the output signals encode at least one valid bit. Upon the digital cell being in the evaluate state, the digital cell can be triggered to reset to the reset state.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: March 31, 2015
    Assignee: Nanyang Technological University
    Inventors: Joseph Sylvester Chang, Bah Hwee Gwee, Kwen Siong Chong
  • Publication number: 20150084671
    Abstract: The invention relates to a reprogrammable logic device comprising a plurality of elementary patches, each patch comprising: at least one logic block configurable by one or more volatile memory cells storing configuration data; and a memory comprising: a plurality of non-volatile memory cells storing refresh data, each non-volatile memory cell comprising first and second resistance-switching elements, each being programmable so as to have one of a first and of a second resistance value representative of the refresh data; and a read-write circuit adapted for periodically refreshing the configuration data on the basis of the refresh data.
    Type: Application
    Filed: April 24, 2013
    Publication date: March 26, 2015
    Inventors: Guillaume Prenat, Olivier Goncalves
  • Patent number: 8981810
    Abstract: A method, non-transitory computer readable medium, and apparatus for preventing accelerated aging of a physically unclonable function (PUF) circuit are disclosed. For example, the method monitors an environmental condition associated with the physically unclonable function circuit, detects a change in the environmental condition associated with the physically unclonable function circuit, and, in response to the change in the environmental condition, implements a security function for preventing the accelerated aging of the physically unclonable function circuit.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: March 17, 2015
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Austin H. Lesea
  • Publication number: 20150042376
    Abstract: Provided is a nonvolatile resistor network assembly characterized by that: it comprises a first and a second resistor network which are each composed of a plurality of nonvolatile resistive elements connected together; it also comprises a write means for writing into the first and second resistor networks; and writing into the first and second resistor networks is performed by the use of the write means in a manner to make total resistances of respectively the first and second resistor networks different from each other. Further provided is a nonvolatile logic gate which performs logical operation using stored data determined by the total resistances of the respective nonvolatile resistor networks.
    Type: Application
    Filed: September 6, 2012
    Publication date: February 12, 2015
    Applicant: NEC CORPORATION
    Inventors: Ryusuke Nebashi, Noboru Sakimura, Yukihide Tsuji, Tadahiko Sugibayashi
  • Publication number: 20150028918
    Abstract: A packaged component may include an interposer and integrated circuit dies mounted on the interposer. At least one of the dies may be a radiation-hardened integrated circuit die, whereas the remaining dies may be non-radiation-hardened dies. If desired, the interposer may be a radiation-hardened interposer whereas the integrated circuit dies may be non-radiation-hardened dies. The radiation-hardened die or the radiation-hardened interposer may include monitor circuitry that is used to test non-radiation-hardened circuitry of the packaged component. Test results may be stored in a database at the monitor circuitry or transmitted to external devices such as a server. The monitor circuitry may be used to reconfigure failed circuitry or may control multiplexing circuitry in the interposer to functionally replace the failed circuitry. If desired, the monitor circuitry may adjust power consumption of non-radiation-hardened circuitry based on the test results.
    Type: Application
    Filed: July 26, 2013
    Publication date: January 29, 2015
    Applicant: Altera Corporation
    Inventor: Michael D. Hutton
  • Publication number: 20150028919
    Abstract: Disclosed is a wafer-level stacked chip assembly, comprising a plurality of chip layers vertically stacked together with vertically electrical interconnections between the adjacent chip layers realized by TSVs (Through Silicon Via). Each chip layer includes a switching mechanism for selectively bypassing chip coding sequence to deactivate failed IC area and its chip coding sequence, thereby the interconnection relationship among the chip layers can be re-defined and the function and chip code of the failed IC area can be deactivated. Accordingly, any known failed chip in the wafer-level stacking chip assembly can be controlled as a dummy chip to realize the wafer-level chip stacking of non-known good dices with exclusion of failed chip(s).
    Type: Application
    Filed: July 22, 2014
    Publication date: January 29, 2015
    Inventor: Shu-Liang NING
  • Publication number: 20150022233
    Abstract: In one embodiment, the operating range of an over-current detection circuit is extended to higher input voltage levels by providing a reference-voltage generation circuit for the detection circuit with voltage protection circuitry that applies an additional voltage drop to shield other vulnerable transistor devices from the higher input voltages. In addition, bypass circuitry is provided that is inactive at the highest input voltage levels, but actively bypasses at least some of the voltage protection circuitry at relatively low input voltage levels to apply a voltage drop that is sufficient to ensure proper operation of the vulnerable transistor devices at the low voltage levels. In one implementation, the vulnerable transistor devices are NFET devices in a programmable current minor of the reference-voltage generation circuit. In addition, a stiffened voltage divider helps to ensure sufficient voltage drop at the low voltage levels. The protection and bypass circuitry also enable hot-socketing operations.
    Type: Application
    Filed: July 22, 2013
    Publication date: January 22, 2015
    Applicant: Lattice Semiconductor Corporation
    Inventor: Edward E. Miller
  • Patent number: 8928348
    Abstract: A current-mode-logic gate designed to have a first electronic path and a second electronic path. Each electronic path has a pair of transistors. The second electronic path is physically separated and identical to the first electronic path. In operation, a first input signal is transmitted through the first electronic path of the current-mode-logic gate to produce a first output signal. Similarly, a second input signal is transmitted through the second electronic path of the current-mode-logic gate to produce a second output signal.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: January 6, 2015
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Patrick Fleming, Bin Li, Lloyd Brown
  • Patent number: 8922242
    Abstract: Methods and circuits are disclosed for backing up the value of a bi-stable circuit included in a set of programmable logic circuits of a programmable IC. The programmable logic circuits are configured to implement logic circuits having functions based on data values stored in a used portion of a plurality of configuration memory cells. The programmable IC includes a backup control circuit configured to back up and restore the value of the bi-stable circuit. In response to a first signal, a first data value stored by the bi-stable circuit is retrieved and stored in a first one of the plurality of configuration memory cells that is unused in implementing the logic circuits. In response to a second signal, the first data value is retrieved from the first one of the plurality of configuration memory cells and stored in the bi-stable circuit.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: December 30, 2014
    Assignee: Xilinx, Inc.
    Inventors: Chen W. Tseng, Weiguang Lu, Karthy Rajasekharan
  • Publication number: 20140340113
    Abstract: TSV repair circuit of a semiconductor device includes a first chip, a second chip, at least two TSV, at least two data path circuits and an output logic circuit. Each data path circuit comprises an input driving circuit, a TSV detection circuit, a memory device, a protection circuit and a power control circuit. The TSV detection circuit detects a TSV status, the memory device keeps the TSV status, the protection circuit determines whether to pull a first end of the TSV to a ground voltage according to the TSV status, and the power control circuit prevents a leakage current of a power voltage from flowing through a substrate.
    Type: Application
    Filed: July 30, 2014
    Publication date: November 20, 2014
    Inventors: Pei-Ling TSENG, Keng-Li SU, Chih-Sheng LIN, Shyh-Shyuan SHEU
  • Patent number: 8884643
    Abstract: Electronic circuit arrangement for processing binary input values x?X of a word width n (n>1), with a first, second and third combinatory circuit components configured to process the binary input values x to form first, second and third binary output values. The arrangement further includes a majority voter element configured to receive the binary output values and provide a majority signal based on the received binary output values. The second and third combinatory circuit components are designed, as regards faults during processing of the binary input values x in the first combinatory circuit component, to process binary input values of a true non-empty partial quantity X1 of the quantity of binary input values X in a fault-tolerant manner and process binary input values of a further non-empty partial quantity X2 of the quantity of binary input values X different from the true non-empty partial quantity X1 in a fault-intolerant manner.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies AG
    Inventors: Michael Augustin, Michael Goessel, Rolf Kraemer
  • Patent number: 8872575
    Abstract: The present invention discloses a semiconductor device and relates to the semiconductor field. The semiconductor device comprises: a PMOS transistor for processing a input signal, the PMOS transistor comprising a gate and a source, the source being connected to a first voltage source; and a restoring circuit connected to the PMOS transistor for preventing degradation of the PMOS transistor, wherein the restoring circuit makes the gate voltage of the PMOS transistor to be higher than the voltage of the first voltage source, when the input signal is at a high level. According to the semiconductor device of the present invention, a positive bias voltage is applied on the gate of the PMOS transistor through the restoring circuit when the PMOS transistor is turned off, which can accelerate electric parameter recovery for PMOS transistors and therefore improve the performance of PMOS transistors.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 28, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Zhenghao Gan, Junhong Feng
  • Patent number: 8854075
    Abstract: The asynchronous circuit includes a fork having at least two branches, each branch being connected to a logic gate so that the logic gate receives as input a branch-ending signal. It further includes a circuit for branching the branch-ending signal at the level of each logic gate to form a branched signal, and a blocking circuit comprising a Muller gate and receiving as input at least one branched signal, the blocking circuit being configured to prevent the propagation of an output signal when the branch-ending signals are in different logic states.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: October 7, 2014
    Assignee: Tiempo
    Inventors: Marc Renaudin, David Nguyen Van Mau
  • Patent number: 8847621
    Abstract: A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: September 30, 2014
    Assignee: The Boeing Company
    Inventors: Ethan Cannon, Salim Rabaa, Josh Mackler
  • Patent number: 8847622
    Abstract: A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method configures the IC to operate in a user mode with a set of test paths that satisfies a set of evaluation criteria. Each test path includes a controllable storage element for controllably storing a signal that the storage element receives. The method operates the IC in user mode. The method reads the values stored in the storage elements to determine whether the set of circuitry is operating within specified performance limits.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: September 30, 2014
    Assignee: Tabula, Inc.
    Inventor: Brian Fox
  • Publication number: 20140266297
    Abstract: An IC cell designed to assert one of multiple possible output states, each with equal probability, implemented to assert a pre-determined one of the multiple output states based on random variations within the IC cell, such as random process variations. An array of IC cells is configurable to provide a hardware-embedded key upon power-up that is unique to the combination of random variations of selected IC cells, resistant to tampering prior to and during manufacture, and tolerant to aging, instantaneous thermal noise, and environmental variations, such as voltage and temperature fluctuations. The key may be used as, without limitation, a Platform Root Key, a High-Bandwidth Digital Content Protection (HDCP) key, an Enhanced Privacy Identification (EPID) key, and/or an Advanced Access Content System (AACS) key. Also disclosed are techniques to measure stability and stress-harden an IC cell based on output states of the IC cell.
    Type: Application
    Filed: May 8, 2013
    Publication date: September 18, 2014
    Inventors: Sanu K. Mathew, Rachael J. Parker, Ram K. Krishnamurthy
  • Patent number: 8803549
    Abstract: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: August 12, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiki Uemura, Yoshiharu Tosaka
  • Patent number: 8798206
    Abstract: A digital input interface is provided which can be checked for its reliability. The configuration of the circuit on the input side allows a high impedance for a DC input signal and a low impedance for induced AC noise, naturally attenuating any AC induced noise while maintaining the DC input signal. The interface also provides a latent failure detection engine. The latent failure detection engine can open and close an optocoupler on the input side of the interface, which discharges and charges a capacitor on the input side. The time taken for the capacitor to recharge when the optocoupler is re-opened is used to determine if there has been any threshold decay in the interface.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: August 5, 2014
    Assignee: Thales Canada Inc.
    Inventors: Gabriel Cristian Ilie, Virgil Lostun, Daniel Sandu, Ovidiu Stan
  • Patent number: 8786307
    Abstract: Standard cells that include transistors subject to aging as a result of BTI-related operating conditions are identified and replaced with BTI-resistant standard cells, for example. The BTI-resistant standard cells are typically functionally equivalent circuits (such as circuits included in standard cells in a design library) and are arranged to ensure that critical transistors are protected (e.g., by either extending recovery times and/or turning the transistor off in response to a critical edge transition).
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 22, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Palkesh Jain
  • Publication number: 20140197863
    Abstract: A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value.
    Type: Application
    Filed: January 15, 2013
    Publication date: July 17, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William V. Huott, Kevin W. Kark, John G. Massey, K. Paul Muller, David L. Rude, David S. Wolpert
  • Publication number: 20140145753
    Abstract: A through silicon via (TSV) repair circuit of a semiconductor apparatus is provided. The TSV repair circuit includes a first chip, at least one second chip, at least two TSVs, at least two data path circuits, and an output logic circuit. Each data path circuit includes an input driving circuit, a short-circuit detection circuit, a bias circuit, and a leakage current cancellation circuit. The input driving circuit transforms an input signal into a pending signal and transmits the pending signal to a first terminal of the corresponding TSV. The short-circuit detection circuit detects a short circuit between the corresponding TSV and a silicon substrate according to the input signal and the first terminal of the TSV and generates a short-circuit detection output signal. The leakage current cancellation circuit prevents a leakage current produced by a first level voltage from entering the silicon substrate according to the short-circuit detection output signal.
    Type: Application
    Filed: April 21, 2013
    Publication date: May 29, 2014
    Applicant: Industrial Technology Research Institute
    Inventors: Pei-Ling Tseng, Keng-Li Su
  • Patent number: 8736300
    Abstract: In one general aspect, a data collection system for a circuit under test implemented as an integrated circuit or using a programmable logic device is disclosed. It comprises a configurable selection network connected to debug nodes of the circuit. The selection network can be reconfigured after implementation of the circuit to route data from selectable debug nodes in the circuit under test to a controller to allow analysis of the circuit. The data collection system can further comprise a configurable data packer. A method of use of the system associates data from the debug nodes with individual debug nodes of the circuit based on a configuration of the configurable selection network or that of the configurable data packer or both. The method and system of the invention allows for efficient data collection from different sets of debug nodes without having to re-implement the circuit.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: May 27, 2014
    Assignee: Tektronix, Inc.
    Inventors: Bradley R. Quinton, Andrew M. Hughes, Steven J. E. Wilton
  • Patent number: 8723548
    Abstract: A hysteresis-based logic element design for improved soft error rate with low area/performance overhead. In one embodiment, a hysteresis inverter block including one or more pairs of inverters can be coupled to a logic element to adjust a switching threshold of the logic element.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: May 13, 2014
    Assignee: Broadcom Corporation
    Inventors: Karthik Chandrasekharan, Balaji Narasimham, Gregory Djaja
  • Publication number: 20140062526
    Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.
    Type: Application
    Filed: November 12, 2013
    Publication date: March 6, 2014
    Inventors: Steven Hennick Kelem, Jaime C. Cummins, John L. Watson, Robert Plunkett, Stephen L. Wasson, Brian A. Box, Enno Wein, Charles A. Furciniti
  • Publication number: 20140043059
    Abstract: A method for verifying that data is correctly loaded into an individual programmable logic device includes computing a reference digest of the data to be loaded into the individual programmable logic device, loading the data into the individual programmable logic device, computing inside the individual programmable logic device an as-programmed digest of the data that was loaded into the individual programmable logic device, reading the as-programmed digest out of the individual programmable logic device, comparing the as-programmed digest with the reference digest, and verifying the loaded data if the as-programmed digest matches the reference digest, and indicating an error if the as-programmed digest does not match the reference digest.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 13, 2014
    Applicant: Microsemi SoC Corp.
    Inventors: Theodore Speers, G. Richard Newell
  • Patent number: 8638122
    Abstract: A metastability-hardened storage circuit includes at least one inverting circuit. The inverting circuit has a logical input. The logical input of the inverting circuit is split into a pair of physical inputs.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: January 28, 2014
    Assignee: Altera Corporation
    Inventors: Bruce B. Pedersen, Sivaraman Chokkalingam
  • Patent number: 8624622
    Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function, providing for the IC to continue the same functioning despite defects which may arise during operation.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: January 7, 2014
    Assignee: Element CXI, LLC
    Inventors: Steven Hennick Kelem, Jaime C. Cummins, John L. Watson, Robert Plunkett, Stephen L. Wasson, Brian A. Box, Enno Wein, Charles A. Furciniti
  • Patent number: 8624623
    Abstract: According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: January 7, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Navneet Gupta, Prashant Dubey, Kaushik Saha, AtulKumar Kashyap
  • Patent number: 8624624
    Abstract: Power isolation during time intervals of sensitive operations is disclosed. In one embodiment, a programmable chip package includes a programmable chip configured to perform a sensitive operation, and a switch configured to selectively couple a main power source to the programmable chip. The programmable chip package may also include an alternate power source and a controller that is configured to control the switch to decouple the main power source from the programmable chip during a time interval of the sensitive operation, wherein the programmable chip is configured to draw power from the alternate power source during the time interval. The controller is further configured to control the switch to couple the main power source to the programmable chip after the time interval.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: January 7, 2014
    Assignee: Lockheed Martin Corporation
    Inventors: David May, Burton Wolfe
  • Patent number: 8618830
    Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: December 31, 2013
    Assignee: Element CXI, LLC
    Inventors: Steven Hennick Kelem, Brian A. Box
  • Patent number: 8604825
    Abstract: This invention relates to Multiple Interlocked Cells (MICE) design as a hardening technique for CMOS logic gates consisting of two or more redundant nodes with node isolation components. This technique is used to modify existing standard CMOS logic gates or create new complex logic gates using common mask layers existing at ultra-deep sub-micron CMOS foundries. For single node upset immunity in logic or register, a primary cell and a redundant cell are used. For multi-node immunity, the primary cell is combined with two or more redundant nodes are used with physical layout spacing techniques which will insure that a single particle track cannot upset all three nodes simultaneously, and logic circuits built using this technique are immune to upsets in any environment. Circuits built using the MICE technique are also immune to single event transients without requiring the large time delays used in other hardening techniques.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: December 10, 2013
    Assignee: Micro RDC
    Inventor: Paul Eaton
  • Patent number: 8566770
    Abstract: This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modern technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: October 22, 2013
    Inventor: Klas Olof Lilja
  • Publication number: 20130265080
    Abstract: A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.
    Type: Application
    Filed: March 13, 2013
    Publication date: October 10, 2013
    Inventors: Luiz C. Alves, William J. Clarke, K. Paul Muller, Robert B. Tremaine
  • Publication number: 20130234753
    Abstract: A hysteresis-based logic element design for improved soft error rate with low area/performance overhead. In one embodiment, a hysteresis inverter block including one or more pairs of inverters can be coupled to a logic element to adjust a switching threshold of the logic element.
    Type: Application
    Filed: May 23, 2012
    Publication date: September 12, 2013
    Applicant: BROADCOM CORPORATION
    Inventors: Karthik Chandrasekharan, Balaji Narasimham, Gregory Djaja
  • Publication number: 20130229204
    Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.
    Type: Application
    Filed: April 18, 2013
    Publication date: September 5, 2013
    Inventors: Steven Hennick Kelem, Jaime C. Cummins, John L. Watson, Robert Plunkett, Stephen L. Wasson, Brian A. Box, Enno Wein, Charles A. Furciniti
  • Patent number: 8525545
    Abstract: Power isolation during sensitive operations is disclosed. In one embodiment, a programmable chip package includes a programmable chip configured to perform a sensitive operation, and a switch configured to selectively couple a main power source to the programmable chip. The programmable chip package may also include an alternate power source and a controller that is configured to control the switch to decouple the main power source from the programmable chip prior to the sensitive operation, wherein the programmable chip is configured to draw power from the alternate power source during the sensitive operation. The controller is further configured to control the switch to couple the main power source to the programmable chip after the sensitive operation.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: September 3, 2013
    Assignee: Lockheed Martin Corporation
    Inventors: David May, Burton Wolfe
  • Patent number: 8519734
    Abstract: A semiconductor apparatus having first and second chips includes a first operation unit disposed in the first chip, and is configured to perform a predetermined arithmetic operation for an initial code according to a first repair signal and generate a first operation code; and a second operation unit disposed in the second chip, and configured to perform the predetermined arithmetic operation for the first operation code according to a second repair signal and generate a second operation code.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: August 27, 2013
    Assignee: SK Hynix Inc.
    Inventors: Chun Seok Jeong, Jae Jin Lee
  • Patent number: 8513972
    Abstract: A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Luiz C. Alves, William J. Clarke, K. Paul Muller, Robert B. Tremaine
  • Patent number: 8493088
    Abstract: In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: July 23, 2013
    Assignee: Apple Inc.
    Inventor: Vincent R. von Kaenel
  • Publication number: 20130181738
    Abstract: A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Luiz C. Alves, William J. Clarke, K. Paul Muller, Robert B. Tremaine