Abstract: An electronic product having a first capacitor and a second capacitor, where the electronic product includes a semi-conductor substrate having a bottom electrode region of the first capacitor and a bottom electrode region of the second capacitor; a first dielectric layer having a first thickness arranged above the bottom electrode region of the first capacitor; a second dielectric layer having a second thickness arranged above the bottom electrode region of the second capacitor, the first thickness and the second thickness being different; a top electrode region of the first capacitor arranged above the bottom electrode of the first capacitor and above the first dielectric layer; and a top electrode region of the second capacitor arranged above the bottom electrode of the second capacitor and above the second dielectric layer.

Abstract: Various techniques are provided to implement power supply regulation for programmable logic devices (PLDs). In one example, a method includes powering configuration memory cells of a PLD with a first voltage. The method further includes configuring the configuration memory cells while the configuration memory cells are powered by the first voltage. The method further includes operating the PLD while the configuration memory cells are powered with a second voltage higher than the first voltage. The method further includes powering the configuration memory cells with a third voltage lower than the first voltage in response to an indication to transition the PLD to a sleep mode of the PLD. Related systems and devices are provided.

Abstract: Embodiments of the present disclosure relate to a system, a controller, and a method for operating the same. The amount of current that each of multiple power domain modules can use may be determined, and information regarding the amount of usable current may be indicated to each power domain module, thereby controlling the total sum of peak power used by the multiple power domain modules at a specific timepoint to be equal to or lower than a configured value.

Abstract: A display device according to an aspect of the present invention includes a display panel, a driver IC configured to perform image display on the display panel, and a plurality of touch ICs. One of the touch ICs is configured to be driven based on a synchronization signal that is output from the driver IC, and output a synchronization signal for another touch IC. The other touch IC is configured to be driven based on a synchronization signal that is output from the one touch IC.

Abstract: A display control device comprises an output unit that outputs an inverted polarity of an AC signal in a constant cycle, based on a signal of the constant cycle; a stop control unit that stops the reversal of the polarity of the AC signal in the output unit, based on a stop signal; a rewrite control unit for outputting a display data rewrite signal; and a transmission control unit for controlling the rewrite control unit. The stop signal stops the reversal of the polarity of the AC signal during a period in which the display data rewrite signal is output. The AC signal stopped by the stop signal maintains a polarity before the stop of polarity reversal. The output unit inverts and outputs the polarity of the AC signal, based on the signal of the constant cycle, after a period in which the display data rewrite signal is output.

Abstract: The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage.

Abstract: Some embodiments include apparatuses having a first circuit path including drive units coupled in series between a first node and a first additional node, a second circuit path including drive units coupled in series between a second node and a second additional node, each drive unit of the driver units of the first circuit path and the second circuit path including an inverter, and a transmission gate circuit including an input node and an output node coupled to an input node and an output node, respectively, of the inverter; and control circuitry to provide control information to the transmission gate circuit of each of the driver units of the first circuit path and the second circuit path.

Abstract: Disclosed is a transmission gate circuit including a control voltage generating circuit, a high voltage transmission circuit and a low voltage transmission circuit. The high and low voltage transmission circuits are coupled between an input terminal and an output terminal. The control voltage generating circuit generates two voltage groups according to an input voltage of the input terminal and an enable voltage and thereby controls the high and low voltage transmission circuits with the two voltage groups respectively. When the enable voltage is high, one voltage group includes identical voltages while a difference between any of the identical voltages and any voltage of the other voltage group is not higher than a predetermined voltage; when the enable voltage is low, each voltage group includes decremental voltages. The high/low voltage transmission circuit is turned on when the enable voltage is high and the input voltage is high/low.

Abstract: A logic gate includes first and second inputs, first through fourth memristors each having a positive terminal and a negative terminal, and first and second outputs. The memristors are connected in a bridge arrangement: the negative terminal of the first memristor and the positive terminal of the second memristor are connected to the first input; the negative terminal of the third memristor and the positive terminal of the fourth memristor are connected to the second input; the negative terminal of the second memristor and the negative terminal of the fourth memristor are connected to the first output; and the positive terminal of the first memristor and the positive terminal of the third memristor are connected to the second output. A voltage of at least one of the outputs, or the voltage difference between the outputs, corresponds to the result of a logic operation relative to voltages applied to the inputs.

Abstract: A tristate and pass-gate based multiplexer circuit structure is described with full scan coverage capability. The circuit provides deterministic state at its output avoiding high impedance (Z) logic states in silicon. This is realized using a pull-up transistors, pull-down transistors, or through stages of combinational logic combining the multiplexer selects/enables feeding a pull-up or pull-down transistors.

Abstract: A system and method for efficiently receiving analog input signals. In various embodiments, a functional unit includes a switch in its interface logic. The switch receives an analog input signal, and when enabled, conveys the received input signal as an analog output signal. The switch is enabled when the received enable signal is asserted. However, when the power supply voltage is at a logic low level, an output n-type device is disabled while an output p-type device is enabled. A guard p-type device serially connected with the output p-type device is disabled by other devices used to control the guard p-type device. The control devices also ensure that the body terminals of the guard p-type device and other p-type devices receive a logic high level regardless of the power supply value, which prevents forward bias currents in parasitic diodes of the p-type devices.

Abstract: A method operates a bandgap voltage reference circuit that includes a bias circuit for receiving a feedback signal and outputting a bias signal, an amplifier for receiving the bias signal and outputting a first reference signal as the feedback signal, an output circuit for receiving the first reference signal and outputting a second reference signal, and an output switch for outputting the second reference signal as an output signal. The method includes, after powering up the bandgap voltage reference circuit, determining whether the output signal is stable, when the output signal is stable, turning off the output switch; turning off the bias circuit; and turning off the output circuit. The sequential turning off the output switch, the output circuit, and the bias circuit puts the bandgap voltage reference circuit into a sleep mode to save power.

Abstract: A memory device includes a plurality of memory cells, a plurality of word lines, and a word line driver. The word lines are respectively coupled to the memory cells. The word line driver is configured to respectively drive the word lines with word line signals that have varying pulse widths.

Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

Abstract: A computing cell and method for performing a digital XNOR of an input signal and weights are described. The computing cell includes at least one pair of FE-FETs and a plurality of selection transistors. The pair(s) of FE-FETs are coupled with a plurality of input lines and store the weight. Each pair of FE-FETs includes a first FE-FET that receives the input signal and stores a first weight and a second FE-FET that receives the input signal complement and stores a second weight. The selection transistors are coupled with the pair of FE-FETs.

Abstract: A wireless power transfer system includes a power supply side and a power reception side. The power supply side is configured to provide wireless power. The power reception side is electrically connected to the power supply side. The power reception side is configured to receive the wireless power and convert the wireless power into power of a required type. The power reception side includes an adiabatic circuit that operates at AC power and a memory circuit that operates at DC power. The adiabatic circuit includes a first circuit and a second circuit. When the first circuit operates during one of a working period and a waiting period, the second circuit operates during the other one of the working period and the waiting period.

Abstract: A switchable charge pump (SCP) combines a switching element and a charge pump. An SCP can be utilized within an RF circuit to allow the charge pump to be activated or deactivated in the circuit depending on incident RF power level. Multiple SCPs can be utilized to provide a generalized a single-pole N-throw (SPNT) system architecture. In one example, an RF transmit-receive (T/R) system utilizes SCPs to operate in one of three modes: transmit mode, receive mode, or self-selecting terminate mode.

Abstract: An integrated circuit configured to execute multiple operations in parallel is provided. The integrated circuit may be organized into multiple logic sectors. Two or more groups of logic sectors may be executed in an interleaved fashion, where successive groups of logic sectors are activated after a predetermined amount of delay. The integrated circuit may include an array of memory cells. Rows of the memory cells may be accessed in an interleaving manner, where successive rows of memory cells are selected after a predetermined amount of delay. Operating groups of circuit components using an interleaving scheme can help improve operational efficiency while reducing power supply noise without having to increase die area for on-die decoupling capacitance.

Abstract: The present invention teaches how to code a new or existing circuit of wave-pipelining with a buffering function in HDL (Hardware Description Language). The circuit comprises at least one critical path component (CPC) and a wave-pipelined component (WPC). A WPC comprises one Data_position_shifter per CPC, an Input_register_rotator if the circuit has multiple input registers, a Combinational_logic_rotator if the circuit has multiple pieces of combinational logic and a sole output register, a buffering controller and up to three FIFOs. All critical paths provide a first storage, FIFO_1 provides a second storage for output-ready data; FIFO_2 is to store indexes of output registers if the circuit has multiple output registers; FIFO_3 is to store assistant data. Each output register has an attached output register state machine which has three states: idle state, active state and buffered state.

Abstract: According to some aspects, a low-leakage switch is provided. In some embodiments, the low-leakage switch includes a plurality of pass transistors in series that selectively couple two ports of the low-leakage switch and a node biasing circuit coupled to a node between the plurality of pass transistors. In these embodiments, the node biasing circuit may adjust a voltage at the node to change the gate-to-source voltage of the pass transistors and, thereby, reduce the leakage current through the pass transistors when the low-leakage switch is turned off. The node biasing circuit may also include circuitry to reduce the leakage current introduced by the node biasing circuit into the node when the low-leakage switch is turned on.

Abstract: Methods of operating a power supply switching circuit including selecting a first power supply signal for provisioning through the power supply switching circuit to a electronic storage device. A current draw can be detected via the first power supply signal that exceeds a predetermined current limit and a second power supply signal can be coupled to the first power supply signal for provisioning through the power supply switching circuit to the electronic storage device responsive to the current draw exceeding the predetermined current limit.

Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

Abstract: Voltage level shifter (VLS) circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase are disclosed. A VLS circuit is configured to voltage level shift an input signal in a lower voltage domain on an output node in a higher voltage domain. The VLS circuit includes a pre-charge circuit configured to pre-charge the output node in a pre-charge phase. The VLS circuit also includes a pull-up circuit and a pull-down circuit that are configured to pull-up and pull-down the pre-charge phase of the output node, respectively, in an evaluation phase based on a logic state of the input signal to generate the output signal. To mitigate or avoid contention between the pull-up and pull-down circuits in the evaluation phase, the input signal is pre-conditioned such that the pull-down circuit is deactivated in response to the pre-charge phase.

Abstract: A semiconductor device according to an embodiment includes; an N-channel type first MOS transistor having a first drain connected to an input terminal, a first source connected to an output terminal, a first gate insulation film, and a first gate; a P-channel type second MOS transistor having a second drain connected to the input terminal in parallel with the first drain, a second source connected to the output terminal in parallel with the first source, a second gate insulation film whose area is larger than an area of the first gate insulation film, and a second gate; an inverter connected to a control terminal in parallel with the first gate; and a delay circuit disposed between the inverter and second gate.

Abstract: Disclosed is a CMOS inverter, including a first selector, a second selector, and a first transistor, a second transistor, a third transistor and a fourth transistor, which respectively are coupled to the input end of the CMOS inverter through the gates, and all the first transistor, the second transistor, the third transistor and the fourth transistor are coupled to the output end of the CMOS inverter, and sources of the first, the third transistors are respectively and correspondingly coupled to a first output end and a second output end of the first selector, and sources of the second, the fourth transistors are respectively and correspondingly coupled to a first output end and a second output end of the second selector; both the first selector and the second selector receive a first control signal and a second control signal, and both are coupled to the input end.

Abstract: Aspects of the subject technology relate to a system and method for preventing voltage sagging using an Oring-FET in a redundant power supply configuration. Each redundant power supply includes an Oring-FET and a voltage comparator. The voltage comparator receives and compares an input voltage and an output voltage of the Oring-FET during power up. In the event input voltage is less than the output voltage, the Oring-FET is deemed to be operating properly and provides output to a communicatively coupled system bus in response to the input voltage reaching a predetermined voltage threshold level. In the event the input voltage is approximately equal to the output voltage, the voltage comparator assists in preventing inrush current from flowing from the communicatively coupled system bus and prevents voltage sagging on the communicatively coupled system bus when another redundant power supply configuration is providing power to the communicatively coupled system bus.

Abstract: Described is an apparatus which comprises a pass-gate; and a control unit to control gate terminal of the pass-gate according to first availability of first or second power supplies, the control unit including: a voltage detector to detect the second power supply; and a supply switching circuit to generate a local supply for controlling the gate terminal of the pass-gate according to an output of the voltage detector.

Abstract: An integrated circuit with programmable logic is provided. The programmable logic may include multiplexers that are actively used by a custom logic design or unused. To ensure that these multiplexers do not suffer from aging effects when they are not in use, the multiplexers may be provided with aging prevention circuitry. In particular, such a multiplexer may include an input selection stage that is coupled in series with a tristate buffer stage. The input selection stage may include pass transistors or full CMOS transmission gates. The tristate buffer stage may include at least two pairs of output driving transistors, with gates that are selectively shorted when the multiplexer is activated using additional transmission gate circuits. The aging prevention circuitry may include tie-off transistors that are activated to drive the gate-to-source voltages of the output driving transistors to zero volts whenever the multiplexer is not in use.

Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.

Abstract: The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.

Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

Abstract: A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver may be operable in a high impedance mode, where the output of the gate driver is left floating during touch or IFP intervals. In another suitable arrangement, the gate driver may be operable in an IFP reduced stress mode, where a digital pass gate in the gate driver is deactivated during IFP intervals. In yet another suitable arrangement, the gate driver may be operable in an all-gate-high (AGH) power-down mode, where the output of each gate driver in the driver circuitry is driven high in parallel when the displayed is being powered off. These arrangements may be implemented in any suitable combination.

Abstract: An interconnect element includes: a selection circuit for receiving input signals and having a selection output; a half-latch circuit having an input coupled to the selection output, wherein the half latch circuit comprises a pull-up device; and a common bias circuit coupled to the pull-up device, wherein the common bias circuit is configured to supply a tunable bias voltage to the pull-up device.

Abstract: A system for computer-aided design (CAD) of an integrated circuit (IC) uses a computer. The computer is configured to optimize placement, routing, and/or region configuration of the integrated circuit (IC) by maximizing a number of low-power regions in the integrated circuit (IC).

Abstract: Described is an apparatus which comprises a pass-gate; and a control unit to control gate terminal of the pass-gate according to first availability of first or second power supplies, the control unit including: a voltage detector to detect the second power supply; and a supply switching circuit to generate a local supply for controlling the gate terminal of the pass-gate according to an output of the voltage detector.

Abstract: A data holding circuit includes: a latch circuit having a first terminal and a second terminal, a logical value held at the first terminal being changed according to a value to be held by the data holding circuit, and the second terminal holding an inverted logical value of the logical value held at the first terminal; and a storing circuit which stores the logical values held at the first terminal and the second terminal in response to a write signal, and sets the logical values held at the first terminal and the second terminal to the stored logical values in response to a read signal, wherein the storing circuit includes two Magnetic Tunnel Junction elements which are connected in series between the first terminal and the second terminal and in reverse directions to each other.

Abstract: A programmable logic is provided that uses only NMOS pass transistors to pass a true output signal to an internal true node and to pass a complement output signal to an internal complement node. The internal true and complement nodes are cross-coupled through PMOS transistors so that the discharge of one of the internal true and complement nodes switches on a corresponding one of the cross-coupled PMOS transistors to charge a remaining one of the internal true and complement nodes.

Abstract: A semiconductor device includes a first circuit node supplied with a first signal changing between first and second logic levels, a second circuit node supplied with a second signal changing between the first and second logic levels, a third circuit node, a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level, a fourth circuit node supplied with a voltage level being close to or the same as the second logic level, and a second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level.

Abstract: A source driver with reduced number of latch devices includes a master latch device and at least one slave latch device. The master latch device has a first transmission gate, a first inverter, a second inverter, a first enable gate, and a second enable gate. The output of the second inverter is connected to the input of the first inverter. The at least one slave latch device has a second transmission gate, a third inverter, and a fourth inverter. When the first enable gate and the second enable gate receive a latch enable signal and a complementary latch enable signal respectively, the master latch device and the at least one slave latch device are concurrently driven to latch data.

Abstract: A buffer circuit comprising a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal; a first buffer stage coupled to the second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage; and, a pulse generator coupled to control the first buffer stage, the pulse generator being configured to generate a control pulse corresponding to a hold time of the first buffer stage such that the buffer circuit detects a transition of the input signal during the hold time.

Abstract: An electronic device display may have an array of display pixels that are controlled using a grid of data lines and gate lines. The display may include compact gate driver circuits that perform gate driver operations to drive corresponding gate lines. Each compact gate driver circuit may include a first driver stage and a second driver stage. The first driver stage may receive a start pulse signal and produce a control signal. The control signal may be stored by a capacitor to identify a control state of the gate driver circuit. The second driver stage may receive the control signal, a clock signal, and a corresponding inverted clock signal and drive the corresponding gate line based on the received signals. The second driver stage may include pass transistor circuitry that passes the clock signal to the corresponding gate line and may include short circuit protection circuitry.

Abstract: The present invention is related to a circuit arrangement of a gate side fan out area. The circuit arrangement comprises: a first circuit module (T1), which the gate is coupled to a first input end (A), the drain and the source are respectively coupled to a second input end (B) and a Nth gate scan line (N); a first end (1) of the first circuit module is coupled to the first input end, a second end (2) is coupled to the second input end, and a third end (3) is coupled to the N+1th gate scan line (N+1); a first end (1) and a second end (2) of the second circuit module are coupled to the second input end (B), and a third end (3) is coupled to the Nth gate scan line (N); a first end (1) and a second end (2) of the third circuit module are coupled to the second input end (B), and a third end (3) is coupled to the N+1th gate scan line (N+1); a periodic square wave is inputted to the first input end (A), and a gate scanning signal is inputted to the second input end (B).

Abstract: A common mode logic buffer device includes a current source configured to provide a source current. An input stage includes a first MOS transistor pair configured to generate, from the source current and based upon an input differential voltage, a differential current between two output paths. An output stage includes a second MOS transistor pair configured to generate an output differential voltage based upon an effective impedance provided for the each of the two output paths. An adjustment circuit is configured to adjust, in response to a control signal, the effective impedance of the second MOS transistor pair.

Abstract: An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to determine first and second UTS ports of the SRAM UTS for independent connection to first and second on-chip test pads, respectively. The integrated circuit OCP test structure further includes a UTS OCP router connected to the OCP controller and configured to connect the first and second UTS ports of the SRAM UTS to the first and second on-chip test pads, respectively. Methods of operating an integrated circuit OCP test structure and OCP testing of an integrated circuit are also included.

Abstract: Disclosed herein is a power generating circuit including a first transistor in which a second control signal is applied to a control terminal and a first control signal is applied to one end, and which has the other end connected to an output terminal, a second transistor in which the first control signal is applied to a control terminal and the second control signal is applied to one end, and which has the other end connected to the output terminal a third transistor in which one of the first and the second control signals is applied to a control terminal and which has one end grounded, and a fourth transistor in which the other one thereof is applied to a control terminal and which has one end connected to the other end of the third transistor and the other end connected to the output terminal.

Abstract: A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.

Abstract: Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

Abstract: Apparatus and methods for a protective multiplexer, among other things, are provided. In an example, a protective multiplexer circuit can include a first switch that in a first state can be configured to couple an input of a power supply to at least one of first or second signal nodes of a passgate when a first voltage of the at least one of the first or second signal nodes is below a first limit voltage.

Abstract: A ternary T arithmetic circuit, including: a logic 0 gate circuit, a logic 1 gate circuit, and a logic 2 gate circuit. The logic 0 gate circuit includes: a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, and a fifth NMOS. The logic 2 gate circuit includes: a fourth PMOS, a fifth PMOS, a sixth NMOS, a seventh NMOS, and an eighth NMOS. The logic 1 gate circuit includes: a sixth PMOS, a seventh PMOS, a ninth NMOS, a tenth NMOS, an eleventh NMOS, and a twelfth NMOS.

Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.