Field-effect Transistor (e.g., Jfet, Etc.) Patents (Class 326/112)
  • Patent number: 10339988
    Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Shuichi Tsukada
  • Patent number: 10230373
    Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: March 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ah-Reum Kim, Hyun Lee, Min-Su Kim
  • Patent number: 10148319
    Abstract: An NFC (near field communication) device can include a resonance unit and an NFC chip. The resonance unit may communicate with an external device through an electromagnetic wave. The NFC chip can provide output data to the resonance unit, receive input data from the resonance unit, and can reduce a Q factor (quality factor) of the resonance unit when a signal receive operation is performed in a card mode, and can maintain the Q factor of the resonance unit in a reader mode and when a signal transmit operation is performed in the card mode.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: December 4, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Pil Cho, Il-Jong Song
  • Patent number: 10122363
    Abstract: A current source logic gate with depletion mode field effect transistor (“FET”) transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 6, 2018
    Assignee: The United States of America as Represented by the Administrator of National Aeronautics and Space Administraion
    Inventors: Michael J. Krasowski, Norman F. Prokop, Philip G. Neudeck
  • Patent number: 10056134
    Abstract: The present invention discloses a ternary 2-9 line address decoder realized by CNFET, comprising two ternary 1-3 line address decoders of the same structure, nine three-input NAND gates of the same structure and nine inverters of the same structure; the ternary 1-3 line address decoder comprises a 1st CNFET transistor, a 2nd CNFET transistor, a 3rd CNFET transistor, a 4th CNFET transistor, a 5th CNFET transistor, a 6th CNFET transistor, a 7th CNFET transistor, an 8th CNFET transistor, a 9th CNFET transistor, a 10th CNFET transistor and an 11th CNFET transistor; as compared with a 3-8 line address decoder, it features in limited deviation to an output terminals and significant reduction in the number of input terminals, which can minimize the number of ports as packaging, and improve decoding efficiency; furthermore, it is realized by CNFET, which features in low power consumption and less postponement.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: August 21, 2018
    Assignee: Ningbo University
    Inventors: Pengjun Wang, Daohui Gong, Yuejun Zhang, Yaopeng Kang
  • Patent number: 9825709
    Abstract: A traveling wave amplifier includes: a first line to transmit an input signal; an output-side line to transmit an output signal; amplifiers each having an input node and an output node, the input nodes being connected with the first line at first intervals and receiving the input signal, each of the amplifiers amplifying a signal input to the input node and outputting the amplified signal from the output node, the output nodes being connected with the output-side line at second intervals and generating the output signal; a second line to transmit another input signal having a phase opposite to a phase of the input signal; a first resistor having a first end connected with the first line and a second end; and a second resistor having a first end connected with the second line and a second end connected with the second end of the first resistor.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: November 21, 2017
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Taizo Tatsumi
  • Patent number: 9722605
    Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: August 1, 2017
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
  • Patent number: 9697891
    Abstract: A sense amplifier circuit includes a power node having a power node voltage at a power voltage level, a bit line having a bit line voltage, a sense amplifier output, an NMOS transistor and a PMOS transistor coupled in series between the power node and the bit line, and a logic gate configured to generate a sense amplifier output voltage at the sense amplifier output based on the bit line voltage. The NMOS transistor is configured to operate in a sub-threshold region to maintain the bit line voltage at a first level and operate in a region above the sub-threshold region to maintain the bit line voltage at a second level, and the first level is between the second level and the power voltage level.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: July 4, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Bharath Upputuri
  • Patent number: 9667244
    Abstract: A control circuit is provided for controlling the voltage at the gate terminal of a field effect transistor acting as a switch. The voltage, at for example, the source terminal of the transistor can be provided to a low pass filter and is then voltage translated to provide the gate signal. The filtering can be arranged so as to compensate for the effect of parasitic capacitances within the transistor, thereby linearizing its frequency response. The voltage translation can help to limit voltage differences between the gate and channel of the transistor. This can be significant as relatively fast transistors, as might be used in microwave circuits, may fail with relatively modest voltages at their gates.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: May 30, 2017
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Bilal Tarik Cavus, Turusan Kolcuoglu, Yusuf Alperen Atesal
  • Patent number: 9614502
    Abstract: A receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: April 4, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Minhan Chen, Kenneth Luis Arcudia
  • Patent number: 9601167
    Abstract: Disclosed are various embodiments related to dual-gate transistors and associated calibration circuitry. In one embodiment, dual-gate transistors may be configured in a sense amplifier arrangement, and calibration circuitry can be used to adjust an input offset of the sense amplifier. In another embodiment, a reference level voltage utilized in an amplifier with dual-gate transistors can be adjusted during a calibration sequence, and may be substantially unchanged from its nominal value outside of the calibration sequence. In another embodiment, a calibration sequence can be utilized to determine circuit results from a circuit including dual-gate transistors, and to adjust control gates to more closely coincide with expected or desired results. In yet another embodiment, a semiconductor memory device can include a memory array with amplifiers that include dual-gate transistors, as well as associated calibration circuitry.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: March 21, 2017
    Inventor: Michael C. Stephens, Jr.
  • Patent number: 9571067
    Abstract: A semiconductor device includes a signal input circuit suitable for synchronizing an input signal with a clock signal and receiving the clock signal as a power source when the input signal has a first phase, where the signal input circuit amplifies a swing width of the input signal based on a swing width of the clock.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: February 14, 2017
    Assignee: SK Hynix Inc.
    Inventor: Hyun-Woo Lee
  • Patent number: 9536593
    Abstract: An input receiver is provided with a pass transistor that is controlled to pass an input signal to an inverter only while a first binary state for the input signal equals a low voltage. The input receiver also includes a source follower transistor configured to pass a threshold-voltage-reduced version of the input signal while the first binary state of the input signal equals a high voltage greater than the low voltage.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: January 3, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: LuVerne Ray Peterson, Thomas Bryan, Jacob Schneider
  • Patent number: 9434157
    Abstract: There is provided a liquid discharging apparatus including: a low voltage system circuit block including a modulation portion which generates a modulation signal pulse-modulated from a source signal; a high voltage system circuit block including a gate driver which generates an amplification control signal based on the modulation signal; a transistor which generates an amplification modulation signal amplified from the modulation signal based on the amplification control signal; a low pass filter which demodulates the amplification modulation signal and generates a driving signal; and a piezoelectric element which is displaced as the driving signal is applied, in which the low voltage system circuit block and the high voltage system circuit block are formed on the same semiconductor substrate, in which the semiconductor substrate has one substrate potential supply terminal to which a substrate potential of the semiconductor substrate is supplied.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: September 6, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Shunichi Shima
  • Patent number: 9362916
    Abstract: In various embodiments, a circuit arrangement may be provided. The circuit arrangement may include a level shifting stage configured to be coupled to a first reference voltage, the level shifting stage having an output node. The circuit arrangement may further include a first input electrode in electrical connection with the level shifting stage. The circuit arrangement may also include a second input electrode in electrical connection with the level shifting stage. The circuit arrangement may further include a load having a first end and a second end, the first end coupled to the level shifting stage and the second end for coupling to a second reference voltage. In addition, the circuit arrangement may include a bypass circuit element connected in parallel to the load. The bypass circuit element may be configured to allow current to flow through upon application of an external voltage for bypassing the load.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: June 7, 2016
    Assignee: Agency for Science, Technology and Research
    Inventor: Jun Zhou
  • Patent number: 9344080
    Abstract: Disclosed are various embodiments related to dual-gate transistors and associated calibration circuitry. In one embodiment, dual-gate transistors may be configured in a sense amplifier arrangement, and calibration circuitry can be used to adjust an input offset of the sense amplifier. In another embodiment, a reference level voltage utilized in an amplifier with dual-gate transistors can be adjusted during a calibration sequence, and may be substantially unchanged from its nominal value outside of the calibration sequence. In another embodiment, a calibration sequence can be utilized to determine circuit results from a circuit including dual-gate transistors, and to adjust control gates to more closely coincide with expected or desired results. In yet another embodiment, a semiconductor memory device can include a memory array with amplifiers that include dual-gate transistors, as well as associated calibration circuitry.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: May 17, 2016
    Inventor: Michael C. Stephens, Jr.
  • Patent number: 9329608
    Abstract: Programmable integrated circuits with configurable logic circuitry and routing resources are provided. Portions of the routing resources on a programmable integrated circuit may be used in implementing a desired user-specified custom logic function, whereas other portions of the routing resources on the programmable integrated circuit may be unused. The unused routing resources may include adjacent pairs of routing paths. These paths may be coupled to control circuitry configured to drive the routing paths to desired voltage levels to provide an optimal amount of decoupling capacitance. In one suitable arrangement, two adjacent routing paths may both be driven to a positive power supply voltage level. In another suitable arrangement, the two adjacent routing paths may be driven to the positive power supply voltage level and a ground power supply voltage level, respectively.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: May 3, 2016
    Assignee: Altera Corporation
    Inventors: Zahir Parpia, Chris Wysocki
  • Patent number: 9325305
    Abstract: Apparatus and methods advantageously maintain transistors of open-drain differential pairs biased in the saturation region when “active,” rather in than the triode or linear region. The biasing techniques are effective over a broad range of process, voltage, and temperature (PVT) variations. By controlling a high voltage level used to drive the gate of a transistor of the differential pair, the biasing of the transistor in the saturation region is maintained. In one embodiment, the low voltage level used to cut off the transistor of the differential pair is also controlled. These techniques advantageously permit differential drivers to exhibit relatively large output swings, relatively high edge rates, relatively high return loss, and relatively good efficiency.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: April 26, 2016
    Assignee: Microsemi Storage Solutions, Inc.
    Inventors: Guillaume Fortin, Charles Roy, Mathieu Gagnon
  • Patent number: 9275933
    Abstract: A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: March 1, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Li Kuo, Yung-Chang Lin
  • Patent number: 9159447
    Abstract: The present disclosure relates to a field of display. Particularly, embodiments of the present invention disclose a shift register unit, a shift register, an array substrate and a display apparatus that enable the respective shift register units to be reset independently. The shift register unit includes a sampling part, an output part and a reset part, wherein the sampling part includes a first switching transistor and a second switching transistor, the output part includes a fifth switching transistor, a sixth switching transistor, a first capacitor and a second capacitor, and the reset part includes a third switching transistor and a fourth transistor.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: October 13, 2015
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Ying Wang
  • Patent number: 9142280
    Abstract: A circuit for configuring an external memory includes a memory controller, a register, an OR gate, first and second input/output (IO) pads, and pull-up and pull-down resistors. When the circuit is in a high power mode, the memory controller refreshes the external memory by providing reset and clock enable signals to the external memory by way of the first and second IO pads. When the circuit is in a low power mode, the pull-up and pull-down resistors configure the external memory in a self-refresh mode. When the circuit exits the low power mode, the first and second IO pads are powered on. The OR gate receives and provides a control signal output by the register to the external memory by way of the first IO pad, which keeps the external memory in the self-refresh mode.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: September 22, 2015
    Assignee: FREESCALE SEMICONDUCOTR, INC.
    Inventors: Rakesh Pandey, Bharat K. Kumbhkar, Biswaprakash Navajeevan, Manmohan Rana
  • Patent number: 9130568
    Abstract: A logic gate with three inputs A, B, and C, and one output implementing a function MAJ(A,B,C)=A*B+B*C+A*C comprising two mutually exclusive transmission gates (TGs) connected in series, based on two parallel double-gate controllable polarity devices, a polarity of each being controlled by input A and a conduction being controlled by input B, or vice-versa, in opposite polarities, and that route either an input A or C from one side of the transmission gates to the output.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: September 8, 2015
    Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
    Inventors: Luca Gaetano Amaru, Pierre-Emmanuel Julien Marc Gaillardon, Giovanni De Micheli
  • Patent number: 9007090
    Abstract: A programming element including a first transistor, a second transistor, and a capacitor between a logic circuit using a semiconductor element and a power supply is provided. In the programming element, a node where a drain electrode of the first transistor, a gate electrode of the second transistor, and one of electrodes of the capacitor are electrically connected to each other is formed. A potential can be supplied to each of a source electrode of the first transistor and the other of the electrodes of the capacitor. The power supply and the logic circuit are electrically connected to each other through a source electrode and a drain electrode of the second transistor. A connection state between the power supply and the logic circuit is controlled in accordance with the state of the second transistor.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 8994406
    Abstract: A digital cell for performing a logic operation on a logic input to produce a logic output, includes an evaluation block and a sense-amplifier block, both configured to receive input signals representative of the logic input, and to detect when the logic input and/or input signals validly encode at least one bit. The digital cell is configured to alternate between an evaluate state and a reset state. Upon the digital cell being in the reset state and the detection, the digital cell is switched from the reset state to the evaluate state in which the evaluation block generates a difference in its output signals, and the sense-amplifier block amplifies the difference so that the output signals encode at least one valid bit. Upon the digital cell being in the evaluate state, the digital cell can be triggered to reset to the reset state.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: March 31, 2015
    Assignee: Nanyang Technological University
    Inventors: Joseph Sylvester Chang, Bah Hwee Gwee, Kwen Siong Chong
  • Publication number: 20150022239
    Abstract: A system includes an inverter element to gate forward current flow from a first signal source, and a reverse current inhibition element to block reverse current flow towards the first signal source from a second signal source.
    Type: Application
    Filed: August 2, 2013
    Publication date: January 22, 2015
    Applicant: Broadcom Corporation
    Inventor: Dario Soltesz
  • Patent number: 8901965
    Abstract: A dual-mode logic gate, for selectable operation in either of static and dynamic modes, includes: a static gate which includes at least one logic input and a logic output; a mode selector, configured for outputting a turn-off signal to select static mode operation and for outputting a dynamic clock signal to select dynamic mode operation; and a switching element associated with the mode selector static gate, comprising a first input connected to a constant voltage, a second input for inputting the mode selection signal from the mode selector, and an output connected to a logic output of the static gate. The switching elements switches the logic gate operation from static to dynamic mode, by applying the appropriate signal to the switching element.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: December 2, 2014
    Assignee: Ben-Gurion University of the Negev Research and Development Authority
    Inventors: Alexander Fish, Asaf Kaizerman, Sagi Fisher, Itamar Levy
  • Patent number: 8901964
    Abstract: A level shifter transfers a first voltage signal to a second voltage signal. The level shifter comprises a comparison circuit, a delay circuit, and a selection circuit. The comparison circuit generates a first signal according to the comparison result between the first voltage signal and the reverse-phase signal of the first voltage signal. The delay circuit generates a second signal according to the first voltage signal. The selection circuit receives the first and the second signals and chooses the higher voltage one from the first signal and the second signal to be the second voltage signal.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: December 2, 2014
    Assignee: Industrial Technology Research Institute
    Inventor: Shien-Chun Luo
  • Patent number: 8890573
    Abstract: A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method. In one embodiment, the clock gating latch includes: (1) a propagation circuit having a single, first switch configured to be driven by an input clock signal, (2) a keeper circuit coupled to the propagation circuit and having a single, first switch configured to be driven by the input clock signal and (3) an AND gate coupled to the propagation circuit and the keeper circuit and having an internal node coupled to a second switch in the propagation circuit and a second switch in the keeper circuit.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 18, 2014
    Assignee: Nvidia Corporation
    Inventors: Ilyas Elkin, Ge Yang, Jonah Alben
  • Patent number: 8890572
    Abstract: Embodiments of the present disclosure enable low swing dynamic circuits with reduced dynamic power and leakage power. In an embodiment, a level detector circuit monitors the pre-charge voltage level of the dynamic node of a dynamic circuit and discontinues the charging of the dynamic node when the pre-charge voltage exceeds a logic high reference voltage. The logic high reference voltage is selected below a supply voltage of the dynamic circuit, resulting in a low swing dynamic circuit. In another embodiment, the pull-down logic circuitry is disconnected from the dynamic node when the dynamic node voltage falls below a logic low reference voltage, above a ground voltage. In another embodiment, a DC keeper circuit of the dynamic circuit is configured based on the pre-charge level of the dynamic node.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: November 18, 2014
    Assignee: Broadcom Corporation
    Inventor: Sachin Joshi
  • Patent number: 8866510
    Abstract: When a semiconductor device is provided with an inverter comprising a transistor having a first gate and a second gate, the semiconductor device does not require a circuit for generating a potential to be input to the second gate of the transistor and has a small number of wirings. Moreover, a semiconductor device having high reliability is provided. The semiconductor device includes a plurality of stages of circuits each provided with two inverter circuits in parallel. Two inverter circuits in a given stage output respective signals of opposite polarities, which is utilized for interchanging signals output from inverter circuits in the previous stage. Thus, an inverted signal is input to the second gate of the transistor included in each of two inverter circuits in the subsequent stage.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Tanabe, Hiroyuki Miyake
  • Publication number: 20140300387
    Abstract: A logic inverter with over-current protection according to one embodiment includes a transistor, an input signal line coupled to a gate terminal or base region of the transistor, an output signal line coupled to a drain terminal or collector region of the transistor, a power supply line coupled to the drain terminal or collector region of the transistor, and a feedback resistor between a source terminal or emitter region of the transistor and ground.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 9, 2014
    Applicant: Applied Wireless Identifications Group, Inc.
    Inventors: Liming Zhou, Vadim Kikin
  • Publication number: 20140266305
    Abstract: A semiconductor device having a power-saving circuit. The semiconductor device includes an input-output terminal and a holding circuit. When the input-output terminal is used, an inverter loop of the holding circuit is made not to operate by controlling a switch, and when the input-output terminal is not used, the inverter loop of the holding circuit operate by controlling the switch. Power consumption of the holding circuit can be reduced. An OS transistor is preferably used for the switch.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 18, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Yuto Yakubo
  • Publication number: 20140232433
    Abstract: A transistor includes a source region, a drain region, a channel region, a gate electrode and a layer of a stress-creating material. The stress-creating material provides a stress that is variable in response to a signal acting on the stress-creating material. The layer of stress-creating material is arranged to provide a stress in at least the channel region. The stress provided in at least the channel region is variable in response to the signal acting on the stress-creating material. Layers of stress-creating material providing a stress that is variable in response to a signal acting on the stress-creating material may also be used in circuit elements other than transistors, for example, resistors.
    Type: Application
    Filed: February 15, 2013
    Publication date: August 21, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: Johannes von Kluge
  • Patent number: 8791721
    Abstract: A circuit has a stacked structure having at least one symmetric FET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to ground than the asymmetric FET.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: July 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Patent number: 8786313
    Abstract: It is an object to provide a logic circuit which can be operated even when unipolar transistors are used. A logic circuit includes a source follower circuit and a logic circuit an input portion of which is connected to an output portion of the source follower circuit and all transistors are unipolar transistors. A potential of a wiring for supplying a low potential connected to the source follower circuit is lower than a potential of a wiring for supplying a low potential connected to the logic circuit which includes unipolar transistors. In this manner, a logic circuit which can be operated even with unipolar depletion transistors can be provided.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: July 22, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Daisuke Kawae
  • Patent number: 8779798
    Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Publication number: 20140176183
    Abstract: PICA test circuits are shown that include a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology.
    Type: Application
    Filed: August 28, 2013
    Publication date: June 26, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Herschel A. Ainspan, SEONGWON KIM, FRANCO STELLARI, ALAN J. WEGER
  • Publication number: 20140145761
    Abstract: A storage cell having a pulse generator and a storage element is proposed. The storage element input is connected to receive a data input signal. The storage element output is connected to provide a data output signal. The storage element is operable in one of a data retention state and a data transfer state in response to a storage control signal received from the pulse generator. The pulse generator is connected to receive a clock signal with rising and falling clock signal edges and is adapted to provide control pulses in the storage control signal. Each control pulse has a leading edge and a trailing edge. The control pulses have a polarity suited to invoke the data transfer state on their leading edges. The novel feature is that the pulse generator is adapted to initiate a rising-edge control pulse when receiving a rising clock signal edge and to initiate a falling-edge control pulse when receiving a falling clock signal edge.
    Type: Application
    Filed: February 3, 2014
    Publication date: May 29, 2014
    Inventor: Jakob SALLING
  • Patent number: 8710866
    Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: April 29, 2014
    Assignees: Electronics and Telecomunications Research Institute, Konkuk University Industrial Cooperation Corp.
    Inventors: Sang Hee Park, Chi Sun Hwang, Sung Min Yoon, Him Chan Oh, Kee Chan Park, Tao Ren, Hong Kyun Leem, Min Woo Oh, Ji Sun Kim, Jae Eun Pi, Byeong Hoon Kim, Byoung Gon Yu
  • Patent number: 8698521
    Abstract: A semiconductor device in which a transistor using an oxide semiconductor containing In, Zn, or the like for a channel region can be driven like a p-channel transistor is provided. The semiconductor device includes a transistor and an inverter, wherein an output of the inverter is input to a gate of the transistor, a channel region of the transistor includes an oxide semiconductor film containing In, Zn, or Sn, and each channel region of transistors in the inverter contains silicon. When a high voltage is input to the inverter, a low voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned off. When a low is input to the inverter, a high voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned on.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuji Nishijima
  • Patent number: 8692579
    Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: April 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Publication number: 20140062532
    Abstract: A dynamic logic gate includes a nano-electro-mechanical-switch, preferably a four-terminal-nano-electro-mechanical-switch. The invention further refers to dynamic logic cascade circuits comprising such a dynamic logic gate. In particular, embodiments of the invention concern dynamic logic cascade circuits comprising single or dual rail dynamic logic gates.
    Type: Application
    Filed: August 26, 2013
    Publication date: March 6, 2014
    Applicant: International Business Machines Corporation
    Inventors: Michel Despont, Daniel Grogg, Christoph Hagleitner, Yu Pu
  • Patent number: 8653854
    Abstract: A circuit includes E-mode transistors with gate-source junction, a D-mode transistor with gate-source junction. A component generates a voltage drop between the source of the D-mode transistor and the drain of an E mode transistor provided as a signal output. A connection is made between this drain of the E-mode transistor and the gate of the D-mode transistor, and a signal input at the gates of the E-mode transistors.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: February 18, 2014
    Assignee: EPCOS AG
    Inventors: Erwin Spits, Léon C. M. van den Oever
  • Publication number: 20140035621
    Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.
    Type: Application
    Filed: October 9, 2013
    Publication date: February 6, 2014
    Applicants: Konkuk University Industrial Cooperation Corp, ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sang Hee PARK, Chi Sun HWANG, Sung MIN Yoon, Him Chan OH, Kee Chan PARK, Tao REN, Hong Kyun LEEM, Min Woo OH, Ji Sun KIM, Jae Eun PI, Byeong Hoon KIM, Byoung Gon YU
  • Publication number: 20140035622
    Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.
    Type: Application
    Filed: October 9, 2013
    Publication date: February 6, 2014
    Applicants: Konkuk University Industrial Cooperation Corp, ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sang Hee PARK, Chi Sun Hwang, Sung Min Yoon, Him Chan Oh, Kee Chan Park, Tao Ren, Hong Kyun Leem, Min Woo Oh, Ji Sun Kim, Jae Eun Pi, Byeong Hoon Kim, Byoung Gon Yu
  • Patent number: 8629693
    Abstract: Each of a plurality of inverters includes: a first transistor having one end connected to a first terminal; and a second transistor having one end connected to a second terminal and the other end connected to the other end of the first transistor. The first transistors included in the inverters located at either odd-number orders or even-number orders counted from an input terminal side of an inverter chain circuit become conductive when a pre-charge signal has a first state to pre-charge the other end of the first transistors, and become non-conductive when the pre-charge signal has a second state.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: January 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Inukai
  • Patent number: 8610464
    Abstract: The circuit includes an E-mode transistor with gate-source junction, a D-mode transistor with gate-source junction, a component generating a voltage drop between the source of the D-mode transistor and the drain of the E-mode transistor, and a connection between the drain of the E-mode transistor and the gate of the D-mode transistor. The gate of the E-mode transistor is provided for an input signal, and the drain of the E-mode transistor is provided for an output signal.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: December 17, 2013
    Assignee: Epcos AG
    Inventor: Erwin Spits
  • Patent number: 8598910
    Abstract: In described embodiments, a timestamp generator includes a fixed clock domain driven by a fixed frequency clock, a core clock domain, coupled to the fixed clock domain, which is driven by a core clock whose frequency is adjustable during an operation of the timestamp generator. A timestamp logic operating in the core clock domain generates a timestamping output of the timestamp generator. A rate generator operating in both the fixed clock domain and the core clock domain generates per clock cycle increments in the fixed clock domain and transfers carry units from the fixed clock domain into the core clock domain, and a timestamp increment generation of the timestamp logic is clocked by the fixed frequency clock provided by the rate generator. A method for enabling timestamp in an ASIC to be accurate with system clock changes is also described.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: December 3, 2013
    Assignee: LSI Corporation
    Inventors: John Leshchuk, Joseph A. Manzella, Walter A. Roper
  • Patent number: 8587342
    Abstract: A novel logic circuit in which data is held even after power is turned off is provided. Further, a novel logic circuit whose power consumption can be reduced is provided. In the logic circuit, a comparator comparing two output nodes, a charge holding portion, and an output-node-potential determining portion are electrically connected to each other. Such a structure enables data to be held in the logic circuit even after power is turned off. Further, the total number of transistors in the logic circuit can be reduced. Furthermore, the area of the logic circuit can be reduced by stacking a transistor including an oxide semiconductor and a transistor including silicon.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: November 19, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuto Yakubo, Shuhei Nagatsuka
  • Patent number: 8576614
    Abstract: A tunnel transistor is provided including a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: November 5, 2013
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Marc Heyns, Cedric Huyghebaert, Anne S. Verhulst, Daniele Leonelli, Rita Rooyackers, Wim Dehaene