Abstract: A multilevel triggering system includes a trigger block library configured to store multiple triggering function modules for performing triggering functions to detect corresponding triggering conditions, respectively; and a triggering matrix including multiple triggering levels, each triggering level being configurable to include one or more trigger blocks and each trigger block being configurable to implement a triggering function module of the multiple triggering function modules, each trigger block generating a corresponding block trigger when the corresponding triggering condition of the triggering function module implemented by the trigger block is detected in a portion of an input signal. Each triggering level is configured to generate a corresponding level trigger when each of the one or more trigger blocks in the triggering level generates the corresponding block trigger.

Abstract: A multilevel triggering system of a signal analysis instrument outputs a complex trigger signal. The triggering system includes a trigger controlled buffer for receiving and buffering an input signal, triggering function modules, and a triggering matrix. Each triggering function module performs a corresponding triggering function for detecting a corresponding triggering condition. The triggering matrix includes multiple triggering levels, each of which is configurable to include at least one trigger block and each trigger block being configurable to implement one of the triggering function modules. Each trigger block generates a corresponding block trigger when the triggering condition of the corresponding triggering function module is detected in the buffered input signal.

Abstract: A transmitter circuit is provided in the present disclosure. The transmitter circuit includes a first capacitance, a first current pump circuit for charging or discharging the first capacitance to output a first voltage, a second capacitance, and a second current pump circuit for charging or discharging the second capacitance to output a second voltage. A charging rate at which the first current pump circuit charges the first capacitance or a discharging rate at which the first current pump circuit discharges the first capacitance determines a rising slew rate or a falling slew rate of the first voltage. A charging rate at which the second current pump circuit charges the second capacitance or a discharging rate at which the second current pump circuit discharges the second capacitance determines a rising slew rate or a falling slew rate of the second voltage.

Abstract: A driving apparatus for a display device includes a gray voltage generator that generates a plurality of gray voltage sets, each including a plurality of gray voltages having different levels, and a signal converter that includes a first selector for selecting one gray voltage set among the plurality of gray voltage sets on the basis of a first portion of an image signal and a second selector for selecting one or more gray voltages among the plurality of gray voltages belonging to the selected gray voltage set on the basis of a second portion of the image signal to output and select gray voltages with a smaller size digital-analog converter.

Abstract: A programmable logic array (PLA) comprising a two-dimensional array of a plurality of nanometer-scale switches is provided. Each switch comprises a pair of crossed wires which form a junction where one wire crosses another and at least one connector species connecting the pair of crossed wires in the junction. The connector species comprises a bi-stable molecule. A plurality of switches is configurable as an AND gate and a plurality of switches is configurable as an OR gate.

Abstract: Receiver circuits using nanotube based switches and logic. Preferably, the circuits are dual-rail (differential). A receiver circuit includes a differential input having a first and second input link, and a differential output having a first and second output link. First, second, third and fourth switching elements each have an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The receiver circuit can sense small voltage inputs and convert them to larger voltage swings.

Abstract: Disclosed are ways of providing a highly flexible high availability storage system. Disk drive carriers for insertion into enclosures in a storage system include several disk drives. The enclosures accept carriers that include drives of different sizes, and drives compatible with different storage technologies, for instance Fibre Channel, SATA, or SAS. Drives oriented in their carriers in a manner that allows them to be connected to a common medium via identical flex circuits that are configured based on the orientation of the drives. Redundant controllers include redundant serial buses for transferring management information to the carriers. The carriers include a controller for monitoring the multiple serial buses and producing storage technology specific management commands for the disk drives.

Abstract: A semiconductor device having a plurality of cascaded IC's (14, 15, 16), wherein the matching impedance between a signal transmission path (12) connected to an external signal transmission path and an input-side or output-side IC (14, 16) is set at 50 ohms which is equal to the characteristics impedance of the external signal transmission path. The matching impedance between a internal signal transmission path (13) and an input-side or output-side IC or intermediate IC is set at 200 ohms which is higher than the 50 ohms. The semiconductor device reduces the current dissipation and can operate at a higher speed.

Abstract: A low power wired OR circuit of the present invention comprises a plurality of logic blocks for pulling a wired OR signal line low in response to certain conditions, a differential pair of lines, such as the wired OR signal line and a reference signal line, and a sensing device coupled to the reference signal line and the wired OR signal line to receive the wired OR signal and the reference signal respectively and to detect a difference between the two signals. Having a differential pair of lines is advantageous because it maintains noise immunity for small voltage swings on the wired OR signal line, thereby reducing power dissipation in the wired OR circuit. A common current source coupled to each logic block through a common return path allows the low power wired OR circuit to control a discharge rate at which the wired OR line discharges.

Abstract: Even input bit lines, a first latch circuit group and a second latch circuit group are provided in a logical circuit. The first latch circuit group has a plurality of latch circuits which simultaneously latch a plurality of signal bits propagating the even input bit lines, respectively, in a first timing. The second latch circuit group has a plurality of latch circuits which simultaneously latch a plurality of signal bits propagating the even input bit lines, respectively, in a second timing. The output ends of a plurality of latch circuits are wired-OR to a first node, the plurality of latch circuits latching signal bits which propagate one half of the even input hit lines. The output ends of a plurality of latch circuits are wired-OR to a second node, the plurality of latch circuits latching signal bits which propagate remaining one half of the even input bit lines. The first and the second nodes, are wired-OR to a third node.

Abstract: A driver amplifier for a bus feeds single polarity signals of controlled slew rate to the bus. The slew rate control is effected by a feedback capacitor connected from the output to the input of the amplifier. A clamp is provided for selectively connecting the input of the amplifier through a low impedance path to a point of reference voltage so that when the amplifier is quiescent signals on the bus cannot be fed through the capacitor to turn on the amplifier. A current source and a switchable current sink are connected to the input of the amplifier to change the capacitor to produce the slew rate controlled transitions. Another driver amplifier of the same design but using components of the opposite conductivity type can be used to apply signals of the opposite polarity to the same bus.

Abstract: A fully differential, low voltage ECL gate (300) receives complementary logic signals (A, Ax, B, Bx) and provides them to first and second differential pairs (306, 318). Collectors from different differential pairs (306) and (318) are coupled together and provided with independent current paths through load resistors, R1, (336) and R2 (338). Differential outputs (OUT, OUTx) are generated at the common collector nodes (344, 346). The load resistors (336, 338) are selected to control the gain and ensure that a minimum switching threshold (V.sub.th) is maintained under all differential input signal conditions of (A, Ax, B, and Bx) for a logical AND or OR function.

Abstract: A configurable I/O arrangement for a controller has a number of internal and external input/output terminals, each of which are field selected as either an input or an output terminal. Logic functions of the controller are configured for a number of output terminals using up to 32 internal logical states and the states of 32 external physical I/O points. The update timing for each logic circuit is selectable to be synchronized in several different ways: synchronous with an internal event within the controller, synchronous with an event external to the controller, and asynchronous. The I/O arrangement includes a combination of a synchronous latchable input state array, user configurable means for logically combining the output signals of the reading circuits, and means for actuating external devices as a function of the logical combinations of the output signals of the reading circuits.

Abstract: A semiconductor integrated circuit device has a dual configuration involving a first latch circuit and a second latch circuit that are connected in parallel with each other. The first latch circuit is provided with an input terminal to operate the first latch circuit independently of the second latch circuit. This semiconductor integrated circuit device is capable of individually testing the latch circuits of the dual configuration, to ensure the merit of the dual configuration.

Abstract: A wired-OR logic circuit has a plurality of logic circuit connected to a common signal line. Each of the plurality of logic circuits includes an output bipolar transistor for outputting a logical output signal to the common signal line, and a constant-current source forming an emitter-follower circuit together with tile output bipolar transistor and being turned-on or turned-off in response to an output select signal. Each of the logic circuits may include a base potential setting circuit which applies different base potentials to a base of the output bipolar transistor. The outputs of the same level from all the logic circuits can be outputted to an output terminal without being influenced by voltage drops caused by distributed wiring resistances inherently existing in the signal line.

Abstract: A semiconductor integrated circuit device has a dual configuration involving a first latch circuit and a second latch circuit that are connected in parallel with each other. The first latch circuit is provided with an input terminal to operate the first latch circuit independently of the second latch circuit. This semiconductor integrated circuit device is capable of individually testing the latch circuits of the dual configuration, to ensure the merit of the dual configuration.

Abstract: Switching between two logic circuits that produce outputs at different respective logic levels is accomplished by means of a common input differential switch that has a branch in each logic circuit. A common current source supplies current to the branches within each logic circuit. The current source remains on regardless of which logic level is selected, thereby enhancing switching speed. The logic circuits produce logic outputs at a common output differential switch, which in turn provides a selected output to a single output terminal. The logic circuits are configured so that the output from the circuit corresponding to the selected logic level dominates the output from the other logic circuit at the output differential switch.