Abstract: A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.

Abstract: A driving circuit and an electronic apparatus having the same are provided. The electronic apparatus includes a load circuit and the driving circuit. The driving circuit is coupled to the load circuit. The driving circuit includes a voltage-divider circuit and a converting circuit. The voltage-divider circuit is configured to receive N control signals and divides voltages of the N control signals to generate a first voltage, wherein N is an integer greater than or equal to two. The converting circuit is coupled to the voltage-divider circuit to receive the first voltage, converts the first voltage into a driving voltage, and drives the load circuit according to the driving voltage.

Abstract: In an aerial vehicle, a malfunction determiner determines whether there is a malfunction in one of thrusters of the aerial vehicle. A flight controller activates the thrusters, and controls the output of each of the thrusters. The flight controller deactivates, when it is determined that there is a malfunction in one of the thrusters as a malfunctioned thruster, the malfunctioned thruster. The flight controller deactivates a selected thruster in the thrusters; the selected thruster being paired to the malfunctioned thruster, and controls the active thrusters except for the deactivated thrusters in all the thrusters to make the flight attitude of the aerial vehicle stable. The flight controller controls the active thrusters to cause the aerial vehicle to land while maintaining the flight attitude of the aerial vehicle being stable.

Abstract: Three state latch. In accordance with a first embodiment, an electronic circuit includes a single latch having three stable states. The electronic circuit may be configured so that all three outputs reflect a change at any one input in not more than three gate delays. The electronic circuit may further be configured so that when all inputs are set to one, a previous state of the latch is retained and output on the outputs.

Abstract: A ternary logic circuit according to the present invention includes a pull-up device (100) and a pull-down device (200) connected in series between power voltage sources (VDD and GND), and an input voltage (VIN) source and output voltage (VOUT) source. When both the pull-up device (100) and the pull-down device (200) are turned off by an input voltage (VIN), both the pull-up device (100) and the pull-down device (200) operate as simple resistors which are affected only by an output voltage (VOUT) and form a ternary digit (“1” state) through voltage division. When only one of the pull-up device (100) or the pull-down device (200) is turned on to allow a current to flow therethrough, VDD (“2” state) or GND (“0” state) is output as the output voltage (VOUT). Accordingly, a bit density can be remarkably increased.

Abstract: A level-up shifter circuit is suitable for high speed and low power applications. The circuit dissipates almost no static power, or leakage current, compared to conventional designs and can preserve the signal's duty cycle even at high data rates. This circuit can be used with a wide range of power supplies while maintaining operational integrity, and includes circuitry to compensate for process variations.

Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.

Abstract: In an integrated circuit having a feedback amplifier circuit composed of the feedback which feedbacks a part of the output signal to the input side in the first stage, a semiconductor integrated circuit of the present invention can suppress the occurrence of the data signal distortion and the gain peaking of the frequency characteristic generated by inter-stage wiring between the first stage and the latter stage. A semiconductor integrated circuit of the present invention includes the first circuit and the second circuit having the first output connected to the first circuit, and the second output that is a signal similar to said first output is outputted from between said first circuit and said second circuit.

Abstract: A memory card with a smart card function including a flash memory unit, a data processing control unit, and a power control unit is provided. The data processing control unit is coupled to the flash memory unit. The data processing control unit controls the flash memory unit and encrypts, decrypts and stores smart card security data. The power control unit receives at least one of a first power input and a second power input. The power control unit selects the first power input or the second power input and provides the selected one to the data processing control unit according to at least one control signal. An output terminal of the power control unit is coupled to the first power input. Furthermore, a power control method and a power control circuit of the forgoing memory card are also provided.

Abstract: Emitter-coupled logic circuits and systems that include such circuits are provided. Some emitter-coupled logic circuits include a plurality of fT-doubler circuits. Each fT-doubler circuit includes a plurality of transistors coupled to one another in an arrangement such that the plurality of transistors are configured to behave as a single enhanced transistor that has an effective unity current gain frequency that is higher than if a single transistor were used in its place. The fT-doubler circuits are configured to increase an operating frequency capability of the emitter-coupled logic circuit. Some emitter-coupled logic circuits include a plurality of cascode amplifier circuits. Each cascode amplifier circuit includes multiple transistors. An emitter of at least one first transistor of the plurality of transistors is coupled to a collector of at least one second transistor of the plurality of transistors Some emitter-coupled logic circuits may include both fT-doubler circuits and cascode amplifier circuits.

Abstract: In one aspect, the invention relates to logic cells that utilize one or more of spin diodes. By placing one or two control wires on the side of the spin diodes to generate magnetic fields in the spin diodes due to input currents, the logic cell can be changed from one logic gate to another logic gate. The unique feature leads to field logic devices in which simple instructions can be used to construct a whole new set of logic gates.

Abstract: In one aspect, the invention relates to programmable logic that utilizes one or more of magnetic diodes. By changing magnetic fields generated in the magnetic diodes due to input signals, the programmable logic can be changed from one logic gate to another logic gate. The unique feature leads to field reprogrammable logic devices in which simple instructions can be used to construct a whole new set of logic gates.

Abstract: An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contacting, the at least one conductive strip.

Abstract: A driving apparatus for a display device includes a gray voltage generator that generates a plurality of gray voltage sets, each including a plurality of gray voltages having different levels, and a signal converter that includes a first selector for selecting one gray voltage set among the plurality of gray voltage sets on the basis of a first portion of an image signal and a second selector for selecting one or more gray voltages among the plurality of gray voltages belonging to the selected gray voltage set on the basis of a second portion of the image signal to output and select gray voltages with a smaller size digital-analog converter.

Abstract: Monitoring parameters of memory modules is described. According to certain embodiments, one or more parameters on respective memory modules are monitored. Corresponding parameter information is transmitted away from the respective memory module to a device that is external to the respective memory modules.

Abstract: A lateral bipolar junction transistor having improved current gain and a method for forming the same are provided. The transistor includes a well region of a first conductivity type formed over a substrate, at least one emitter of a second conductivity type opposite the first conductivity type in the well region wherein each of the at least one emitters are interconnected, a plurality of collectors of the second conductivity type in the well region wherein the collectors are interconnected to each other, and a plurality of base contacts of the first conductivity type in the well region wherein the base contacts are interconnected to each other. Preferably, all sides of the at least one emitters are adjacent the collectors, and none of the base contacts are adjacent the sides of the emitters. The neighboring emitter, collectors and base contacts are separated by spacings in the well region.

Abstract: An electronic device is presented for performing at least one logic function. The device comprises an electron emission based electrode arrangement associated with an electron extractor. The electrode arrangement comprises at least one basic unit including a photocathode, an anode, and one or more gates arranged aside a cavity defined between the photocathode and the anode. Said one or more gates are connectable to a voltage supply unit to be operated by one or more input voltages signals corresponding to one or more logical values, respectively. Said anode is operable as a floating electrode from which an electrical output of the device indicative of a resulted logic function is read. The anode is electrically connected to a photocathode of another cathode-anode unit of the same device, or is connected to an electrode of another electronic device.

Abstract: The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added.

Abstract: Various logic gates and methods for using such are disclosed herein. For example, some embodiments of the present invention provide parallel differential logic gates. Such logic gates include two or more differential input pairs. The collectors of the first transistors in each of the differential pairs are all electrically coupled to an upper voltage via a first load resistor. Similarly, the collectors of the second transistors in each of the differential pairs are all electrically coupled to an upper voltage via a second load resistor. Depending upon the relative values selected for the first and second load resistors, the gate operates as an AND gate or an OR gate.

Abstract: A drive circuit of a computer system is for driving a mode indicator. The computer system includes a first port and a second port. The mode indicator includes a first receiving end and a second receiving end. The drive circuit includes a first input end connected to the first port, a second input end connected to the second port, a first output end connected to the first receiving end, a second output end connected to the second receiving end. A power supply is connected to the first input end and the second input end via a first resistor and a second resistor respectively. The mode indicator is dichromatic and has two LEDs emitting non-matching colored light.

Abstract: A semiconductor device having a plurality of cascaded IC's (14, 15, 16), wherein the matching impedance between a signal transmission path (12) connected to an external signal transmission path and an input-side or output-side IC (14, 16) is set at 50 ohms which is equal to the characteristics impedance of the external signal transmission path. The matching impedance between a internal signal transmission path (13) and an input-side or output-side IC or intermediate IC is set at 200 ohms which is higher than the 50 ohms. The semiconductor device reduces the current dissipation and can operate at a higher speed.

Abstract: This invention prevents a cross talk caused by intersection of interconnections, and offers a semiconductor integrated circuit with improved circuit characteristics. By disposing a pair of emitter follower circuits symmetrically with respect to a center line of a differential amplifier, an area where the interconnections cross with each other is eliminated and interconnections within a circuit block and a ground wiring can be made with a single metal layer. Herewith cross talk due to the intersection of the interconnections can be resolved.

Abstract: A method for evaluating the upper bound fault coverage of an integrated circuit (IC) or a portion thereof from register transfer level (RTL) description is provided. The method requires the analysis of a circuit described in RTL consisting of primary input and output pins as well as devices connected to each other and/or to the primary pins to determine the controllability and observability of each pin of the circuit to ‘stuck at zero’ and ‘stuck at one’ conditions. The upper bound fault coverage is then determined based on the ratio between the number of pins that are both controllable and observable and twice the number of pins in the circuit. The method does not require a dynamic simulation for its fault coverage assessment and hence is advantageous over other methods consuming significant time and resources.

Abstract: A cascadable divide-by-two binary counter circuit (120) that has particular application for use as a synchronous divider circuit (50, 54) in a phase lock loop (26). The counter circuit (120) employs a D flip-flop (122) that receives a D input and provides a Q output. A first AND gate (124) is responsive to a P input and a Q input, where the Q input is the output from a preceding counter circuit and the P input is the state of all of the preceding counter circuits. The output of the AND gate (124) is applied to an exclusive-OR gate (126) along with the Q output of the flip-flop (122). The output of the exclusive-OR gate (126) is applied to one input of a second AND gate (128). The other input of the second AND gate (128) is a reset signal and the output of the second AND gate (128) is the D input of the flip-flop (122). A decoder (142) is programmed to provide the reset signal when the desired count is reached.

Abstract: A transistor output circuit featuring a low power consumption, high speed and stabilized operation is realized.

Abstract: The invention provides a logic circuit which has a sufficient load driving capacity even in its operation with a low power supply voltage and can operate at a high speed. In a next stage to a differential circuit having an output stage for which an emitter followers are used, a folding circuit in which a pair of transistors of a diode connection are used to raise the signal level of differential outputs of the differential circuit.

Abstract: Differential-signal gate structures are provided in which first and second current-switching modules are coupled to first and second electrical loads with the differential input ports of the modules cross coupled. Although each of the modules separately exhibits an increased propagation-delay response to one input signal sequence, they are never simultaneously exposed to this sequence because of the cross coupling of the input ports. Accordingly, these gate structures have significantly reduced propagation-delay variations.

Abstract: A method and apparatus of eliminating the unwanted effects of parasitic bipolar discharge in dynamic logic circuits including silicon-on-insulator (SOI) field effect transistors (FET) by measuring setup time in a logic partition of a dynamic logic circuit having a precharging device and an output device. The method determines a first time delay of a clock signal from said logic partition to a control input of said precharging device and a second time delay of a logic signal from said logic partition to a control input of said output device. The method then determines a setup time according to said first and second time delays. The precharging device remains active during the setup time to prevent parasitic bipolar discharge.

Abstract: A signal level shifting circuit comprises an emitter-follower transistor with a base supplied with an input signal, a collector coupled to a supply voltage, and an emitter coupled via a level shifter to a bias circuit, whereby a level shifted signal is produced at a junction point between the level shifter and the bias circuit. The level shifter comprises one or more diodes to provide a forward voltage drop providing a signal level shift, a PMOS transistor switch in parallel with the diode(s), and a control circuit responsive to the supply voltage for controlling the switch to bypass the diode(s), thereby providing a smaller level shift, when the supply voltage has a lower one of two possible values. The circuit can have a differential input and a differential output stage, and cascode-connected transistors for reducing voltages so that the circuit can be implemented using BCMOS technology.

Abstract: A variable base drive output circuit that is operational for low-potential power supplies. The output circuit includes a current regulating branch and a base drive branch. A control transistor is logically coupled to an enable signal and an input signal to be propagated. Activation of that control transistor establishes a current path to the base of a bipolar pulldown transistor that is coupled to output. The current regulating branch includes a resistance device in series with current limiting transistors. The resistance device is coupled to the control node of a base current transistor such that when the load on the output node drops, the current to the base of the pulldown transistor also drops. The result is a savings in Icc current for logic LOW signals at the output node. The variable base drive output circuit is operable for low supply potentials.

Abstract: A circuit for shifting the potential level of an input signal toward higher potentials is added to a conventional differential ECL circuit in order to shift levels of emitter potentials of npn bipolar transistors forming a current switch toward higher potentials. Thus, the ECL circuit is improved to ensure a continuous flow of a current and to maintain stable operations even at an instant where base potentials of the npn bipolar transistors are switched by a standard ECL-level signal even when the power source voltage is around −2 V.

Abstract: A logic gate arrangement having a master gate or section for controlling the logic threshold voltage of slave gates responsive to the master. Both the master and slave gates have two opposite conductivity type transistors disposed in combination with a logic function circuit. The transistors have a common gate connection to a control input. Varying the voltage on the control input varies the logic threshold voltage of the gate. The logic function in the master gate is typically an inverter, with input and output connected together and driving the control inputs of the slave gates. The logic function of the slave gates may be a variety of different logic functions. The logic threshold voltage of the slave gates is substantially the same as a voltage applied to the control input of the master gate.

Abstract: A logic circuit (3) comprises IIL aggregates (4a, 4b, 4c) each consisting of a plurality of IIL elements. Each of the IIL aggregates (4a, 4b, 4c) is supplied with an injector current (I.sub.inj) from an injector current source (2) through a wiring (5). A monitoring element (6) is formed by utilizing an IIL element which needs the longest time until the injector current therein attains a predetermined value. When the injector current applied to an injector current input end (9) attains the predetermined value, potentials of an output terminal (10) and a reset signal input terminal (7) fall. Therefore, a reset operation is performed in accordance with the IIL element which needs the longest time until the injector current attains the predetermined value.

Abstract: A protection circuit for a semiconductor switch for switching a load is disclosed. Control circuitry is used for switching the semiconductor switch on in response to a switching signal and for switching the semiconductor switch off in response to a deactivation signal. A deactivation circuit is used for generating the deactivation signal. An overvoltage detector circuit responsive to a voltage at an output of the semiconductor switch that exceeds a predetermined value is used for generating an overvoltage signal. The overvoltage detector circuit includes a Zener diode that has its cathode coupled through a resistor to the output of the semiconductor switch and its anode coupled to the collector of the diode connected transistor. A first logic circuit is used for causing the deactivation circuit to generate the deactivation signal in response to the switching signal and the overvoltage signal.

Abstract: A level shifter circuit for converting an input signal referenced to the least positive power supply (typically ground) to an output signal referenced to a higher, more usable voltage. The level shifter circuit generally includes a current mirror arrangement for coupling first and second current legs. The first current leg includes an NPN bipolar transistor arranged in series with a resistor R and a PNP bipolar transistor, wherein the NPN and PNP transistors have base inputs V.sub.ref and V.sub.in, respectively. The second current leg comprises a series arrangement of a diode-connected NPN bipolar transistor, a resistor R and a diode-connected NPN bipolar transistor. An output voltage (V.sub.OUT =V.sub.ref -V.sub.in), is taken at the collector of the diode-connected NPN transistor in the second current leg.

Abstract: A PNP bipolar transistor is connected to both ends of a resistive element of a Super Push-Pull Logic (SPL) circuit so as to place an emitter thereof at the side of a power supply source. Resistive elements and an NPN bipolar transistor forms a bias circuit for biasing a low voltage to a base of the PNP bipolar transistor. The base of the PNP bipolar transistor is connected to an emitter node of a NPN bipolar transistor through a capacitative load element. By this construction, the present invention can provide signal without any delay to turn on the PNP bipolar transistor. Therefore, the collector response speed of the SPL circuit can be increased.

Abstract: A digital switching stage includes a differential amplifier having a first and a second differential amplifier branch. A first resistor is connected in the first differential amplifier branch and has a first terminal and a second terminal. The first terminal is a terminal for a first supply potential. A first bipolar transistor is connected in an emitter follower circuit with respect to the second terminal of the first resistor and has an emitter being connected to an output terminal. A second bipolar transistor has a base and has a collector-to-emitter path being connected between the output terminal and a terminal for a second supply potential. A second resistor is connected in the second differential amplifier branch and has a first terminal and a second terminal. The first terminal of the second resistor is connected to the output terminal and the second terminal of the second resistor is connected to the base of the second bipolar transistor.

Abstract: An ECL circuit including first and second transistors driven by differential input signals. Both transistors include emitters connected to a common node. The first transistor has a first collector connected to a first output terminal and a first base connected to receive a first biasing signal. The second transistor has a second collector connected to a second output terminal and a second base connected to receive a second biasing signal. The first and second biasing signals driving the first and second transistors are logical complements.

Abstract: A basic logic circuit 10 which functions as a data selector consists of a basic circuit 11, a HET (hot electron transistor) 12, the first and second emitters of which are connected to the first emitter of a HET 16 and a data input end A respectively, and an inverter 13 connected to an output end of the circuit 11. In a HET 14 having no base electrode, its collector is connected to a power supply line VCC via a load resistor 15, its first emitter is used exclusively for current output by connecting to the collector of the HET 16 the second emitter of which is connected to a power supply line VSS, its second emitter is used for current input/output by directly connected to a control input end S, and its third emitter is used exclusively for current input by connecting to the first emitter of a HET 17 the second emitter of which is connected to a data input end B. An output data Q is equal to an input data A/B when a control data S is high/low level respectively.

Abstract: The logic ensures a smallest achievable propagation delay, lowest achievable supply voltage and low power consumption. Silicon or GaAs can be used. The gain of each gate is preferably low. A local supply voltage E depends on temperature and is provided for each gate or plurality of gates fabricated on a single chip. The main supply voltage V-, whose variations are insignificant, may be as small as -1 V or -0.5 V if bipolar transistors or FETs are used respectively. An inverter may comprise merely one transistor with the source coupled to E. A or a second transistor is coupled between the drain of the first transistor and ground. A binary input voltage is applied to the gate of the first transistor. A binary output voltage appears at the drain and is independent of temperature. An n-input NOR gate is established simply by adding n-1 transistors in parallel with the first transistor.