Abstract: A semiconductor device includes an RF circuit and a microcontroller. The RF circuit has: a transmission unit generating a transmission signal; a reception unit generating a first generation signal and a second generation signal; and a transmission/reception loop-back switching unit switching between a first coupling state of coupling an output terminal of the transmission unit to a transmission antenna and coupling an input terminal of the reception unit to a reception antenna and a second coupling state of coupling an output terminal of the transmission unit to the input terminal of the reception unit. The microcontroller switches the transmission/reception loop-back switching unit to the second coupling state and executes a test of the RF circuit on the basis of the second generation signal when the transmission/reception loop-back switching unit is in the second coupling state and an output signal of a first sensor circuit.

Abstract: A protective circuit for protecting an output stage in the event of faulty contacting of the electrical connections, wherein the output stage includes a driver unit and has an analog or digital signal output is provided. Accordingly, in order to protect the output stage from a faulty connection in a simple and economical manner, the protective circuit comprises a first transistor circuit, which is connected in series between the output stage and the signal output, and a second transistor circuit, which is connected in series between the negative supply connection and the signal output. The second transistor circuit is connected to the base of the first transistor circuit in order to influence the first transistor circuit in such a way that the first transistor circuit becomes highly resistive in the event of a fault.

Abstract: A high-voltage, high-current, solid-state closing switch uses a field-effect transistor (e.g., a MOSFET) to trigger a high-voltage stack of thyristors. The switch can have a high hold-off voltage, high current carrying capacity, and high time-rate-of-change of current, di/dt. The fast closing switch can be used in pulsed power applications.

Abstract: The present invention relates to a switching mode power supply and a driving method thereof. In the present invention, a supply voltage is generated by using a start voltage that corresponds to input power, and a switching operation frequency of a power switch is changed according to an increase/decrease of the supply voltage.

Abstract: An electronic device is presented for performing at least one logic function. The device comprises an electron emission based electrode arrangement associated with an electron extractor. The electrode arrangement comprises at least one basic unit including a photocathode, an anode, and one or more gates arranged aside a cavity defined between the photocathode and the anode. Said one or more gates are connectable to a voltage supply unit to be operated by one or more input voltages signals corresponding to one or more logical values, respectively. Said anode is operable as a floating electrode from which an electrical output of the device indicative of a resulted logic function is read. The anode is electrically connected to a photocathode of another cathode-anode unit of the same device, or is connected to an electrode of another electronic device.

Abstract: A switching matrix has a first number of inputs and a second number of outputs as well as a conductor arrangement and controllable switching elements by means of which the inputs can be connected with the outputs. The controllable switching elements are fashioned such that at least two independent control signals are required to trigger a switching event.

Abstract: An electronic device is presented for performing at least one logic function. The device comprises an electron emission based electrode arrangement associated with an electron extractor. The electrode arrangement comprises at least one basic unit including a photocathode, an anode, and one or more gates arranged aside a cavity defined between the photocathode and the anode. Said one or more gates are connectable to a voltage supply unit to be operated by one or more input voltages signals corresponding to one or more logical values, respectively. Said anode is operable as a floating electrode from which an electrical output of the device indicative of a resulted logic function is read. The anode is electrically connected to a photocathode of another cathode-anode unit of the same device, or is connected to an electrode of another electronic device.

Abstract: A reception line break detection apparatus includes a transmission-side line drive, a reception line, a switching element, and a reception-side line receiver receiving signals transmitted from the transmission-side line drive through the reception line. The apparatus further includes a break detection unit detecting a break of the reception line using the switching element, where the switching element is switched according to a line voltage of lead-in wires branched off from the reception line. Accordingly, the apparatus includes fewer components than conventional apparatuses and fewer power sources are required.

Abstract: An asynchronous FIFO circuit has

Abstract: A signal level shifting circuit comprises an emitter-follower transistor with a base supplied with an input signal, a collector coupled to a supply voltage, and an emitter coupled via a level shifter to a bias circuit, whereby a level shifted signal is produced at a junction point between the level shifter and the bias circuit. The level shifter comprises one or more diodes to provide a forward voltage drop providing a signal level shift, a PMOS transistor switch in parallel with the diode(s), and a control circuit responsive to the supply voltage for controlling the switch to bypass the diode(s), thereby providing a smaller level shift, when the supply voltage has a lower one of two possible values. The circuit can have a differential input and a differential output stage, and cascode-connected transistors for reducing voltages so that the circuit can be implemented using BCMOS technology.

Abstract: A relatively low voltage, high speed, differential diode transistor logic DDTL) family of circuits for performing various Boolean logic functions, such as AND, OR, etc. as well as non-Boolean functions, such as buffering and storage. The logic family may be configured in emitter coupled logic (ECL), also known as current mode logic (CML), with bipolar transistors, such as bipolar junction transistors (BJT) or heterojunction bipolar transistors (HBT). The logic family can also be implemented in source-coupled field effect transistor logic (SCFL) and utilize FETs, MOSFETs, HEMTs and MESFETs. In accordance with one aspect of the invention, gate circuits configured for reduced voltage multiple input operation only include input diodes connected to one of the transistors forming the differential pair, thus reducing the number of input diodes by one half.

Abstract: There is provided emitter coupled logic (ECL) circuitry comprising a differential amplifier circuit for receiving an input signal and a reference potential Vbb, and for causing an output circuit to make a transition to its high state by charging a parasitic capacitor which is parasitic in the output circuit, and make a transition to its low state by discharging a charge stored in the parasitic capacitor to a potential Vtt by way of a load resister, according to whether or not the level of the input signal is larger than the reference potential Vbb, and a discharge switching circuit which can switch to its conductive state in response to a control signal applied thereto so that the charge stored in the parasitic capacitor is also discharged to the negative potential Vee by way of the discharge switching circuit.

Abstract: In order to provide a differential ECL wherein the malfunction resulting from the constant current source being cut off from the power supply is prevented and wherein the output logic is determined on one side even when input terminals thereof are left open, a differential ECL of the invention comprises means for clamping a potential difference that is smaller than a predetermined value between the collector and the emitter of one of the differential transistors and enabling a current to flow through the constant current source.

Abstract: An inverter stage includes a supply voltage terminal and a reference potential terminal. An npn transistor has a base terminal for receiving an input signal, a collector terminal for supplying an output signal, and an emitter terminal. A controllable current source is connected between the emitter terminal of the transistor and the reference potential terminal. A series circuit of at least two diodes is connected between the supply voltage terminal and the collector terminal of the transistor. A symmetrical inverter stage assembly includes two of the inverter stages being connected in parallel with the emitters of the transistors of each of the inverter stages being connected to one another. A ring oscillator includes n (n.gtoreq.1) of the inverter stages connected in series. The inverter stages include first and last inverter stages, each of the inverter stages has an output and an input, and the output of the last inverter stage is connected to the input of the first inverter stage.