Abstract: Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

Abstract: Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

Abstract: Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

Abstract: Protective elements are provided for non-volatile memory cells in crossbar arrays in which each memristor is situated at a crosspoint of the array. Each memristor is provided with a protective element. The protective element includes a layer of a first oxide that upon heating converts to a second oxide having a higher resistivity than the first oxide.

Abstract: In one example, an oxide-based negative differential resistance comparator circuit includes a composite NDR device that includes a first electrode, a first thin film oxide-based negative differential resistance (NDR) layer in contact with the first electrode and a central conductive portion. The composite NDR device also includes a second thin film oxide-based NDR layer disposed adjacent to the first NDR layer and a second electrode. A resistor may be placed in series with the composite NDR device and an electrical energy source can apply applying a voltage across the first electrode and second electrode. The composite NDR device produces a threshold based comparator functionality in the comparator circuit.

Abstract: A switching matrix has a first number of inputs and a second number of outputs as well as a conductor arrangement and controllable switching elements by means of which the inputs can be connected with the outputs. The controllable switching elements are fashioned such that at least two independent control signals are required to trigger a switching event.

Abstract: CMOS semiconductor pass-transistor logic circuitry (200) is disclosed, comprising pass transistor circuitry (204, 212, 218), and tunneling structure circuitry (228) coupled to the pass transistor circuitry; where the tunneling structure circuitry is adapted to hold a node (222) voltage stable by compensating a leakage current (302) originating from said pass transistor circuitry.

Abstract: CMOS semiconductor latch and register (500) circuitry is disclosed, comprising a first tunneling structure latch circuit (502); data input circuitry (506), coupled and adapted to pass data to (504) said first tunneling structure latch circuit (502), a second tunneling structure latch circuit (514), data transmission circuitry (516), coupled between said first and second tunneling structure latch circuits, and adapted to transfer data from said first tunneling structure latch circuit to said second tunneling structure latch circuit, and data output circuitry (518), coupled to (512) said second tunneling structure latch circuit (514).

Abstract: Circuit designs of basic digital logic gates are disclosed using Resonant Tunneling Diodes (RTDs) and MOSFETs, which reduces the number of devices used for logic design, while exploiting the high speed negative differential resistance (NDR) characteristics of RTDs. Such logic circuits include NAND, NOR, AND, and OR gates and Minority/Majority circuits, which are used in full adder circuits. By implementing RTDs along with conventional MOSFETs, the use of series connected MOSFETs, which results in low output rise and fall times, especially for a large number of inputs, can be avoided. Furthermore, the RTD logic design styles do not require the use of resistors or any elaborate clocking or resetting scheme.

Abstract: A multi-function resonant tunneling logic gate is provided in which a resonant tunneling transistor (12) includes a first terminal, a second terminal, and a third terminal. A plurality of signal inputs are coupled to the first terminal of the resonant tunneling transistor (12) through a summer (10). Furthermore, a biasing input is operable to apply a bias to the first terminal of resonant tunneling transistor (12) such that the transfer characteristic of the resonant tunneling transistor (12) can be shifted relative to the signal inputs.