Abstract: The invention provides a bidirectional level shifter which includes: a first signal terminal; a second signal terminal; a first switch, coupled between the first signal terminal and ground; an inverter receiving a signal from the first signal terminal; a Schottky diode including an anode and a cathode, the anode receiving a signal from the second signal terminal; a second switch, coupled between the cathode of the Schottky diode and the ground; a comparing circuit, comparing a reference voltage and a voltage at the second signal terminal to control the first switch, wherein the reference voltage is lower than a forward bias voltage of the Schottky diode; a first voltage source coupled to the first common node; and a second voltage source coupled to the second common node.

Abstract: In one aspect, the invention relates to logic cells that utilize one or more of spin diodes. By placing one or two control wires on the side of the spin diodes to generate magnetic fields in the spin diodes due to input currents, the logic cell can be changed from one logic gate to another logic gate. The unique feature leads to field logic devices in which simple instructions can be used to construct a whole new set of logic gates.

Abstract: In one aspect, the invention relates to programmable logic that utilizes one or more of magnetic diodes. By changing magnetic fields generated in the magnetic diodes due to input signals, the programmable logic can be changed from one logic gate to another logic gate. The unique feature leads to field reprogrammable logic devices in which simple instructions can be used to construct a whole new set of logic gates.

Abstract: A power management device for controlling a power supply device includes a pulse generator, a delay unit, a first XOR gate, an OR gate, and a second XOR gate. The pulse generator generates a pulse signal, the delay unit, the first XOR gate, the OR gate, and the second XOR gate cooperatively generate an enabling signal corresponding to the pulse signal to enable and disable the power supply, and receive an output voltage of the power supply device as a feedback signal. Upon receiving the feedback signal, the power management device can stay at correct enabled and disabled statuses of the power supply device.

Abstract: A switching matrix has a first number of inputs and a second number of outputs as well as a conductor arrangement and controllable switching elements by means of which the inputs can be connected with the outputs. The controllable switching elements are fashioned such that at least two independent control signals are required to trigger a switching event.

Abstract: A duplexer is provided. The duplexer includes a first band pass filter (BPF) coupled to a first signal port and a second signal port; and a second BPF coupled to the first signal port and a third signal port, each of the first BPF and the second BPF including a first resonance circuit which comprises a plurality of first resonators coupled in series; a second resonance circuit which comprises a plurality of second resonators coupled in series; and a third resonance circuit which comprises a plurality of third resonators coupled in parallel and formed in divided lines coupling the first and second resonance circuits.

Abstract: To make a decision circuit for RZ format optical signals at a very high data rate, the device (1?) comprises an electronic component (2) having a tunnel diode characteristic presenting a peak current (IP) and a valley current (IV). The device (1?) comprises a control current source (9) controlled by a control signal (VRESET) said current being injected into the component (2) and taking a first value or a second value. In response to an input optical signal (E), generator means (2) generate a current (IRZ) into the component (2). The valley current (IV) is of a value greater than the first current value and the peak current (IP) is of a value lying between a second current value (IR) and the sum of said second value plus the value (IRZ) of the current generated the generator means (2).

Abstract: Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

Abstract: Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

Abstract: Circuit designs of basic digital logic gates are disclosed using Resonant Tunneling Diodes (RTDs) and MOSFETs, which reduces the number of devices used for logic design, while exploiting the high speed negative differential resistance (NDR) characteristics of RTDs. Such logic circuits include NAND, NOR, AND, and OR gates and Minority/Majority circuits, which are used in full adder circuits. By implementing RTDs along with conventional MOSFETs, the use of series connected MOSFETs, which results in low output rise and fall times, especially for a large number of inputs, can be avoided. Furthermore, the RTD logic design styles do not require the use of resistors or any elaborate clocking or resetting scheme.

Abstract: An inverter circuit has first and second input terminals for receiving a complementary input signals, first and second output terminals for outputting a complementary output signals generated from the complementary input signals, and a pair of rectifier sections each for flowing the charge stored on a higher-potential side of the output terminals to a lower-potential said of the output terminals, for saving power dissipation.

Abstract: A rectifying transfer gate circuit includes first and second field effect transistors and one diode. The source of the first field effect transistor is coupled to a first input node and the gate thereof is coupled to a second input node. Meanwhile, the source of the second field effect transistor is coupled to the second input node and the gate thereof is coupled to the first input node. The diode is coupled between the common drain of the first and second field effect transistors and an output node, so as to increase the speed of the operation in the application circuit utilizing the above rectifying transfer gate circuit.

Abstract: A separating circuit 244 is connected between a scanning voltage circuit 241, which supplies a selected voltage V1 to a line SU and an unselected voltage V2 to a line SD, and a sustaining voltage circuit 242, which selectively supplies a sustaining voltage Vs and 0 V to a line SC. A power recovery circuit 243 is connected to the line SC. In the separating circuit 244, a switch SW16 is connected between the line SD and the line SC and line SC, and a switch SW17 is connected between the line SU and the line SC. During an address period, the switches SW16 and SW17 are turned off and during a sustain period the switch SW16 is turned on/off and SW17 is turned on. The switch SW16 is constituted with a diode whereas the switch SW17 is constituted with a MOS transistor. When the unselected voltage V2 is negative, either the switch SW16 or SW17 may be omitted.

Abstract: A serial differential cell includes complementary positive and negative pass gate networks coupled to a differential amplifier, which produces a valid logic output. The complementary pass gate networks can include one or more pass gate stages coupled in series. In a serial differential multiplexer, a stage includes first and second inputs, and a select input for controlling which input is passed to an output of the stage. For multiple stages, the output of a first stage is coupled to one of the inputs of a next stage. A number of stages can be coupled together in series to form networks, with a differential amplifier coupled between positive and negative networks where necessary to provide a valid logic output.