Abstract: A device configured to emulate a unary correlithm object logic function gate comprises a memory and a logic engine. The memory stores a logical operator truth table that includes a plurality of input logical values and a plurality of output logical values. These logical values are represented by correlithm objects. The logic engine receives an input and determines the Hamming distance between the correlithm object of the input and the correlithm objects of the truth table to determine the appropriate output.

Abstract: Aspects of the present disclosure are directed to single-wire bus communications. In accordance with one or more embodiments, a pull-up current is delimited when a single-wire bus circuit is operated at a dominant level during the transmission of data on the single-wire bus circuit. This approach can be implemented to facilitate power savings, such as in applications involving a master control circuit that transmits signals by driving the single-wire bus circuit between dominant and recessive levels.

Abstract: A switching device driver, which includes switching circuitry and a first capacitive element, which is coupled to the switching circuitry, is disclosed. The switching circuitry receives a logic level input signal and provides a switching control output signal to a switching device based on the logic level input signal. When the logic level input signal has a first logic level, the switching circuitry charges the first capacitive element. When the logic level input signal transitions from the first logic level to a second logic level, the switching circuitry at least partially discharges the first capacitive element to rapidly transition the switching control output signal, thereby causing the switching device to quickly change states.

Abstract: A switching device driver, which includes switching circuitry and a first capacitive element, which is coupled to the switching circuitry, is disclosed. The switching circuitry receives a logic level input signal and provides a switching control output signal to a switching device based on the logic level input signal. When the logic level input signal has a first logic level, the switching circuitry charges the first capacitive element. When the logic level input signal transitions from the first logic level to a second logic level, the switching circuitry at least partially discharges the first capacitive element to rapidly transition the switching control output signal, thereby causing the switching device to quickly change states.

Abstract: A semiconductor device includes: a GaAs chip; and a resin sealing the GaAs chip. The GaAs chip includes: a p-type GaAs layer; an n-type GaAs layer on the p-type GaAs layer; a metal electrode located on the n-type GaAs layer along an edge of the GaAs chip and to which a positive voltage is applied; a device region located in a central portion of the GaAs chip; a semi-insulating region located between the metal electrode and the device region and extending in the p-type GaAs layer and the n-type GaAs layer; and a connecting portion disposed outside the semi-insulating region and electrically connecting the p-type GaAs layer to the metal electrode.

Abstract: A circuit and a method are provided to produce a noise-free multi-input I/O pad for an integrated circuit chip. The circuit includes a normal mode internal node, which connects to normal mode circuitry and a test mode internal node, which connects to test mode circuitry. There are separate transfer devices which connect the I/O pad to the normal mode circuitry and to the test mode circuitry. In addition, a third transfer device, a load device, and a new intermediate internal node are added to prevent negative input voltage swings which occur on the I/O pad during the normal mode from causing the transfer gate to the test mode circuitry from turning ON causing chip failure.

Abstract: Since voltages of two input terminals of an output unit having an online download function are decided by voltages which are not correlative to each other, a value of an incoming current on the start-up becomes large. The present invention solves the problem of turning-on of a parasitic transistor due to a transitional minus potential even when the voltage of the output unit on a stationary state is set to 0 V in order to reduce the incoming current. In this invention, a switch is turned on and off by a download switching digital signal, and an input from a delay circuit for charging and discharging a condenser in the delay circuit whose one end is connected to a reference potential is input to one of the input terminals of the output terminal while the reference potential is applied to the other input terminal of the output unit. Thus, an input error in the output unit is reduced to prevent an excessive incoming current.

Abstract: A high speed switch. The novel switch includes an input circuit having a transistor Q1 for receiving an input signal, a first mechanism for providing a path from an output of Q1 to an output terminal, and a second mechanism for receiving a control signal and in accordance therewith reducing the conductivity of the path during a mute mode. The first mechanism includes a first circuit for providing a first path from an output of Q1 to a first node, and a second circuit for providing a second path connecting the first node to the output terminal. The second mechanism is adapted to apply a signal to the first node during the mute mode such that the first and second circuits are off or partially conducting. The switch also includes a circuit for clamping the first node to a first predetermined voltage during the mute mode.

Abstract: A logic buffer includes a logic gate having at least two input terminals and two output nodes, a plurality of output terminals, each having a capacitance associated therewith and a pull-up circuit interconnected between each output node and the plurality of output terminals for alternately charging the capacitance of each output terminal. The buffer also includes a differential pull-down circuit including a common pull-down current source, the pull-down device interconnected between the output nodes and the output terminals for inversely alternately discharging the capacitances through the common pull-down current source for accelerating the discharge of the capacitance of the respective output terminal.

Abstract: A transistor output circuit featuring a low power consumption, high speed and stabilized operation is realized.

Abstract: A relatively low voltage, high speed, differential diode transistor logic DDTL) family of circuits for performing various Boolean logic functions, such as AND, OR, etc. as well as non-Boolean functions, such as buffering and storage. The logic family may be configured in emitter coupled logic (ECL), also known as current mode logic (CML), with bipolar transistors, such as bipolar junction transistors (BJT) or heterojunction bipolar transistors (HBT). The logic family can also be implemented in source-coupled field effect transistor logic (SCFL) and utilize FETs, MOSFETs, HEMTs and MESFETs. In accordance with one aspect of the invention, gate circuits configured for reduced voltage multiple input operation only include input diodes connected to one of the transistors forming the differential pair, thus reducing the number of input diodes by one half.

Abstract: An output driver circuit for coupling a logic circuit to load includes an input node, an output node for coupling to the load and a pull down switch which discharges the output node in response to a signal received at the input node. A current sink circuit includes a feeder transistor which provides current to the control terminal of the pull down switch to render the pull down switch conductive when the voltage at the output node exceeds a first threshold value between a logic high and a logic low. The feeder transistor is charged by a first charging path having a first impedance by which it takes a first time period to render the pull down switch conductive, the first impedance providing a low standby current when the voltage at the output node is below about the first value.

Abstract: It is common that the presence of a defect causes abnormal gate output voltage excursions in data buffers, AND gates, OR gates and multiplexers in current-mode logic circuits. A voltage excursion is detected by a voltage excursion detection apparatus which includes a built-in detector. The detector, which is little overhead, is used to monitor output swings of all gates (differential circuits) and flags all abnormal voltage excursions. These detection results cover classes of faults that cannot be tested by stuck-at testing methods only. The voltage detection apparatus works well below "at-speed" frequencies.

Abstract: Circuits using differential logic are employed in high-speed optical communications systems. An essential problem in the design of large-scale integrated circuits for this purpose is the control of undesired heat generation, so that the circuits should have low power consumption. According to the invention, a reduction in power consumption is achieved by reducing the number of stages connected in parallel with respect to the power supply. To accomplish this, part of the parallel-connected stages are connected in series with the remaining part of the parallel-connected stages, so that the total number of parallel branches is reduced.

Abstract: A multiple input, low voltage, OR/NOR gate architecture based on a single-ended OR/NOR gate circuit, wherein a plurality of input transistors are connected in parallel. A reference transistor connects to the input transistors. A feedback means connects the NOR output signal to the base or gate of the reference transistor. The feedback means provides an effectively differential input for the multiple input circuit, without increasing circuit complexity, thereby providing enhanced noise margin characteristics.

Abstract: An Emitter Coupled Logic (ECL) circuit includes therein a constant potential generating circuit which is comprised of a load resistor, an active pull-down transistor and a constant current source. By containing the constant potential generating circuit which has been independently provided externally to an ECL circuit, the ECL logic circuit is operable at the power supply potential of -4.5 V or -5.2 V at the high speed with reduced power supply consumption. The constant current source is an NPN transistor whose base is connected to an output node of a bias circuit, and the output of the bias circuit is an output having a value set so that a collector current of the active pull-down transistor is kept constant at all times. Hence, the electric power consumption can be further reduced.

Abstract: First and second inverting stages and first and second decoding stages form in combination a decoder circuit, each of NAND gates of the first and second decoding stages and each of inverters of the first and second inverting stages are implemented by bi-MOS circuits, respectively, and the bi-MOS circuit for the NAND gate and the bi-MOS circuit for the inverter are a high-speed large-current consumption type and a low-speed small-current consumption type so that the decoder circuit achieves a high switching speed without sacrifice of power consumption.

Abstract: A control circuit for providing fast turn on of a PNP transistor in which a capacitor charging current is boosted and provided to the base of the PNP transistor. An embodiment of the invention provides a current amplifier in parallel with a current source for coupling to the base of the PNP transistor. The PNP transistor is connected to a positive voltage supply. A capacitor is also coupled to the positive voltage supply for delivering a charging current amplifier. In a further embodiment, an NPN transistor has its base coupled to the capacitor and its collector coupled to the base of the PNP transistor for providing the drive current boost. A diode may be coupled to the capacitor for passing a discharge current to the capacitor when the PNP transistor is off and to block the capacitor current when the PNP transistor is being switched on. A PNP drive transistor may be coupled between the collector of the NPN transistor and the base of the PNP transistor.

Abstract: A fully differential, low voltage ECL gate (300) receives complementary logic signals (A, Ax, B, Bx) and provides them to first and second differential pairs (306, 318). Collectors from different differential pairs (306) and (318) are coupled together and provided with independent current paths through load resistors, R1, (336) and R2 (338). Differential outputs (OUT, OUTx) are generated at the common collector nodes (344, 346). The load resistors (336, 338) are selected to control the gain and ensure that a minimum switching threshold (V.sub.th) is maintained under all differential input signal conditions of (A, Ax, B, and Bx) for a logical AND or OR function.

Abstract: A complementary-output vertically-stacked ECL gate circuit is disclosed which is low in power dissipation and fast in operation. The ECL gate circuit has a dual differential pair circuit arrangement provided with a pair of complementary outputs and an active pull-down circuit at each of the outputs. This arrangement allows complementary currents to flow through current switching circuits for the respective differential pair circuits and thus provides complementary outputs with built-in active pull-down circuits.

Abstract: Switched pull down (SPD) ECL circuits have a switching circuit within the pull down portion of the output stage, so that a large portion of the total pull down current is switched to the negative going output node, and so that a small portion of the total pull down current is switched to the positive going output node. The negative going output node has a larger that normal ECL pull down current attached to it. The larger pull down current on the negative going node discharges the output capacitor in a shorter period of time. The shorter discharge time of negative going output results in a shorter fall delay time. Two smaller current sources are connected to each of the two differential ECL outputs to insure that both pull up transistors are forward biased so as to provide an adequate noise margin and insure correct circuit operation. Forward biasing the pull up transistors with a minimum acceptable amount of bias current at the emitters of the output pull up transistors provides proper immunity to noise.

Abstract: A high-voltage semiconductor driving circuit to be instantaneously operated for the duration of an arbitrary pulse width can be effectuated through an extremely simple circuit configuration.The circuit comprises a pulse transformer (2) which receives an input pulse signal and generates a pulse voltage, a diode (3) which conducts the pulse voltage to the capacitive gate electrode of the high-voltage semiconductor switching element (5), and another switching element (4) which is connected in parallel to the diode (3) and adapted to discharge, at the falling of the pulse voltage, the gate capacitance which has been charged at the rising of the pulse voltage.

Abstract: First emitters of a pair of input multi-emitter transistors are connected to a current source in common, to form an input differential amplifier. The other emitters of the input multi-emitter transistors are connected to current sources respectively. Pull-up and pull-down transistors are provided for respective ones of a pair of output terminals. Bases of the pull-up transistors are supplied with collector voltages of the input multi-emitter transistors, while those of the pull-down transistors are supplied with voltages of the other emitters of the multi-emitter transistors. Provided is an emitter-coupled logic circuit which has excellent load drivability, operates stably and obtains complementary outputs at a low cost.

Abstract: Fast fall time for ECL logic waveforms are produced by use of a circuit, which very quickly transfers charge from the ECL output load capacitance into a temporary holding capacitor. The charge transferred onto the temporary holding capacitor may then be removed at a leisurely pace. The circuit includes a pulldown transistor, and a control circuit that selectively turns the pulldown transistor on, if the ECL output will be low, or off, if the ECL output will be high. The control circuit includes an emitter-follower transistor which follows the differential ECL collector node that changes voltage inversely to the desired final ECL output. A diode is connected to the emitter-follower transistor's emitter so that the diode output is two diode drops below the ECL collector node inverse in polarity to the output. The diode drives the base of the pulldown transistor, so that the base of the pulldown transistor remains static until the inputs to the circuit change.

Abstract: An ECL stage has its current consumption adapted to its operation speed. For this purpose, the load resistor and the bias current source are adjustable so that the product of the current value of the source by the resistor value is substantially constant.

Abstract: An improved tri-state output buffer having an emitter-follower output stage clamps the reverse-bias voltage across the base-emitter path of an emitter-follower to limit the output leakage current and thereby extending the operating life of an integrated circuit (IC). A current sensitive voltage device such as a bipolar transistor or diode clamps the reverse-bias voltage of the base-emitter path. Voltage clamping prevents the bipolar transistors from activating while the buffer is disabled. The output leakage current that occurs when the junction is forward biased is minimized. This results in low output load capacitance that improves the propagation delay particularly when multiple buffers are used.

Abstract: The invention provides a BiCMOS logic gate circuitry comprising: input and output terminals: an output driving section including two bipolar transistors in the form of totem pole connection between a high voltage line and a low voltage line in which an intermediate point between the two bipolar transistors is connected to the output terminal; a base driving section including a plurality of MOS transistors and being connected to an input terminal for receiving an input signal and connected to bases of the bipolar transistors; and a base clamping section including at least one clamping circuit being connected to at least one of the bipolar transistors through its base for restricting a base potential of the at least one bipolar transistor in the vicinity of the same potential as a base-emitter forward bias at which the bipolar transistor turns ON so as to reduce the necessary time for charging a parasitic capacitance of the base of the at least one bipolar transistor.

Abstract: The semiconductor IC device has a circuit arrangement in which one or more of the circuits, such as on a single substrate, include a totem-pole series connection of bipolar transistors which are driven by arrangements of complementary MOS circuits in a manner such that high-speed logic/switching operation is effected. Arrangements of circuits can also be effected in which the totem-pole series connection is constituted by a PNP transistor, on the power source terminal side, and an NPN or NMOS transistor on the ground or pull-down side thereof. With such configurations, the output signal swing at low operating voltages can be maximized while achieving the same with reduced propagation delay time and low power consumption. The device can also be implemented by circuitry employing capacitance bootstrapping effect as well as IIL (I.sup.2 L) design schemes.

Abstract: A new logic family is identified that achieves much better speeds than CML logic gates. This new logic family operates with multiple inputs and a single logic level, using differential pairs of transistors for each input transistor of the multiple input. This new logic family enables high speed operation, or higher speed, than the prior art, together with lower operating current and a power-delay enhancement significantly increased over the prior art.

Abstract: An emitter-coupled logic circuit having superior drivability, stable operation, and obtaining complementary outputs. A pair of input differential transistors have their emitters coupled to a first current source in common, their bases connected to receive respective input signals, and outputting complementary logic values corresponding to the respective input signals. Pull-up and pull-down transistors are provided for respective ones of a pair of output terminals. Bases of the pull-up transistors are supplied with collector voltages of the input transistors and their emitters are connected to the respective output terminals. The bases of the pull-down transistors are supplied with the respective input signals, their emitters are coupled to a second current source in common, and their collectors are connected to the respective output terminals. A stabilizing circuit is connected to the respective output terminals to maintain the pull-up transistors in conducting states.

Abstract: In an output circuit, a signal /.phi. opposite in phase to a signal /EN inputted through an input terminal 3 is generated by an inverter 1, and a signal .phi. in phase with the signal /EN is generated by two inverters 8 and 2. When the input signal /EN changes from a high level to a low level, a bipolar NPN transistor 35 is turned on instantaneously to decide an output terminal 5 at the low level forcedly. On the other hand, when the signal /EN changes from the low level to the high level, an NPN transistor 10 is turned on in advance of the other circuits to decide the output terminal 5 at the high level forcedly. Accordingly, it is possible to roughly equalize a delay time (from when the level of the input signal /EN changes at the input terminal 3 to when the level of the signal /.phi. changes at an output terminal 4) to another delay time (to when the level of the signal .phi. changes at the output terminal 5), thus realizing an ideal phase relationship between the two signals/.phi. and .phi.

Abstract: In an ECL circuit, when a potential of an input signal A changes from "L" to "H", an output signal D correspondingly changes from "H" to "L", and, at this time, an output sent from a switching stage circuit is supplied to a gate of a PMOS transistor via a control capacitor. Thereby, a base current of a pull-down transistor flows, and change of a potential of an output terminal node is promoted. An NMOS transistor receiving the potential of the output terminal node is arranged between a node and a VEE supply terminal. Therefore, when the potential changes, the current flowing through a transistor decreases, and the base current of the pull-down transistor further increases, so that the change of the output signal D is further promoted.

Abstract: A first current switch circuit 1a outputs a first logic signal and a complementary signal thereof in response to an input logic signal. A pull-up transistor Q10 has a base receiving the first logic signal. A second current switch circuit 1b outputs a second logic signal based on the complementary signal and the potential of an output terminal OUT1. A level shift circuit 1c shifts the level of the second logic signal and provides it to the base of a pull-down transistor Q11. When the potential of an input terminal IN1 changes from a low level to a high level, a capacitive load CL is discharged through transistors Q9 and Q11. When the potential of output terminal OUT1 becomes lower than that of a first reference potential terminal VBB1, the second logic signal attains a low level, thereby turning off pull-down transistor Q11.

Abstract: A BiCMOS power driver circuit for interfacing to a bus comprises circuitry for channelling current from a power source to the base of a bipolar device to pull the output all the way down to within a bipolar V.sub.SAT voltage drop of ground, and then uses feedback to turn-off the pull-down circuit to conserve power. A similar circuit functions to provide Incident Wave Switching and Glitch Suppression by monitoring the voltage level at the output and sinking current as necessary to maintain a low logic level.

Abstract: In a semiconductor device where a CMOS circuit and a bipolar circuit are mixed, the bipolar circuit is operated between a first power supply voltage and a second power supply voltage, and the CMOS circuit and a level conversion circuit between a CMOS level and a bipolar level are operated between the first power supply voltage and a third power supply voltage. The third power supply voltage is between the first and second power supply voltages.

Abstract: In a push-pull type logic apparatus including a push-pull buffer formed by two bipolar transistors, a control circuit for turning ON one of the bipolar transistors and turning OFF the other, and a voltage clamp circuit for clamping the voltage of the base of at least one of the bipolar transistors, a clamp releasing circuit is provided for releasing the clamp operation of the voltage clamp circuit when the corresponding bipolar transistor is turned ON. Also, a MOS transistor is connected between the collector and emitter of the corresponding bipolar transistor and is turned ON when the corresponding bipolar transistor is turned ON.

Abstract: In an active pull down ECL apparatus including a current switch formed by an input transistor and a reference transistor, an emitter follower controlled by a collector voltage of the input transistor or the reference transistor, and an active pull down circuit connected to the emitter follower, a resistor is connected to an emitter of the input transistor or the reference transistor.

Abstract: An efficient high-speed ECL to CMOS logic converter for BiCMOS integrated circuits. In one embodiment, a differential amplifier compares an ECL input signal to an ECL reference voltage and generates a pair of complementary intermediate signals on a corresponding pair of differential output nodes. The differential amplifier has two load resistors coupled in series with a common load resistor which limits the upper voltage swing at the differential output nodes. A regenerative stage coupled to the differential output nodes switches between a partially on state and a fully on state in response to the complementary intermediate signals. A pair of inverter stages convert the complementary intermediate signals into a pair of CMOS level signals. A pair of complementary output drivers coupled to the respective complementary inverter stages provide current driving capability.

Abstract: A drive transistor has its base coupled to a circuit input and its collector coupled to provide an output current at a circuit output. The output current is responsive to a base current received at the base of the drive transistor. A voltage induced across a resistor connected between the circuit input and the base of the drive transistor indicates the amount of drive transistor base current. A portion of an input current presented at the circuit input is diverted to the circuit output based on the indicated amount of drive transistor base current. The remaining portion of the input current is provided as the drive transistor base current. The drive transistor is thus prevented from saturating.

Abstract: A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced.Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion.

Abstract: For increasing an operation speed of a logic circuit in a case where an output level is shifted from a high level to a low level, a control circuit is made of a combination of a first control transistor and a second control transistor. An input circuit has a local terminal and produces a local signal in response to an input signal to supply the local signal to the local terminal. An output circuit has an output terminal and produces an output signal in response to the input and the local signals to supply the output signal to the output terminal. The first control transistor is connected between the local terminal and the second control transistor and has a first transistor control terminal which is supplied with the output signal for controlling operation of the first control transistor.

Abstract: Switching between two logic circuits that produce outputs at different respective logic levels is accomplished by means of a common input differential switch that has a branch in each logic circuit. A common current source supplies current to the branches within each logic circuit. The current source remains on regardless of which logic level is selected, thereby enhancing switching speed. The logic circuits produce logic outputs at a common output differential switch, which in turn provides a selected output to a single output terminal. The logic circuits are configured so that the output from the circuit corresponding to the selected logic level dominates the output from the other logic circuit at the output differential switch.

Abstract: Switchable diffused junction capacitors providing selectable data signal paths in a logic gate. A control circuit, such as a current switch, renders one of the junction capacitors conductive to present a large diffusion capacitance which acts as a fast signal pathway to the respectively applied data signal. Non-conducting junction capacitor presents a negligible diffusion capacitance which essentially acts as an open circuit to the respectively applied data signal. The control circuit response is slow and non-critical. The combination of a slow response control to configure selectable fast response data signal pathways is useful in "half good" or "partial good" semiconductor chip technologies, data buffers with fast flush, and self-test, self-repair chip designs, among others.