Accelerating Switching Patents (Class 326/17)
  • Patent number: 11264989
    Abstract: According to one embodiment, a semiconductor device includes first, second, third, and fourth circuits. A first voltage is applied to the first circuit. A second voltage is applied to each of the second, third and fourth circuits. The third circuit is configured to generate a first control signal and a second control signal based on a signal generated by the first circuit and a signal generated by the second circuit. The fourth circuit is configured to output an output signal based on the first control signal and the second control signal. The output signal is brought to a high impedance state when at least one of the first voltage or the second voltage is not applied.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: March 1, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masanori Kinugasa, Tooru Wakahoi
  • Patent number: 11165426
    Abstract: A level shifter comprising: a translation circuit having two input lines and two output lines and configured to receive a differential signal in a low-voltage domain on the two input lines and provide a second differential signal, being a copy of the first differential signal, in a high-voltage domain on the two output lines; and a combiner circuit configured to convert the second differential signal into a single-ended signal at a high-voltage shifter output; wherein the combiner circuit comprises a two-input Muller C-element circuit wherein one input is inverted. Corresponding methods are also disclosed.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: November 2, 2021
    Assignee: NXP USA, Inc.
    Inventors: Mojtaba Ashourloo, John Pigott
  • Patent number: 11137854
    Abstract: A display device of the present invention includes a display panel having gate lines and a shift register configured to provide gate pulses to the gate lines.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: October 5, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Chung Sik Kong, Han In Cho
  • Patent number: 10855254
    Abstract: Systems for calibrating impedances caused by a first component and a second component of a voltage-mode transmitter driver are described herein. The first component includes a first transistor and a first resistor connected to the first transistor, wherein the first component is connected to a voltage source and an output end of the voltage-mode transmitter driver, respectively. The second component includes a second transistor and a second resistor connected to the second transistor, wherein the second component is connected to the output end of the voltage-mode transmitter driver, and a third transistor, respectively. A first gate of the third transistor is applied with a first tunable gate voltage, and the first tunable gate voltage is configured to be tuned to calibrate a first impedance between the output end and a ground to match with a second impedance between the voltage source and the output end.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: December 1, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Fei Guo, Yihui Li, Hong Xue, Xin Ma, Hui Wang
  • Patent number: 10797722
    Abstract: A system and method for encoding data by providing data expansion and compression functions for arbitrary input and output lengths. The input is partitioned into groups of sequential bits. A subkey is selected from secret key material for each group of the input bits. A tree of XOR gates applies XOR operations between the subkeys to generate the output. The XOR gates are arranged in layers and all the XOR gates within a layer switch at about the same time. A compression function is performed if the input length is greater than or equal to the output length and an expansion function is performed if the input length is less than or equal to the output length. There is no statistical correlation between the input and the output. A nonlinear function can be applied to the output such as an invertible S-Box, non-invertible S-Box, or series of Rotate-Add-XOR operations.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: October 6, 2020
    Assignee: The Boeing Company
    Inventor: Laszlo Hars
  • Patent number: 10715139
    Abstract: Driver and pre-driver circuitry operate in an integrated circuit with two supply voltages. In one form, a reference voltage generation circuit is operable to respond to varying voltage supply conditions in which a driver may be subject to over voltage effects by generating a reference voltage based the first supply voltage when the second supply voltage is not available, and based on the second supply voltage when the first supply voltage is not available. A first drive signal generation circuit drives a pull-up transistor gate based on a data signal, varying the gate voltage between the second supply voltage and the reference voltage. A second drive signal generation circuit drives a pull-down transistor gate with a signal varying between the second supply voltage minus the reference voltage, and zero volts. In one form, certain gate-source voltages in the driver are maintained to be equal.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: July 14, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rajesh Mangalore Anand, Jagadeesh Anathahalli Singrigowda, Girish Anathahalli Singrigowda, Prasant Kumar Vallur
  • Patent number: 10614864
    Abstract: A buffer output circuit, a driving method thereof and a memory apparatus are provided. The memory apparatus includes a memory array and the buffer output circuit including a first output stage circuit and a second output stage circuit. The first output stage circuit and the second output stage circuit receive the data signal at the same time and are both coupled to the data output terminal outputting a data output signal. The second output stage circuit receives a feedback signal from the first output stage circuit. During a pre-charging-discharging period, the first output stage circuit performs a voltage pre-raising operation or a voltage pre-decreasing operation on the data output signal based on the data signal, and the second output stage circuit keeps the level of the data output signal changing based on the feedback signal until the state transition of the data output signal is completed.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: April 7, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Liang-Shiang Chiu
  • Patent number: 10593374
    Abstract: A memory module includes a front side interface configured to serial-to-parallel convert a command, an address, and data, based on a host clock, and transfer the converted command, address, and data; a processing block configured to operate in synchronization with a division clock, process the command, address, and data transferred from the front side interface, and transfer the processed command, address, and data; a back side interface configured to include a PLL for generating a media clock having a frequency different from the host clock, to parallel-to-serial convert the command, address, and data transferred from the processing block, based on the media clock, and to transfer the converted command, address, and data; and memory devices configured to operate in synchronization with the media clock, and to write the data transferred from the back side interface therein in response to the command and address transferred from the back side interface.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: March 17, 2020
    Assignee: SK hynix Inc.
    Inventor: Hyun-Seok Kim
  • Patent number: 10418990
    Abstract: A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 17, 2019
    Assignee: MONTEREY RESEARCH, LLC
    Inventors: David G. Wright, Jason Faris Muriby, Erhan Hancioglu
  • Patent number: 10361618
    Abstract: A driving circuit drives an N-channel or NPN high-side transistor. A level shift circuit includes an open-drain differential conversion circuit that converts an input signal SIN into a differential signal SdiffP/SdiffN, and a latch circuit that switches its state according to the differential output SdiffP/SdiffN of the differential conversion circuit. A driver drives a high-side transistor according to an output of the level shift circuit. A bootstrap circuit generates a bootstrap voltage VBST to be used as an upper-side power supply for the driver. Upon detecting an abnormal state, a protection circuit controls at least a part of the driving circuit except for the input signal SIN so as to turn off the high-side transistor.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: July 23, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Yuichi Shinozaki
  • Patent number: 10305482
    Abstract: A voltage level shifter including a voltage level shifting circuit and a boost circuit is provided. The voltage level shifting circuit includes a first reference input end, a second reference input end, a first boosted input end, and a second boosted input end. The voltage level shifting circuit operates between a first voltage and a second voltage. The boost circuit is coupled to the voltage level shifting circuit. The boost circuit boosts the first boosted input end and the second boosted input end according to voltage values of the first reference input end and the second reference input end to reduce a transient current that flows from the first voltage to the second voltage.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: May 28, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Chung-Zen Chen
  • Patent number: 10186958
    Abstract: A circuit includes a first circuit that operates at a first-circuit supply voltage value and generates at least one of a first reference voltage value or a second reference voltage value, based on a voltage rated for transistors in a second circuit. The second circuit operates at the first-circuit supply voltage value and receives a first signal and at least one of the first reference voltage value or the second reference voltage value. The first signal is configured to swing between a low voltage value and a high voltage value lower than the first-circuit supply voltage value. The second circuit keeps a voltage across two terminals of a first transistor in the second circuit below the voltage rated for the first transistor, based on the at least one of the first reference voltage value or the second voltage value.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: January 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Alan Roth, Chia-Chun Chang, Eric Soenen
  • Patent number: 10164637
    Abstract: A device and method for shifting voltage levels within a circuit are provided. An aspect of the disclosure provides a level shifting circuit for shifting a first logic domain to a second logic domain. In particular, the level shifting circuit can receive an input signal having a first logic domain with a first high voltage and a first low voltage. The level shifting circuit can receive inputs corresponding to a second high voltage and a second low voltage from the second logic domain. The level shifting circuit can concurrently switch the first high voltage and first low voltage at the input to the second high voltage and the second low voltage to produce a level-shifted version of the input signal at the output. The level shifting circuit can also have a plurality of guard transistors that prevent overvoltage of the circuit components.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: December 25, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Sreenivasa Mallia, Ayush Mittal, Krishnaswamy Thiagarajan, Karthikeya Aruppukottai Boominathan
  • Patent number: 10144292
    Abstract: Described herein is a method and sanity monitoring system for power modules that detect abnormal conditions with respect to transistors in the power modules. A sanity monitor is added to each transistor. The sanity monitor can include a sensor that detects voltage, current, temperature, magnetic fields or similar parameters that indicate a health of a transistor. A failure handling device receives measurements from the sanity monitors and determines whether the measured parameters are within expected ranges for the transistors. If an abnormality is detected, the failure handling device performs a corrective action. For example, the failure handing device can reduce the overall current in a power stage to prevent remaining transistors from failing. The failure handling device additionally informs the driver, (e.g., via an input/output (I/O device), of the problem, indicating that the driver should bring the car to service.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 4, 2018
    Assignee: NIO USA, Inc.
    Inventor: Robert Herb
  • Patent number: 10141934
    Abstract: A level shifter circuit includes a latch module with a first plurality of PMOS transistors and a second plurality of NMOS transistors; a MOS module with a third plurality of MOS transistors operatively connected to the latch module; a fourth plurality of transistors operatively connected between the MOS module and the ground; and a fifth plurality of capacitors operatively connected between the latch module and the gates of fourth plurality of transistors.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Tao Yang, Wen-Shen Chou, Yung-Chow Peng
  • Patent number: 10101760
    Abstract: A power-on control circuit is provided. The power-on control circuit includes first and second power terminals, a switch circuit, an inverter chain circuit, and a capacitor. The switch circuit has a control terminal receiving a first control signal, an input terminal coupled to the second power terminal, and an output terminal coupled to a first node. The inverter chain circuit has an input terminal coupled to the first node and generates the first control signal. The capacitor is coupled between the first node and a ground. When the first power terminal receives a first voltage and the second power terminal does not receive a second voltage, the switch circuit is turned on according to the first control signal. When the first power terminal receives the first voltage and the second power terminal receives the second voltage, the switch circuit is turned off according to the first control signal.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: October 16, 2018
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Jung-Tsun Chuang, Chieh-Yao Chuang, Hung-Wei Chen
  • Patent number: 10044342
    Abstract: A die-to-die data transmitter is disclosed with a pull-up one-shot circuit and a pull-down one-shot circuit, each forming a delay circuit that determines a variable preemphasis period.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: August 7, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: LuVerne Ray Peterson, Thomas Bryan, Tin Tin Wee
  • Patent number: 9923559
    Abstract: A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: March 20, 2018
    Assignee: Monterey Research, LLC
    Inventors: David G. Wright, Jason Faris Muriby, Erhan Hancioglu
  • Patent number: 9819340
    Abstract: In accordance with one or more aspects of the disclosed embodiments, a drive circuit having a source of modulation for producing a modulated signal, a level shifter configured to receive the modulated signal and produce a level-shifted driver signal, an inverter circuit configured to receive the level-shifted driver signal and produce a MOSFET control signal, and at least one p-channel metal oxide semiconductor field effect transistor (MOSFET) configured to receive the MOSFET control signal and modulate an application of high current to a load, where the MOSFET control signal is supplied directly to the p-channel MOSFET through the inverter circuit.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: November 14, 2017
    Assignee: The Boeing Company
    Inventor: Suhat Limvorapun
  • Patent number: 9785601
    Abstract: A device includes a first driver circuit coupled to a first bus line, where the first driver circuit includes a first delay element. The first delay element is configured to receive a first input signal and generate a first output signal. The first output signal transitions logic levels after a first delay period when the first input signal transitions from a logic high level to a logic low level. The first output signal transitions logic levels after a second delay period when the first input signal transitions from the logic low level to the logic high level. The first delay element includes a sense amplifier. The first driver circuit is configured to transmit the first output signal over the first bus line. The device also includes a second driver circuit configured to transmit a second output signal over a second bus line.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: October 10, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Baker S. Mohammad, Paul D. Bassett, Martin Saint-Laurent
  • Patent number: 9780786
    Abstract: Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second logic gates coupled in series; a first circuit coupled between the first logic gate and a power supply line that activates the first logic gate responsive to a first control signal; and a second circuit coupled between the second logic gate and the power supply line that activates the second logic gate responsive to a second control signal that is different from the first control signal.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: October 3, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Tetsuya Arai
  • Patent number: 9754945
    Abstract: A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Eduard A. Cartier, Herbert L. Ho, Donghun Kang
  • Patent number: 9722579
    Abstract: A semiconductor device may include: a pre-driving unit suitable for transmitting input data to a first node in response to a first control signal; a main driving unit suitable for outputting the input data transmitted to the first node, using a first voltage as a driving voltage; and a bias control unit suitable for supplying a second voltage to the first node in response to a second control signal, the second voltage having a different level from the first voltage.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: August 1, 2017
    Assignee: SK Hynix Inc.
    Inventor: Jae-Heon Kim
  • Patent number: 9698667
    Abstract: A semiconductor device that has a level shift circuit, an anterior stage circuit, and a posterior stage circuit. The level shift circuit transmits an input signal from a primary potential system to a secondary potential system different from the primary potential system. The anterior stage circuit including a first transistor receives a gate driving signal delivered by the level shift circuit. The posterior stage circuit including a second transistor with the same channel type as that of the first transistor drives a switching element according to the output signal from the first transistor. The threshold voltage of the first transistor is set at a lower value than the threshold voltage of the second transistor.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: July 4, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Kanno, Hitoshi Sumida
  • Patent number: 9641068
    Abstract: Embodiments are provided that include a circuit for generating voltage in a memory. One such circuit includes a charge pump circuit including a first transistor, a high-voltage switch circuit, and a cut-off switch circuit arranged to reduce leakage current from the charge pump circuit. The cut-off switch circuit includes a second transistor, wherein an output of the charge pump circuit is coupled to one of a source node and a drain node of the second transistor, and a first control signal is input at a gate of the second transistor. Further embodiments provide a method for generating voltage. One such method includes enabling a first transistor coupled to an output of a charge pump circuit when the charge pump is operating and disabling the first transistor coupled to the output of the charge pump circuit when the charge pump circuit is not operating.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: May 2, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 9571091
    Abstract: An emitter switched bipolar transistor circuit includes a bipolar junction transistor (BJT) having a collector coupled to an output terminal, a metal oxide semiconductor field effect transistor (MOSFET) coupled to an emitter of the BJT, a bias voltage supply coupled to the base of the BJT, a buffer coupled to the base of the BJT, and a comparator. The comparator includes a first input coupled to the collector of the BJT, a second input coupled to a voltage reference, and an output coupled to an input of the buffer. The comparator is configured to receive a collector voltage of the BJT at the first input of the comparator, compare the received collector voltage with the voltage reference, and cause the buffer to inject a current pulse to the base of the BJT until the collector voltage is less than the voltage reference, indicating the BJT is substantially saturated.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: February 14, 2017
    Assignee: ASTEC INTERNATIONAL LIMITED
    Inventor: Vijay Gangadhar Phadke
  • Patent number: 9523736
    Abstract: An apparatus for detecting fault injection includes a high-fanout network, which spans an Integrated Circuit (IC), and circuitry. In some embodiments, the high-fanout network is continuously inactive during functional operation of the IC, and the circuitry is configured to sense signal levels at multiple sampling points in the high-fanout network, and to identify a fault injection attempt by detecting, based on the sensed signal levels, a signal abnormality in the high-fanout network. In some embodiments, the circuitry is configured to sense signal levels at multiple sampling points in the high-fanout network, to distinguish, based on the sensed signal levels, between legitimate signal variations and signal abnormalities in the high-fanout network during functional operation of the IC, and to identify a fault injection attempt by detecting a signal abnormality.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: December 20, 2016
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Ziv Hershman, Leonid Shamis, Natan Keren
  • Patent number: 9490780
    Abstract: Embodiments include apparatuses, methods, and systems for a circuit to shift a voltage level. The circuit may include a first inverter that includes a first transistor coupled to pass a low voltage signal and a second inverter coupled to receive the low voltage signal. The circuit may further include a second transistor coupled to receive the low voltage signal from the second inverter to serve as a feedback device and produce a high voltage signal. In embodiments, the first transistor conducts asymmetrically to prevent crossover of the high voltage signal into the low voltage domain. A low voltage memory array is also described. In embodiments, the circuit to shift a voltage level may assist communication between a logic component including the low voltage memory array of a low voltage domain and a logic component of a high voltage domain. Additional embodiments may also be described.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: November 8, 2016
    Assignee: INTEL CORPORATION
    Inventors: Daniel H. Morris, Uygar E. Avci, Rafael Rios, Ian A. Young
  • Patent number: 9429618
    Abstract: A semiconductor integrated circuit device having a function for detecting degradation of a semiconductor device and a method of driving the same are disclosed. The semiconductor integrated circuit device includes an NMOS transistor electrically coupled to a PMOS transistor and configured to constitute an inverter together with the PMOS transistor, a first stress application unit electrically coupled to the PMOS transistor and configured to apply stress to the PMOS transistor, and a second stress application unit electrically coupled to the NMOS transistor and configured to apply the stress to the NMOS transistor.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: August 30, 2016
    Assignee: SK hynix Inc.
    Inventor: Jeong Tae Hwang
  • Patent number: 9413165
    Abstract: An input protection circuit may include an input node to receive an input signal, and may further include an output node to provide a protected output signal based on the input signal. Protection circuitry may be coupled between the input node and the output node to establish a current path that bypasses the input node and pulls the output pin to a specified reference voltage level in the event of a transient at the input node. A push-pull power supply may be used to provide the reference voltage to the current path, and dissipate any excess voltage by burning it off in a semiconductor device included in the push-pull power supply circuitry.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: August 9, 2016
    Assignee: National Instruments Corporation
    Inventor: Matthew Viele
  • Patent number: 9378789
    Abstract: Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: June 28, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: David Paul Hoff, Amey Kulkarni, Jason Philip Martzloff, Stephen Edward Liles
  • Patent number: 9287874
    Abstract: A voltage level shifting device for driving a capacitive load has an input terminal for receiving a first input signal switchable between a first logic state corresponding to a first reference voltage and a second logic state corresponding to a second reference voltage, and an output terminal for supplying an output signal switchable between a first logic state corresponding to a third reference voltage and a second logic state corresponding to a fourth reference voltage. The device also has a first electronic circuit that is activated following a commutation of the first input signal from the first reference voltage to the second reference voltage for fixing the output terminal to the fourth reference voltage. The device further has a second electronic circuit that is activated following a commutation of the first input signal from the second reference voltage to the first reference voltage.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: March 15, 2016
    Assignee: ST-ERICSSON SA
    Inventors: Pierangelo Confalonieri, Federico Guanziroli
  • Patent number: 9125005
    Abstract: The application provides a method, apparatus and computer program product to enable the provision of mobile services outside the typical coverage area of a cell. Moreover, some embodiments of the application may enable the provision of burst radio link communications over long distances between transmission and reception devices (e.g., access points) having devices within their respective coverage areas in order to enable the devices to provide data or content from one device to another. Furthermore, in some embodiments, the access points may be enabled to communicate with the devices within their respective coverage areas via short range communication techniques and aspects of cognitive radio may be employed.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: September 1, 2015
    Assignee: Nokia Technologies Oy
    Inventors: Markku Oksanen, Jari-Jukka Kaaja, Joni Jantunen
  • Publication number: 20150130657
    Abstract: Embodiments of a drain modulator that uses high power switch sensing to control active pulldown are generally described herein. In some embodiments, a logic and sense module is arranged to receive a control signal for controlling an on and an off state of an input of a switch to turn a high power voltage at an output of the switch on and off. A pullup module and a pulldown module are coupled to the input of the switch. An active pulldown module coupled to the output of the switch. The logic and sense module monitors the input to the switch and activates the active pulldown module to drain the output of the switch to a zero voltage when the input of the switch transitions to the off state.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: Raytheon Company
    Inventors: Mark T. Richardson, Denpol Kultran, George W. Gerace, Richard D. Young, Mark E. Stading, Jeffrey H. Saunders
  • Publication number: 20150091609
    Abstract: An integrated circuit has signal assist circuitry for assisting with pulling a signal on the signal line towards the logical low or high signal level. The signal assist circuitry comprises first and second assist circuits. The first assist circuit couples the signal line to the logical high signal level following a pullup transition of the signal and provides a floating signal level following a pulldown transition, while the second assist circuit provides the floating signal level following the pullup transition and provides the logical low signal level following the pulldown transition. By providing complementary first and second assist circuits, each circuit can be optimized for the opposite transition to achieve improved performance or power consumption.
    Type: Application
    Filed: November 25, 2013
    Publication date: April 2, 2015
    Applicant: ARM LIMITED
    Inventors: Srinivasan SRINATH, Ambica ASHOK, Fakhruddin Ali BOHRA
  • Publication number: 20140111246
    Abstract: A switching device driver, which includes switching circuitry and a first capacitive element, which is coupled to the switching circuitry, is disclosed. The switching circuitry receives a logic level input signal and provides a switching control output signal to a switching device based on the logic level input signal. When the logic level input signal has a first logic level, the switching circuitry charges the first capacitive element. When the logic level input signal transitions from the first logic level to a second logic level, the switching circuitry at least partially discharges the first capacitive element to rapidly transition the switching control output signal, thereby causing the switching device to quickly change states.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Applicant: CREE, INC.
    Inventor: Robert J. Callanan
  • Publication number: 20140028344
    Abstract: Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high, threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by “pre-heating” the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given minimum temperature at which the IC is designed or guaranteed) to properly function at are provided.
    Type: Application
    Filed: September 30, 2013
    Publication date: January 30, 2014
    Applicant: Broadcom Corporation
    Inventors: Paul Penzes, Mark Fullerton
  • Patent number: 7911436
    Abstract: A shift register includes a plurality of stages connected to one another to sequentially generate output signals. Each of the stages has a plurality of output terminals, and each of the output terminals is connected to at least two gate lines and outputs a first output voltage alternately to the at least two gate lines to turn on thin film transistors.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: March 22, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Woo Lee, Kye-Hun Lee, Jong-Hwan Lee
  • Patent number: 7893723
    Abstract: Devices and methods are disclosed for logic gate devices to provide reduced leakage while improving performance. The device is configured for low leakage logic application where high threshold voltage devices are used to reduce leakage at the expense of reduced logic speed. Better performance is achieved than a high threshold voltage stack.
    Type: Grant
    Filed: December 29, 2007
    Date of Patent: February 22, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Andrew Marshall
  • Patent number: 7884647
    Abstract: There is provided an output driver, which includes a pre-driver configured to generate a main driving control signal in response to a data signal, a main driver configured to drive an output terminal in response to the main driving control signal, an auxiliary driving control signal generator configured to generate an auxiliary driving control signal having an activation interval corresponding to the data signal and an interval control signal, and an auxiliary driver configured to drive the output terminal in response to the auxiliary driving control signal.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: February 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyung-Hoon Kim, Dae-Han Kwon, Taek-Sang Song
  • Patent number: 7768296
    Abstract: A current boost module receives a signal from the input and the output of a buffer to determine whether the buffer is transitioning between logic states. When the buffer is transitioning, a boost current is provided to a load connected to the buffer output to supplement the current from buffer output, thereby facilitating transition of a signal at the load. The current boost module can shut down the boost current before the signal at the load completes its transition from one logic state to the other.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: August 3, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kiyoshi Kase, Dzung T. Tran
  • Patent number: 7663406
    Abstract: An output circuit including an input terminal; an output terminal; a PMOS transistor connected with a positive side of a power voltage and the output terminal; a NMOS transistor connected with a negative side of the power supply voltage and the output terminal; a first inverter, to which a gate voltage of the PMOS transistor is input and which exhibits hysteresis in threshold voltage; and a second inverter, to which a gate voltage of the NMOS transistor is input and which exhibits hysteresis in threshold voltage, wherein an OR logic signal of the input signal and a signal obtained by inverting an output signal from the second inverter is input to a gate of the PMOS transistor, and an AND logic signal of the input signal and a signal obtained by inverting an output signal from the first inverter is input to a gate of the NMOS transistor.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: February 16, 2010
    Assignee: Ricoh Company, Ltd.
    Inventor: Koichi Hagino
  • Patent number: 7639039
    Abstract: A semiconductor integrated circuit includes a CMOS controlled inverter consisting of series-connected PMOS and NMOS transistors. The source of the NMOS transistor is coupled to a ground line through an additional NMOS transistor for power gating of voltage VSS. The source of the PMOS transistor can be coupled to a power supply line through an additional PMOS transistor for power gating of voltage VDD. The inverter receives an input signal IN and its complementary version that has transitioned earlier than the input signal. In response to the input signal, the inverter produces an output signal. A NAND gate that receives the output signal and the complementary input signal controls the power gating NMOS transistor. A NOR gate that receives the output signal and the complementary input signal controls the power gating PMOS transistor.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: December 29, 2009
    Assignee: Mosaid Technologies Incorporated
    Inventor: HakJune Oh
  • Publication number: 20090273362
    Abstract: A booster circuit for reducing the nominal latency of a logic gate. The booster circuit includes a charge sharing mechanism to transfer a stored charge to the output of the logic gate in response to a logic state transition on the input of the logic gate. The transfer of stored charge also reduces the charge drawn from the supply during the output transition.
    Type: Application
    Filed: July 23, 2009
    Publication date: November 5, 2009
    Applicant: Sun Microsystems, Inc.
    Inventor: Scott M. Fairbanks
  • Patent number: 7512850
    Abstract: Some embodiments provide a configurable integrated circuit (IC) that has several configurable circuits and several user design state (UDS) circuits. The UDS circuits store user-design state values. The configurable IC also includes a debug network communicatively coupled to the UDS circuits. The debug network is for retrieving the user-design state values of several UDS circuits at various stoppages of the operation of the IC without retrieving configuration data that is used to configure the configurable circuits of the IC. The retrieved user-design state values at each stoppage are used as the checkpointed state of the IC while debugging the IC. In some embodiments, the debug network allows the checkpointing of only certain portions of the configurable IC.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: March 31, 2009
    Assignee: Tabula, Inc.
    Inventors: Jason Redgrave, Brad Hutchings, Herman Schmit, Steven Teig, Tom Kronmiller
  • Patent number: 7504863
    Abstract: A half-duplex communication system may include one or more low-voltage differential signaling half-duplex transceivers. Each transceiver may include a plurality of input terminals receiving a plurality differential data signals, an input driver transferring the differential data signals from differential transmission lines through output terminals, and an output driver transferring the differential data signals from the input terminals through the differential transmission lines and out to one of the first and second transceivers via the non-inverse and inverse transmission lines. The differential data signals may be transferred in response to the differential data signals at the input terminals and at the output terminals of the input driver. Each transceiver may include a pre-driver configured to shift a reference voltage level of differential data signals input thereto from the input terminals and which are to be supplied to the output driver therefrom.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: March 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jin Hyun Kim
  • Patent number: 7498833
    Abstract: A semiconductor integrated circuit comprises logic cones having a structure in which substrates thereof are isolated from each other and substrate potentials can be controlled, and a potential switching section for supplying a substrate voltage from any of a first substrate bias supply potential and a second substrate bias supply potential to the logic cone. A signal output by a logic cone previous to a logic cone whose substrate potential is controlled is input as a trigger signal to the substrate supply potential switching section.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: March 3, 2009
    Assignee: Panasonic Corporation
    Inventor: Isao Tanaka
  • Publication number: 20080238474
    Abstract: A booster circuit for reducing the nominal latency of a logic gate. The booster circuit includes a charge sharing mechanism to transfer a stored charge to the output of the logic gate in response to a logic state transition on the input of the logic gate. The transfer of stored charge also reduces the charge drawn from the supply during the output transition.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Applicant: Sun Microsystems, Inc.
    Inventor: Scott M. Fairbanks
  • Publication number: 20080238473
    Abstract: A push-pull pulse register circuit. The push-pull pulse register circuit includes a first logic inverter having first-inverter input and first-inverter output, a second logic inverter having second-inverter input and second-inverter output, a third logic inverter having third-inverter input and third-inverter output and configured to receive logic input data at the third-inverter input, a first logic gate having first-gate input, first-gate output, and first-gate control input, and a second logic gate having second-gate input, second-gate output, and second-gate control input.
    Type: Application
    Filed: March 27, 2007
    Publication date: October 2, 2008
    Applicant: STMICROELECTRONICS, INC.
    Inventor: Thomas Zounes
  • Patent number: 7397271
    Abstract: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: July 8, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mototsugu Hamada, Tsuyoshi Nishikawa, Toshiyuki Furusawa