Abstract: A high-voltage tolerant circuit includes a first level shifter responsive to an input signal having a first logic high voltage and a first logic low voltage for providing a first intermediate signal having the first logic high voltage and a second logic low voltage referenced to a second reference voltage higher than the first logic low voltage, a second level shifter responsive to the input signal for providing a second intermediate signal having a second logic high voltage referenced to a first reference voltage lower than the first logic high voltage, and the first logic low voltage, an output stage responsive to the first and second intermediate signals for providing an output signal having the first logic high voltage and the first logic low voltage, and a reference voltage generation circuit providing the second logic high and second logic low voltages without drawing current from the reference voltage generation circuit.

Abstract: The circuit device includes a first MOS transistor of a first conductivity type a source of which is coupled to a first power supply voltage node, a second MOS transistor of a second conductivity type a source of which is coupled to a second power supply voltage node, a first variable resistance circuit which is coupled between a drain of the first MOS transistor and an output node, and which includes a first switch, and a second switch coupled between the drain of the first MOS transistor and the second power supply voltage node. The control circuit performs control of making the first switch OFF and making the second switch ON when the clock signal fails to be output from the output node, and making the first switch ON and making the second switch OFF when the clock signal is output from the output node.

Abstract: Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.

Abstract: To suppress the generation of a shoot-through current in a Schmitt trigger inverter circuit, a Schmitt trigger inverter circuit SINVa includes: a CMOS inverter CI having the input and output connected to the input and output of the Schmitt trigger inverter circuit, respectively; a first transistor MN3 having the gate connected to the output of the CMOS inverter; and a first current limiting element DEP1 connected to the first transistor in series.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: A memory interface latch including a data NAND gate and a feedback gate can be created within an integrated circuit (IC). When a feedback node is driven low, the data NAND gate can drive an inverted value of a memory array bitline input to a data output of the memory interface latch within a time of one gate delay. A feedback gate can, in a functional mode, during one phase of a clock signal, drive the feedback node high and during the other phase of the clock signal, drive the feedback node to a complement the data output. The feedback gate can be also, in an LBIST write-through mode, drive the feedback node to the value of a WRITE_DATA input. The feedback gate can be also, in a fence mode, drive the feedback node to fixed logic value.

Abstract: An I/O cell includes a reference output circuit that has a reference output transistor, connected to an output terminal, and has a reference pre-buffer, the reference pre-buffer driving the reference output transistor according to an input signal of the input terminal; adjustment output circuits that have an adjustment output transistor, connected to the output terminal and connected in parallel with the reference output transistor, and have an adjustment pre-buffer, the adjustment pre-buffer driving the adjustment output transistor according to the input signal; and a gate voltage detection control circuit that monitors all of gate voltages applied to the output transistors included in the reference output circuit and the adjustment output circuit. The gate voltage detection control circuit generates a timing when all of the output transistors are turned OFF when switching the H/L level of the output current to the load according to the change of the input signal.

Abstract: The present disclosure provides circuits and methods for generating clock-signals. An exemplary clock-signal generation circuit includes a delay buffer unit; an inverter unit coupled to the delay buffer unit; a first delay unit having a first NAND Boolean calculation sub unit, a first sub delay unit and a first level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a first delayed clock-signal; and a second delay unit having a second NAND Boolean calculation sub unit, a second sub delay unit and a second level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a second delayed clock signal.

Abstract: This disclosure provides systems, methods and apparatus for an all n-type transistor inverter circuit. A circuit can include an input thin film transistor (TFT), a pull-down TFT, a discharge TFT, a first pull-up TFT, a second pull-up TFT, and a floating capacitor. The circuit also can include first and second low-voltage voltage sources and first and second high-voltage voltage sources. The TFTs, the capacitor, and the voltage sources can be coupled such that an output of the circuit is the logical opposite of an input of the circuit. In some implementations, the circuit can exhibit zero DC current in both logic states and can output voltages substantially equal to the voltage output by the first low-voltage voltage source and the second high-voltage voltage source. In some implementations, the circuit can be used to construct D flip-flops, buffers, and controllers for an active matrix electronic display.

Abstract: There is provided an input buffer circuit having hysteresis characteristics. The input buffer circuit includes: a first operating unit performing a NOR operation on an input signal and a first signal; a second operating unit performing a NAND operation on the input signal and a second signal; and an inverting unit inverting outputs of the first and second operating units to generate a second signal and a first signal, respectively, wherein reference levels of the first and second operating units determining a high or low level of the input signal are set to be different.

Abstract: There is provided an input buffer circuit having hysteresis characteristics. The input buffer circuit includes: a first operating unit performing a NOR operation on an input signal and a first signal; a second operating unit performing a NAND operation on the input signal and a second signal; and an inverting unit inverting outputs of the first and second operating units to generate a second signal and a first signal, respectively, wherein reference levels of the first and second operating units determining a high or low level of the input signal are set to be different.

Abstract: Provided is a gate signal line driving circuit including: 2n clock signal lines where 2n-phase clock signals are input in the normal order of the sequence in normal-directional scanning and in the inverse order of the sequence in inverse-directional scanning, respectively; and a plurality of basic circuits, each being connected with the 2n clock signal lines and outputting a gate signal from an output terminal, in which each of the basic circuits includes a high-voltage applying switching circuit where one clock signal line is connected to an input side and applies a voltage applied to the clock signal line to the output terminal and an off-signal applying switching circuit that applies an off-voltage to a switch of the high-voltage applying switching circuit, and a clock signal line where a clock signal having an inverse phase is connected to a switch of the off-signal applying switching circuit.

Abstract: The present invention provides a current segmentation circuit for optimizing output waveform from high speed data transmission interface, which comprises a four current sources controlled by four switches to segment current so as to control the rising and falling time of the high speed transmission data, and to match the delay of the current control signal and the delay of the data, wherein the four current sources are I1, I2, I3 and I4, and the current control switches are K1, K2, K3 and K4, wherein I1+I2=I3+I4, wherein the switches K1 and K3 control the current I1/I3 to flow into DP/DM line, and the switches K2 and K4 control the current I2/I4 to flow into DP/DM line. The present invention can depress overshoot and eliminate turning point in the waveform.

Abstract: A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.

Abstract: The Schmitt circuit includes a first logic circuit that receives an output signal of the input logic circuit and has a first threshold voltage. The Schmitt circuit includes a second logic circuit that receives the output signal of the input logic circuit and has a second threshold voltage lower than the first threshold voltage. The Schmitt circuit includes a variable resistance circuit that adjusts the threshold voltage of the input logic circuit in accordance with an output signal of the first logic circuit and an output signal of the second logic circuit.

Abstract: There is provided a data acceleration device comprising a pull-up driver for driving a pull-up in response to the signal level on a first node, a pull-down driver for driving a pull-down in response to the signal level on the first node, a first pull-up circuit for pull-up driving a second node which is electrically coupled with the first node, in response to an output signal from the pull-up driver, a first pull-down circuit for pull-down driving the second node, in response to an output signal from the pull-down driver, a delay circuit for delaying a signal from the second node by a preset time to output a delayed signal, a first switch for switching an operation of the first pull-up circuit in response to an output signal from the delay circuit, and a second switch for switching an operation of the first pull-down circuit in response to the output signal from the delay circuit. Also, there is presented a data transmission apparatus including the data acceleration device.

Abstract: There is provided a semiconductor integrated circuit device with a filer circuit serving for eliminating a glitch contained in a logic signal supplied to the device, wherein the filter circuit includes: a first delay circuit activated within a certain period after each rising edge timing of input logic signals to delay the rising edge; a second delay circuit activated within a certain period after each falling edge timing of the input logic signals to delay the falling edge; and an output driver controlled by outputs of the first and second delay circuits to output delayed logic signals to an output node in response to the input logic signals.

Abstract: A method of transmitting adjacent signals is disclosed. Sensing is performed on signals in the group and adjacent signals are either switched or delayed if the adjacent signals are switching at the same time. The method is used in networks where coupling and capacitance effects are possible.

Abstract: Provided is an input buffer whose input capacitance presented to input signals can be reduced. The input buffer includes a first differential amplifier which compares the sizes of a first input signal and a second input signal and outputs an output signal as the result of the comparison; a second differential amplifier which compares the sizes of the first input signal and a reference voltage and outputs a second output signal as the result of the comparison; and a third differential amplifier which compares the sizes of the second input signal and the reference voltage and outputs a third output signal as the result of the comparison, wherein the first differential amplifier shares transistors, to which the first and second input signals are input, with the second and third differential amplifiers. The first differential amplifier operates only in a differential operation mode, and the second and third differential amplifiers operate only in a single operation mode.

Abstract: A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer/driver without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer/driver may be an inverter, non-inverter, or provide a multiple input logic function.

Abstract: A noninverting transistor switch having only a first terminal, a second terminal and a third terminal includes a transistor connected to the second and third terminals, the transistor having an on switching state in which current is able to pass between the second and third terminals and an off switching state in which current is interrupted from passing between the second and third terminals. The transistor switch also includes a voltage stabilizer connected to the second and third terminals. The transistor switch further includes a CMOS inverter connected to the first terminal, the second terminal, the transistor and the voltage stabilizer. In use, the CMOS inverter interrupts the passing of current between the voltage stabilizer and the second terminal when the transistor is in its off switching state.

Abstract: A termination resistor circuit includes a first and second passive resistive elements coupled in series between a common mode voltage and a signal node, and a plurality of active resistive elements coupled in parallel with the first passive resistive element. The active resistive elements may be selectively enabled by corresponding control signals to provide various numbers of parallel resistances across the first passive resistive element, thereby tuning the termination resistor circuit to a desired resistance value.

Abstract: A semiconductor integrated circuit which is supplied with a first power supply voltage and a second power supply voltage from outside so as to operate incorporated circuits, and outputs data at an output terminal, includes an internal circuit that carries out a predetermined function for an input signal, an output circuit which includes a first circuit for converting the signal from the internal circuit into an output signal and a second circuit containing a final stage buffer circuit which outputs, depending on the signal from the first circuit, data to the output terminal; and a switching circuit that switches a power supply voltage supplied to the second circuit, to either the first power supply voltage or the second power supply voltage. A voltage obtained by decreasing the first power supply voltage is supplied to the internal circuit. The first power supply voltage is supplied to the first circuit.

Abstract: A delay circuit includes an output circuit including first and second output elements. The first and second output elements are connected serially between a first power supply source and a second power supply source. The delay circuit further includes a delay element, which is coupled between a first input circuit and an output circuit to generate a first control signal that is delayed with respect to the input signal. The delay circuit still further includes a first node coupled between the delay element and one of the first and second output elements; and a second node, coupled to the other output elements to supply a second control signal having substantially no delay with respect to the input signal.

Abstract: The present invention is directed to an improved system and method for transmitting and receiving digital data. In order to counter the spatial filtering effects of a digital data bus, data is spatially filtered by a driver before being sent on the digital data bus to its destination. In the alternative, the data may be spatially filtered by a receiver after being sent on the digital data bus. The spatial filter may include one or more current-limiting elements, such as a resistor or a transistor, coupled between the power supply and the various buffers on the bus. Such a configuration results in a lowering of the crosstalk and ground bounce present between adjacent lines on a data bus.

Abstract: An intermediate voltage control circuit maintains the signal line at a stable intermediate potential. The circuit comprises a first n-channel transistor; a second p-channel transistor; a monitoring circuit for determining a potential level of a signal line connected to the output node; and a control circuit for sending first and second control signals to a gate of each of the first and second transistors so as to prevent a feedthrough current from flowing in the transistor.

Abstract: An inverter circuit includes a first transistor connected between an input terminal and a gate of a second transistor, a second transistor connected between power supply voltage and an output terminal, a third transistor connected between an input terminal and a gate of a fourth transistor and a fourth transistor connected between a ground and the output terminal.

Abstract: A noise suppression circuit for suppressing above-ground noise is disclosed. The noise suppression circuit for suppressing noises includes a first inverter, a second inverter, and a one-shot circuit. The first inverter, connected to an input line, switches at a first voltage value above which a noise-coupling event is suspected. The second inverter, also connected to the input line, switches at a second voltage value above which a full-switch input is assumed. A first transistor is coupled to the input line. A second transistor passes an output of the second inverter to a gate of the first transistor when an output of the one-shot circuit is high. The third transistor holds the gate of the first transistor low when the output of the one-shot circuit is low.

Abstract: A noise canceling circuit is provided in a dynamic circuit that includes a high fan-in domino gate. The noise canceling circuit decouples noise from neighboring wires in the dynamic circuit that is injected into a wire that controls the domino gate.

Abstract: In order to improve the robustness against electrostatic discharge, when power source terminal and ground terminal are open, of a semiconductor device having a first, a second and a third inverter that are connected in a cascade arrangement, the semiconductor device is provided not only with a first input protection circuit for guiding positive electrostatic discharges, that are applied from outside to a signal input terminal, to a power source line, and a second input protection circuit for guiding negative electrostatic discharges, that are applied from outside to the signal input terminal, to a ground line, but also an internal protection circuit for guiding electrostatic discharges that have been guided by the first input protection circuit to the power source line and flow from a P-channel MOS transistor in the second inverter towards the third inverter, to the ground line.

Abstract: A data receiver is provided for stabilizing a reference voltage to which input data is compared. The data receiver includes a differential amplification flip flop for comparing input data to a reference voltage in response to a clock signal, an amplifier for amplifying the results of the comparison, a latch for storing the logic level of the input data, and a counter coupling circuit for reducing the variation of the reference voltage caused by the operation of the differential amplification flip flop in response to an inverted clock signal. In the data receiver, the reference voltage is stably preserved without minimized variation. Also, there is substantially no consumption of direct current (DC) when the data receiver operates.

Abstract: An input buffer for an integrated circuit and providing reduced sensitivity to input noise present in a transmission line environment. This input buffer deskews an input signal where the rise time is much slower than the fall time, such as that from an open-collector output driver, so that the rising edge propagation delay and falling edge propagation delay of the input buffer are approximately equal.

Abstract: The present invention provides a centralized amplifier-accelerator a tri-state bus. The centralized amplifier-accelerator utilizes the module drivers as pre-drivers to the amplifier-accelerator. The centralized amplifier-accelerator is located physically in the center of the chip. This central amplifier-accelerator consists of a highly sensitive input sense circuit which detects voltage transition at very near the N-channel threshold for rising transitions and at very near the P-channel threshold for falling transitions. Once the sense circuit threshold is met, the output driver is triggered to drive the bus.

Abstract: An off-chip driver circuit having a set of input terminals and an output terminal, a pull-up transistor having a controllable path connected between a first power supply and the output terminal of the off-chip driver circuit, a pull-down transistor having a controllable path connected between a second power supply and the output terminal of the off-chip driver circuit, a first controllable path for applying a first voltage at one of the input terminals to a control terminal of the pull-up transistor, the first controllable path functioning in response to voltages at the output terminal below a first value, a second controllable path for applying a second voltage greater than the first voltage to the control terminal of the pull-up transistor, the second controllable path functioning in response to voltages at the output terminal above the first value.

Abstract: An input/output (I/O) circuit with a high I/O voltage tolerance is provided for use in conjunction with an IC device that operates with two system voltages, such as 3.3 V and 5 V. The particular circuit configuration of this I/O circuit allows it to be fabricated using the Single Gate-Oxide technology instead of the Double Gate-Oxide technology, so that the manufacturing cost can be reduced as compared to the prior art. Moreover, this I/O circuit allows an output impedance lower than that of the prior art, allowing the signal transmission speed via this I/O circuit to be increased by about 30% as compared to the prior art. It can also help eliminate the problems of poor gate oxide reliability, PN junction inversion, and PMOS leakage that otherwise occur in the prior art. Furthermore, this I/O circuit can help eliminate the DC leakage current in the input-stage circuit, so that the power consumption can be reduced compared to the prior art.

Abstract: An hysteresis input buffer includes a first CMOS inverter generating a node signal, a second CMOS inverter coupled to the first CMOS inverter, inverting the node signal from the first CMOS inverter, and producing an intermediate signal, and a hysteresis control circuit coupled to the second CMOS inverter, receiving the intermediate signal, and producing an output signal having a low level during a predetermined delay time and a high level after the predetermined delay time has elapsed.

Abstract: This invention describes an improved design of CMOS. digital input circuits. This improvement reduces the switching level uncertainty range and thus increases the noise margin, compensating for manufacturing process variations. This improvement is achieved by providing resistive compensation devices in series with the P-type and the N-type CMOS transistors in the first stage of a multistage digital input circuit. These resistive devices can be implemented by means of resistors or by means of MOSFET devices which provide the required resistive function. These compensation devices modify the input-output voltage transfer characteristics of the first stage so as to reduce the switching level variation at the input to the circuit. The resulting digital input circuit has a greater tolerance to input noise levels. The improvement provided by this invention is particularly important as integrated circuits design trend is to operate with lower supply voltages.

Abstract: An input circuit for an integrated circuit for interfacing an external signal line external to the integrated circuit includes first circuit means having an input that may be coupled to the signal line to provide a regenerated signal at their output, and second circuit means having an input coupled to receive the regenerated signal and driving the external signal line. The external signal line can thus be maintained at a predetermined logic level, even in the absence of any driving on the external signal line. Third circuit means are provided that are capable of providing to the second circuit means a supply voltage equal to the greater of a supply voltage of the integrated circuit to which the input circuit belongs, and the voltage existing on the external signal line.

Abstract: An output buffer includes a p-channel transistor, and first and second n-channel transistors. The p-channel transistor has one of a source and drain which is connected to power supply and the other which is connected to an output node connected to an output terminal. The first n-channel transistor has one of a source and drain which is grounded and the other which is connected to the output node. The second n-channel transistor is series-connected to the p-channel transistor between a power supply and the output node and receives at a gate a power supply potential level which rises at substantially the same time as the power supply upon ON operation.

Abstract: The present invention is directed to an input buffer circuit comprising a first inverter for receiving an input signal, a second inverter for receiving an output signal from the first inverter, and a transition time detecting circuit for detecting a transition time of an output signal of a sense amplifier which amplifies and reads a logic value stored in a memory cell. The transition time detecting circuit generates a control signal for a delay depending on a detected level of the transition time. A logic threshold control circuit is provided for feeding the control signal from the transition time detecting means back to an input terminal of said second inverter to control a hysteresis interval of a logic threshold level of an output signal produced in response to the input signal. An output signal from the second inverter is delayed by a delay circuit which provides the delayed output signal to the logic threshold control circuit.

Abstract: An input buffer includes a first CMOS inverter (400) made up of a PMOS transistor (602) connecting Vdd to the buffer output and an NMOS transistor (604) connecting the buffer output to Vss. NMOS transistors (404) and (414) have with series connected source to drain paths to connect the buffer output to Vss in conjunction with transistor (604) of inverter (400). PMOS transistors (402) and (412) have series connected source to drain paths connecting Vdd to the buffer output in conjunction with transistor (602). To control transistors (402, 404, 412 and 414) an inverter (420) is connected from the buffer output to the gates of transistors (402 and 404), and inverters (431, 432, 433, and 440) are connected between the buffer input and the gates of transistors (412 and 414).

Abstract: Switching on a first line, from a first signal level to a second level, tends to induce a change in signal level of a second line. To reduce induced noise, the second line is connected to a power rail for a predetermined time interval, responsive to the switching on the first line. The connecting for the time interval tends to counteract the change induced in the second line by the signal of the first line.

Abstract: An input/output circuit with wide voltage tolerance is using a feedback circuit for increasing the voltage tolerance. A single gate oxide structure is fabricated instead of a dual gate oxide structure.

Abstract: Circuits and methods of suppressing noise on a signal line are disclosed. A noise suppression pull-down circuit is coupled to a signal line which couples the output element of a first logic element to the input terminal of a second logic element. When the first logic element drives a logic low onto the signal line, the noise suppression pull-down circuit is activated to provide a weak pull-down on the signal line. When the first logic element drives a logic high onto the signal line, the noise suppression pull-down circuit is deactivated to prevent interference with the first logic element.

Abstract: The present invention provides a circuit for increasing the noise tolerance of a receiving gate. This is accomplished by separating the circuit which sets the positive going threshold, from the circuit which sets the negative going threshold. This eliminates the need of making a design compromise equally suitable to both these threshold requirements. It is achieved by separating the logical drive for switching from a low to a high from the logical drive for switching from a high to a low. Alternate embodiments are presented. In one embodiment, separate drivers for PFET and NFET inverter inputs are employed together with an output latch circuit which prevents the output from being in a floating state. In an alternate embodiment the latch is included in-line with the gate output. An implementation of the invention in a two input AND gate is also described.

Abstract: A dynamic logic signal repeater includes a complementary dynamic logic circuit with an input node to receive an input signal and an output node storing a precharge signal. The complementary dynamic logic circuit configuration, transistor sizing, and the use of a precharge driver results in a signal transition trip point for the precharge signal on the output node that is substantially equivalent to the signal transition trip point of a static logic circuit. Thus, the dynamic logic signal repeater has improved noise immunity. An evaluation locking transistor is connected to the complementary dynamic logic circuit and the output node. The evaluation locking transistor prevents the charging of the output node during a dynamic logic evaluation period.

Abstract: Disclosed is a circuit for removing noise components included in a signal which an oscillator generates by using an integrator and hysteresis characteristic. The signal is oscillated by an oscillator. A square-wave generating inverter receives a sine wave signal including noise components oscillated by a quartz crystal oscillator circuit and then generates a square-wave signal having improved RC and integrator characteristics, and provides the generated square-wave signal to a Schmitt trigger. The Schmitt trigger receives the square-wave signal including the noise components from the square-wave generating inverter and removes the noise components included in the received square-wave signal. The circuit can remove noise components included in a signal oscillated by an oscillator due to a surrounding influence such as a temperature. Therefore, state clocks which is used in a microprocessor and a microcontroller, may be generated.

Abstract: A method for asserting signals onto an output line connected to a passive external pull-up resistor by using a fast edge rate signal driver is provided. The fast edge rate signal driver has first, second and third pull-down predrivers, first, second and third pull-up predrivers, first and second delay elements, and first, second and third output devices, and a PMOS and an NMOS current controller, and each of the output devices has one output terminal coupled to each other forming the output line.

Abstract: A method and apparatus that controls and modulates the amount of hysteresis in a buffer in response to changes in operating conditions. The buffer comprises a first stage switching element and a hysteresis control element. The first stage switching element is configured to have a DC voltage trip point. As an input voltage, transitioning from a first state to a second state, is applied to the first stage switching element, the first stage switching element transitions as the input voltage reaches the DC voltage trip point. The transition of the first stage switching element enables the hysteresis control element to provide a feedback path biasing the first stage switching element. Consequently, as the input voltage transitions from the second logic level to the first logic level, the first stage switching element transitions at a voltage level offset from the DC trip point to provide hysteresis in the buffer.

Abstract: Dynamic CMOS circuits are provided with improved noise immunity. These circuits comprise first and second stacked NFET devices connected respectively between ground and a first node. An input node is coupled to the first NFET device closest to ground and a clock node coupled to the second NFET device closest to the first node. A PFET device is connected between the input node and a node formed by the stacked NFET devices. The first NFET device and the PFET device form an inverter for receiving an input signal, the switch point of the inverter being adjustable by adjusting the PFET/NFET ratio of the inverter, thereby increasing the noise immunity of the circuit.