Signal Sensitivity Or Transmission Integrity Patents (Class 326/21)
  • Patent number: 10809672
    Abstract: A measurement system includes a control device which controls a control target device in real time and transmits control data to a terminal device, and a measuring instrument which acquires data indicating a physical status of the control target device and transmits the data as measurement data to the terminal device. The control device includes a control unit and a sequence control unit, and the control unit transmits a timing signal to the measuring instrument. The control device transmits the control data that includes a piece of time information based on the timing signal to the terminal device. The measuring instrument transmits the measurement data that includes a piece of time information based on the timing signal to the terminal device. The terminal device compensates for a delay between the control data and the measurement data on the basis of the pieces of time information.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: October 20, 2020
    Assignee: FANUC CORPORATION
    Inventor: Noriaki Hatanaka
  • Patent number: 10790847
    Abstract: Apparatus and associated methods relate to unit circuits that having a number of capacitors and/or buffers controlled by two different control signals, capacitors and/or buffers that receiving, through routing, a same control signal from a control circuit are physically placed adjacent without crossing routings that connects capacitors and/or buffers controlled by a different control signal. In an illustrative example, a first capacitor may be configured to receive a first control signal through an inverting buffer, and a second capacitor may be configured to receive the first control signal through a non-inverting buffer, the inverting buffer and the non-inverting buffer may be provided by an integrated buffer structure. By arranging the physical positions of the capacitors and/or buffers, wire capacitances of the unit circuit may be advantageously reduced.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: September 29, 2020
    Assignee: XILINX, INC.
    Inventor: Pedro W. Neto
  • Patent number: 10732697
    Abstract: Various aspects are described herein. In some aspects, the disclosure provides techniques for reducing latency in switching computing cores of a computing system between operating modes. Certain aspects provide a computing device including a plurality of computing cores, each configured to operate in any one of a plurality of operating modes. The computing device further includes a first voltage rail and a plurality of components, each associated with one of the computing cores. The computing device further includes a plurality of switches, each switch configured to selectively couple a corresponding one of the plurality of components to the first voltage rail. The computing device further includes a controller configured to determine a current operating mode of each of the plurality of computing cores and switch the plurality of switches at a first selected switching rate based on the determined current operating mode of each of the plurality of computing cores.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: August 4, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Raghavendra Srinivas, Abhijit Joshi, Bharat Kavala, Abinash Roy
  • Patent number: 10719097
    Abstract: A voltage regulation circuit is suitable to provide an output voltage to a core circuit. The voltage regulation circuit includes a pad, a pull-low unit, a first controlling unit, a second controlling unit and a voltage regulation circuit. The pad receives and provides an input voltage. The pull-low unit generates a pull-low voltage according to the input voltage. The first controlling unit generates a first controlling signal according to the input voltage and the pull-low voltage. The second controlling unit generates a second controlling signal according to the input voltage and the first controlling signal. The voltage regulation unit regulates the input voltage according to the first controlling signal and the second controlling signal, so as to generate the output voltage.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: July 21, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jung-Tsun Chuang, Shao-Chang Huang, Wen-Tsung Wang, Chieh-Yao Chuang, Chi-Hung Lo
  • Patent number: 10712769
    Abstract: A clock distribution network and method of distributing a clock signal is disclosed. In one embodiment, a clock distribution network is coupled to at least a first circuit. The clock distribution network includes a clock source configured to generate a differential clock signal and provide it to a current mode logic (CML) driver. The CML driver is configured to transmit the clock signal over a differential signal path. A CML receiver is coupled to receive the clock signal via the differential signal path.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: July 14, 2020
    Assignee: Oracle International Corporation
    Inventors: Dabin Zhang, Philip P. Kwan, Zuxu Qin
  • Patent number: 10712772
    Abstract: A data-processing-circuit comprising: a clock-input-terminal configured to receive a clock-signal; a data-output-terminal configured to provide a data-output-signal; an adjustable-driver-buffer configured to: receive a data-signal; and apply a driver-strength-value to the data-signal in order to provide a data-output-signal, wherein the current level of the data-output-signal is based on the driver-strength-value; and a driver-control-module comprising: a time-alignment-module configured to: process the clock-signal and the data-output-signal in order to determine a timing-delay-signal that is representative of a time delay between: a transition in the clock-signal; and a transition in the data-output-signal; provide the driver-strength-value for the adjustable-driver-buffer based on the timing-delay-signal and a target-delay-signal, wherein the driver-strength-value is for reducing a difference between: the timing-delay-signal; and the target-delay-signal.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: July 14, 2020
    Assignee: NXP B.V.
    Inventors: Antonius Martinus Jacobus Daanen, Guillaume Lemaitre, William Gerard Leijenaar, Michael Levi
  • Patent number: 10700888
    Abstract: Various aspects provide for a multiplexer for high-speed serial links. For example, a system can include a first stage data path multiplexer circuit and a second stage data path multiplexer circuit. The first stage data path multiplexer circuit comprises a first inverter circuit to select a first data signal from a set of data signals and a second inverter circuit to select a second data signal from the set of data signals. The first inverter circuit comprises a first set of inverters and a first set of transmission gates. The second inverter circuit comprises a second set of inverters and a second set of transmission gates. The second stage data path multiplexer circuit is configured as a third inverter circuit to select the first data signal or the second data signal as an output data signal. The third inverter circuit comprises a third set of inverters and a third set of transmission gates.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 30, 2020
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Naga Rajesh Doppalapudi, Echere Iroaga
  • Patent number: 10698692
    Abstract: An asynchronous pipeline includes a first stage and one or more second stages. A controller provides control signals to the first stage to indicate a modification to an operating speed of the first stage. The modification is determined based on a comparison of a completion status of the first stage to one or more completion statuses of the one or more second stages. In some cases, the controller provides control signals indicating modifications to an operating voltage applied to the first stage and a drive strength of a buffer in the first stage. Modules can be used to determine the completion statuses of the first stage and the one or more second stages based on the monitored output signals generated by the stages, output signals from replica critical paths associated with the stages, or a lookup table that indicates estimated completion times.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: June 30, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Greg Sadowski, John Kalamatianos, Shomit N. Das
  • Patent number: 10693444
    Abstract: A spur cancellation circuit for use in a mixed signal circuit. A spur cancellation circuit includes a clock generation circuit, a flip-flop bank, and a control circuit. The clock generation circuit is configured to generate a clock signal. The flip-flop bank is coupled to the clock generation circuit, and includes a plurality of flip-flops configured to be clocked by the clock signal. The control circuit is coupled to the clock generation circuit and the flip-flop bank. The control circuit is configured to individually enable one or more of the flip-flops to change state responsive to the clock signal and consume a predetermined amount of power; and to provide a data value to be clocked into the flip-flops.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: June 23, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nagalinga Swamy Basayya Aremallapur, Eeshan Miglani, Visvesvaraya Pentakota, Praxal Sunilkumar Shah
  • Patent number: 10693462
    Abstract: Techniques are described for ground-intermediating buffering that can effectively use the reference grounds of the circuit domains on either side of a buffer stage to generate one or more intermediated grounds for one or more signal buffers. For example, one of the reference grounds has a first amount of ground noise, the other of the reference grounds has a second amount of ground noise that is greater than or less than the first amount, and the intermediated grounds are generated to have respective amounts of ground noise that are between the first and second amounts. The ground intermediating buffer can perform signal buffering with respect to the intermediated ground(s), thereby reducing ground noise coupling across the circuit domains through both the signal and ground paths of the buffer stage.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: June 23, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Kaveh Moazzami, Faisal Hussein, Ahmed Emira
  • Patent number: 10693674
    Abstract: Systems, methods, and apparatus are described that enable a device to indicate availability of priority data to be communicated over a half-duplex serial bus without waiting for an ongoing transmission to be completed. In-datagram critical signaling is accommodated without breaking backward compatibility. A method implemented at a transmitting device coupled to a serial bus includes transmitting a data byte over a first line of the serial bus to a receiving device in accordance with a clock signal transmitted by a master device on a second line of the serial device, detecting a first pulse on the first line of the serial bus during a cycle of the clock signal designated for an acknowledgement or negative acknowledgement by the second device, and processing an alert indicated by the first pulse.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: June 23, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, Richard Dominic Wietfeldt, Radu Pitigoi-Aron
  • Patent number: 10657262
    Abstract: Systems and methods for securing embedded devices via both online and offline defensive strategies. One or more security software components may be injected into firmware binary to create a modified firmware binary, which is functionally- and size-equivalent to the original firmware binary. The security software components may retrieve live forensic information related to embedded devices for use in live hardening of the modified firmware binary while the embedded device is online, dynamically patching the firmware. In addition, the live forensic information may be aggregated with other analytical data identifying firmware vulnerabilities. A vulnerability identification and mitigation system can then identify and inject modifications to the original firmware binary to develop secure firmware binary, which may be imaged and loaded onto one or more embedded devices within a network.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: May 19, 2020
    Assignee: RED BALLOON SECURITY, INC.
    Inventors: Ang Cui, Salvatore J. Stolfo
  • Patent number: 10659015
    Abstract: In certain aspects of the disclosure, an apparatus comprises a latching element having a data input, a first feedback input, a second feedback input, and an output. A pull-up input block is coupled to the data input and has at least a first pull-up input, and a pull-down input block is also coupled to the data input and has at least a first pull-down input. A feedback pull-down block implementing a logic function complementary to the pull-up input block is coupled to a feedback pull-down control device and responsive to the first pull-up input, and a feedback pull-up block implementing a logic function complementary to the pull-down input block is coupled to a feedback pull-up control device and responsive to the first pull-down input. The pull-up input block and pull-down input block are guaranteed not to be enabled concurrently.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: May 19, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Stephen Liles, Jared Buckner
  • Patent number: 10659026
    Abstract: A semiconductor device that can perform voltage monitoring with a small circuit area is provided. The resistive subdivision circuit RDIV performs the resistive subdivision of the input voltage Vin by means of the input ladder resistor (R1-R4), and drives the nMOS transistors MN1-MN3 by the subdivided input voltages Vi1-Vi3 each having different resistive subdivision ratios, respectively. The pMOS transistor MP0 is provided in common for the pMOS transistors MP1-MP3, and configures a current mirror circuit with each of the pMOS transistors MP1-MP3. The bias current generating circuit IBSG supplies a bias current to the pMOS transistor MP1.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masataka Minami
  • Patent number: 10637463
    Abstract: A voltage level shifting circuit includes two PMOS transistors and four NMOS transistors. Sources of the PMOS transistors receive a first supply voltage value, a first PMOS transistor gate coupled with drains of second PMOS and NMOS transistors is a first output, and a second PMOS transistor gate coupled with drains of first PMOS and NMOS transistors is a second output. The first NMOS transistor source is coupled with a third NMOS transistor drain, and the third NMOS transistor gate is a first input. The second NMOS transistor source is coupled with a fourth NMOS transistor drain, and the fourth NMOS transistor gate is a second input. A voltage generating circuit generates a voltage at first and second NMOS transistor gates based on the first supply voltage value and on a signal, the signal behaving based on the first supply voltage value and a different second supply voltage value.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Wen-Han Wang
  • Patent number: 10622988
    Abstract: A power semiconductor module includes an insulated-gate type power semiconductor device, and a drive circuit controlling a gate voltage applied to the power semiconductor device in accordance with an input signal to drive the power semiconductor device so as to turn ON and OFF. The drive circuit includes a variable resistance circuit changing the gate voltage to the power semiconductor device, and a short-circuit state detecting circuit which maintains the resistance value of the variable resistance circuit to be a predetermined value at the time of a normal operation of the power semiconductor device, and which increases the resistance value of the variable resistance circuit so as to be greater than the predetermined value when a short-circuit state of the power semiconductor device is detected to suppress an oscillation in the power semiconductor device.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: April 14, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masahiro Sasaki
  • Patent number: 10599847
    Abstract: Disclosed are devices, systems, apparatus, methods, products, media and other implementations, including a method that includes triggering a beacon circuit combined with a hardware-based protection module, included within a hardware device, the hardware-based protection module configured to provide protection against malicious implementations within the hardware device, with the beacon circuit being configured to provide a beacon output when triggered. The method further includes determining based on the beacon output provided by the triggered beacon circuit whether the hardware device includes at least one malicious implementation.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 24, 2020
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Lakshminarasimhan Sethumadhavan, Adam Waksman
  • Patent number: 10498320
    Abstract: A transmitter includes: an output driver that outputs differential signals to differential signal lines; first termination resistors and a first switch which are provided in series between a first reference voltage input terminal to which a reference voltage is inputted and the differential signal lines; a pulse generator that outputs a common-mode pulse to the differential signal lines during a period during which a pulse output instruction signal is at a significant level; and a detector that outputs a detection result signal indicating a magnitude relationship between a voltage level of the common-mode pulse and a threshold, during a period during which the pulse output instruction signal is at a significant level, and outputs a detection result signal indicating that the voltage level of the common-mode pulse does not exceed the threshold, during a period during which the pulse output instruction signal is at a non-significant level.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: December 3, 2019
    Assignee: THINE ELECTRONICS, INC.
    Inventors: Yusaku Hirai, Akihiro Moto
  • Patent number: 10483973
    Abstract: A circuit includes: a first type of swing reduction circuit coupled between an input/output pad and a buffer circuit; and a second type of swing reduction circuit coupled between the input/output pad and the buffer circuit, wherein the first type of swing reduction circuit is configured to increase a voltage received by respective gates of a first subset of transistors of the buffer circuit when a voltage applied on the input/output pad is equal to a first supply voltage, and the second type of swing reduction circuit is configured to reduce a voltage received by respective gates of a second subset of transistors of the buffer circuit when the voltage applied on the input/output pad is equal to a second supply voltage.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hui Chen, Wan-Yen Lin, Tsung-Hsin Yu
  • Patent number: 10411009
    Abstract: A number of field effect transistor circuits include voltage controlled attenuators or voltage controlled processing circuits. Example circuits include modulators, lower distortion variable voltage controlled resistors, sine wave to triangle wave converters, and or servo controlled biasing circuits.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: September 10, 2019
    Inventor: Ronald Quan
  • Patent number: 10348302
    Abstract: A radiation-hardened electronic system is disclosed. The radiation-hardened electronic system includes a reconfigurable analog circuit block, a digital configuration logic circuit block, and a radiation-hardened isolation latch circuit connecting between the reconfigurable analog circuit block and the digital configuration logic circuit block. The reconfigurable analog circuit block includes multiple analog inputs and outputs. The digital configuration logic circuit block includes multiple digital inputs and outputs for controlling various functionalities of the reconfigurable analog circuit block via a set of configuration data. The radiation-hardened isolation latch circuit prevents the configuration data from entering the reconfigurable analog circuit block when the configuration data has been corrupted by a SEU.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: July 9, 2019
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Jason F. Ross, Jamie A. Bernard, John T. Matta
  • Patent number: 10326450
    Abstract: A method and circuit for implementing a level shifter for translating logic signals to output voltage analog levels, and a design structure on which the subject circuit resides are provided. The circuit includes a level shifter resistor divider string of a plurality of series connected resistors, the level shifter resistor divider string is connected between an analog voltage rail and an analog ground. A plurality of level shifter cascaded inverters are connected between respective resistors of the level shifter resistor divider string and an analog voltage rail and an analog ground. An output of the level shifter is programmed by the level shifter resistor divider string connected to the cascaded inverters.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andrew D. Davies, David M. Friend, Grant P. Kesselring, James D. Strom
  • Patent number: 10291222
    Abstract: A gate potential control device configured to control potential of a gate of a main switching element is provided herein. The gate potential control device includes: a turn-on switching element and a turn-off switching element. In a turn-off operation, a main voltage between main terminals of the main switching element increases from an on-voltage to a peak value of a surge voltage and then decreases to an off-voltage. The gate potential control device is configured to keep both of the turn-on switching element and the turn-off switching element turned off in a period which is at least a part of a specific period in the turn-off operation, the specific period being from a timing after a predetermined time lapse from a timing of rise-up of the main voltage from the on-voltage to a timing at which the main voltage reaches the peak value.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 14, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidetoshi Morishita, Hikaru Watanabe
  • Patent number: 10284183
    Abstract: The slew rate enhancement circuit includes: a first transistor located between a first power source and an eleventh node, the first transistor having a gate electrode coupled to the eleventh node, the first transistor being coupled as a current mirror to the first current source; a third current source having the other side coupled to a second power source lower than the first power source; a second transistor coupled between the first power source and the eleventh node; a third transistor coupled between the eleventh node and one side of the third current source; a fourth transistor coupled between the first power source and a twelfth node; and a fifth transistor coupled between the twelfth node and the one side of the third current source.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: May 7, 2019
    Assignee: Aconic Inc.
    Inventors: Minjae Lee, Eunseok Song
  • Patent number: 10236882
    Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: March 19, 2019
    Assignee: Rambus Inc.
    Inventor: Huy Nguyen
  • Patent number: 10236877
    Abstract: A half bridge GaN circuit is disclosed. The circuit includes a low side power switch, a high side power switch, and a high side power switch controller, configured to control the conductivity of the high sigh power switch based on the one or more input signals. The high side power switch controller includes a receiver input reset circuit configured to simultaneously receive first and second signals, wherein the first signal corresponds with the high side power switch being turned on, wherein the first signal corresponds with the high side power switch controller turning on the high side power switch, wherein the second signal corresponds with the high side power switch controller turning off the high side power switch, and wherein the receiver input reset circuit is further configured, in response to the first and second signals, to prevent the high side power switch from becoming non-conductive.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 19, 2019
    Assignee: NAVITAS SEMICONDUCTOR, INC.
    Inventors: Santosh Sharma, Daniel Marvin Kinzer, Ju Zhang
  • Patent number: 10216671
    Abstract: Systems and methods for operating a bus interface unit include queues for receiving and storing one or more words from one or more agents for transmission on to a data bus. From at least a subset of the one or more words, a next word which will cause the least switching power among the subset of the one or more words when transmitted on to the data bus is determined and the next word is selected for transmission on to the data bus, to reduce dynamic power consumption of the data bus. The next word may be selected as a word among the subset of the one or more words with a least Hamming distance from a current word scheduled for transmission on to the data bus.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: February 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Martyn Shirlen
  • Patent number: 10191526
    Abstract: A transmit driver is configured to operate under distinct supply voltage provided at output differential terminals. The transmit driver includes differential input transistors, first and second pairs of over-voltage protection differential transistors, and a current source coupled in series between the output terminals and a lower voltage rail. The transmit driver includes a first bias voltage generator configured to generate a first bias voltage based on the supply voltage across the output differential terminals. The first bias voltage is applied to the control terminals of the first pair of over-voltage protection transistors. The transmit driver includes a second bias generator for generating a second (substantially fixed) bias voltage for the control terminals of the second pair of over-voltage protection transistors. The transmit driver may be configured to operate based on a 3.3V supply voltage provided by an HDMI sink, or based on a 1.8V supply voltage provided by a bridge chip.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: January 29, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Madjid Hafizi, Chiu Keung Tang
  • Patent number: 10186942
    Abstract: A node that stores a charge is discharged in two phases, starting with a current controlled phase where a current mirror sink controls the current sunk from the node, and then moving to a second phase where a resistive discharge is provided. A pull down device such as a transistor switches from its saturation mode in the first phase to its linear mode in the second phase. a discharge circuit implementing this method provides optimized area and control for the discharge process as compared with approaches that rely solely on current mirroring or resistive discharging.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: January 22, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Emre Topcu, Turev Acar, Kemal Ozanoglu
  • Patent number: 10110221
    Abstract: A half bridge GaN circuit is disclosed. The circuit includes a low side power switch, a high side power switch, and a high side power switch controller, configured to control the conductivity of the high sigh power switch based on the one or more input signals. The high side power switch controller includes a receiver input reset circuit configured to simultaneously receive first and second signals, wherein the first signal corresponds with the high side power switch being turned on, wherein the first signal corresponds with the high side power switch controller turning on the high side power switch, wherein the second signal corresponds with the high side power switch controller turning off the high side power switch, and wherein the receiver input reset circuit is further configured, in response to the first and second signals, to prevent the high side power switch from becoming non-conductive.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: October 23, 2018
    Assignee: Navitas Semiconductor, Inc.
    Inventors: Santosh Sharma, Daniel Marvin Kinzer, Ju Zhang
  • Patent number: 10095889
    Abstract: An integrated circuit includes a control circuit, a one-time programmable circuit, and a security feature. The control circuit determines if the one-time programmable circuit is programmed in response to a request by a user of the integrated circuit to access the security feature. The control circuit generates a signal to indicate to the user of the integrated circuit that the security feature has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the security feature. The control circuit causes the one-time programmable circuit to be programmed in response to the request if the control circuit determines that the one-time programmable circuit has not been programmed.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 9, 2018
    Assignee: Altera Corporation
    Inventors: Bruce Pedersen, Ting Lu, Brian Wong, Alok Doshi, Yun Sum Wong
  • Patent number: 10068043
    Abstract: A technique validates results from a circuit simulation estimation program. The technique determines whether the estimated results satisfy Kirchhoff's current law (KCL), Kirchhoff's voltage laws (KVL), and power conservation for the original circuit. A reporting tool shows the validation results and may be customized by the user. The tool can show in the original circuitry where the estimated results may be inaccurate.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: September 4, 2018
    Assignee: Worldwide Pro Ltd.
    Inventor: William Wai Yan Ho
  • Patent number: 10069637
    Abstract: A transmitter (TX) circuit harvesting power from a power supply of a receiver (RX) circuit is disclosed herein. The TX circuit for data transmission over a differential channel comprises a driver circuit coupled with the differential channel across a first pair of resistors. One terminal of each resistor of the first pair coupled together at a common mode voltage node. The differential channel is series terminated at the RX circuit by a second pair of resistors to a power supply node of the RX circuit. The driver circuit includes a differential pair and a current source drawing current from the power supply node of the RX circuit. A pre-driver circuit coupled with the driver circuit provides an output of the pre-driver circuit as an input to the driver circuit. At least the pre-driver circuit is powered from the common mode voltage node of the driver circuit.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: September 4, 2018
    Assignee: Lattice Semiconductor Corporation
    Inventor: Dayasagar Reddy Gaade
  • Patent number: 10037739
    Abstract: A gate driving and modulating circuit, for reduced flicker on a display, includes a first discharge circuit and a plurality of interconnected gate drivers. The plurality of gate drivers is electrically coupled to ground through the first discharge circuit. Each of the plurality of gate drivers includes a second discharge circuit. The gate driving circuit performs a chamfering of a gate signal by being simultaneously discharged through the first discharge circuit and the second discharge circuit.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: July 31, 2018
    Assignee: Fitipower Integrated Technology, Inc.
    Inventors: Li-Shen Chang, Chen-Chi Yang
  • Patent number: 10027319
    Abstract: A circuit arrangement for controlling power transistors of a power converter includes a logic circuit configured to generate a pulse-width modulation (PWM) signal and a clock generator configured to generate a clock signal. A first and a second isolator are configured to galvanically isolate transmission of the PWM signal and the clock signal into a high-voltage portion of the power converter so as to produce a galvanically isolated PWM signal and a galvanically isolated clock signal. The first isolator for the PWM signal is configured transmit both DC voltage signals and AC voltage signals. A correction circuit is configured to correct jitter of the galvanically isolated PWM signal based on the galvanically isolated clock signal. The second isolator for the clock signal exhibits a jitter lower than that of the first isolator by a factor of at least two.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: July 17, 2018
    Assignee: ETEL S.A.
    Inventors: Mario Mauerer, Johann W. Kolar
  • Patent number: 10014682
    Abstract: A system includes a voltage surge protection circuit that receives a source voltage from a source. The voltage surge protection circuit includes a reference circuit to generate a reference voltage based on the source voltage when the source voltage exceeds a clamping voltage and a feedback control circuit to receive the reference voltage and clamp an output voltage to the clamping voltage when the voltage from the source exceeds the clamping voltage. A dynamic resistance of the feedback control circuit is substantially zero.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: July 3, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Dening Wang, Roland Son
  • Patent number: 9960769
    Abstract: One example discloses an apparatus for power management, including: a circuit having a first power-domain and a second power-domain; wherein the first and second power-domains include a set of operating parameter values; a circuit controller configured to incrementally sweep at least one of the operating parameter values of the first power-domain; a circuit profiler configured to derive a total power consumption profile of the circuit based on the circuit's response to the swept operating parameter value; wherein the circuit controller sets the operating parameter values for the first and second power-domains based on the total power consumption profile of the circuit.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: May 1, 2018
    Assignee: NXP B.V.
    Inventor: Ajay Kapoor
  • Patent number: 9948307
    Abstract: Techniques and mechanisms allow a Programmable Logic Device (PLD) to support a pseudo open drain (POD) input/output (I/O) standard used in interface protocols such as fourth generation double data rate (DDR4). An OR gate with inputs including data and an inverted output enable from a user's design may be inserted into programmable logic. The output of the OR gate may be coupled with an input of an I/O buffer.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: April 17, 2018
    Assignee: ALTERA CORPORATION
    Inventors: Navid Azizi, Gordon Raymond Chiu, Michael Howard Kipper
  • Patent number: 9948298
    Abstract: An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: April 17, 2018
    Assignee: SK hynix Inc.
    Inventor: Yo Han Jeong
  • Patent number: 9948292
    Abstract: A bidirectional integrated CMOS switch is provided which is capable of switching voltages beyond the range of the supply and ground potentials. The switch is composed of NMOS and PMOS transistors as the switch conductor path, a diode bridge, and control circuitry to turn the switch on and off by means of low voltage logic, regardless of the voltages on the switch terminals. The device and method of the invention enables the switching of high voltage loads operating at arbitrary or floating voltages relative to the low voltage power supply and ground, and provides on/off control of the switch with ordinary low voltage logic levels. The invention provides bidirectional switching without conducting through the parasitic body diodes of the CMOS devices.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: April 17, 2018
    Assignee: Telephonics Corporation
    Inventor: Harold Simmonds
  • Patent number: 9924246
    Abstract: An illustrative driver embodiment supplies an electrical transmit signal to an emitter module in response to an input bit stream. The illustrative driver embodiment includes: a voltage supply node which may be powered via a parasitic series inductance; a transmit signal buffer that drives the electrical transmit signal with current from the voltage supply node, the electrical transmit signal including transitions at bit intervals as dictated by the input bit stream; and an auxiliary signal buffer that supplies an auxiliary signal with current from the voltage supply node to an auxiliary module having an input impedance matched to an input impedance of the emitter module, the auxiliary signal having a transition at every bit interval where the electrical transmit signal lacks a transition.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: March 20, 2018
    Assignee: Credo Technology Group Limited
    Inventor: Lawrence (Chi Fung) Cheng
  • Patent number: 9916039
    Abstract: The present disclosure provides a shift register unit, its driving method, a gate driver circuit and a display device. The shift register unit includes a pull-up circuit configured to pull up a potential at the pull-up node PU in accordance with a starting signal from a starting signal input end, a pull-down circuit configured to pull down the potential at the pull-up node in accordance with a resetting signal from a resetting signal input end, a first capacitor configured to bootstrap the potential at the pull-up node at a pull-up stage, a first noise reduction circuit configured to perform noise reduction on a signal from the output end of the shift register unit at a pull-down stage and a compensation circuit configured to compensate for the potential at the pull-up node at a touch stage in accordance with a touch switch signal from a touch switch end.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: March 13, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Honggang Gu, Xiaohe Li, Xianjie Shao, Bo Liu, Jie Song
  • Patent number: 9893718
    Abstract: A transmission driver impedance calibration circuit and method. A circuit is disclosed that includes: a controller for controlling a set of switches; a comparator having an output that is coupled to the controller; and a first comparator input coupled to: a first selectable node coupled between a first p-type adjustable resistor segment (PSEG) and an external resistor; and a second selectable node coupled between a pair of internal resistors; and a second comparator input coupled to: a third selectable node coupled between a second PSEG and a tcoil resistor, the tcoil resistor being further coupled in series to a n-type adjustable resistor segment (NSEG); and a fourth selectable node coupled between the tcoil resistor and the NSEG.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: February 13, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Suhas Shivaram, Giri N. K. Rangan
  • Patent number: 9875994
    Abstract: A multi-chip package may include a plurality of semiconductor chips integrated in a single package and sharing one or more command pins. Each of the semiconductor chips may include: a command decoder suitable for decoding a command to generate a buffer enable signal, a mode enable signal, and a mode signal; a data input buffer suitable for buffering data to output internal data, in response to the buffer enable signal and a common test mode signal; a command controller suitable for receiving the mode enable signal to output a test mode enable signal by selectively blocking the mode enable signal based on the internal data and the common test mode signal; and a test controller suitable for generating the common test mode signal and a test mode signal, based on the test mode enable signal and the mode signal.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: January 23, 2018
    Assignee: SK Hynix Inc.
    Inventors: Chang-Ki Baek, Joon-Woo Choi
  • Patent number: 9852673
    Abstract: When an input signal maintains a first level throughout a predetermined judgment time, a noise removal circuit asserts an output signal. When the input signal transits from the second level to the first level, a first timer starts time measurement. When the input signal transits to the second level after time measurement by the first timer, a second timer measures time during which the input signal continues at the second level. A judgment unit is configured such that (i) it holds the measurement time obtained by the first timer when the input signal transits to the second level, (ii) when the measurement time obtained by the second timer and the measurement time of the first timer thus held satisfy a predetermined relation, the first timer is reset, and (iii) when the measurement time obtained by the first timer exceeds the judgment time, the output signal is asserted.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: December 26, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Tomoaki Kubo
  • Patent number: 9842066
    Abstract: An integrated circuit for bias stress condition removal comprising at least one input/output (IO) buffer driver circuit comprising at least one input signal is described. A primary buffer driver stage receives the at least one input signal and providing an output signal in a first time period; and a secondary buffer driver stage receives the at least one input signal and providing an output signal in a second time period. The primary buffer driver stage and the secondary buffer driver stage cooperate and an operational mode of the primary buffer driver stage and an operational mode of the secondary buffer driver stage is varied to produce a varying output signal.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: December 12, 2017
    Assignee: NXP USA, Inc.
    Inventors: Michael Priel, Dan Kuzmin, Sergey Sofer
  • Patent number: 9831855
    Abstract: Various implementations described herein are directed to circuit. The circuit may include a first input stage having first devices and a first path for slow slew input detection. The circuit may include a second input stage having second devices and a second path for fast slew input detection. The circuit may include a separation stage that couples the second input stage to the first input stage during a first mode of operation so as to reduce power consumption of the circuit during slow slew input detection.
    Type: Grant
    Filed: May 14, 2016
    Date of Patent: November 28, 2017
    Assignee: ARM Limited
    Inventors: Seshagiri Rao Bogi, Vijaya Kumar Vinukonda, Mikael Rien
  • Patent number: 9829906
    Abstract: A current mirror circuit that amplifies a reference current generated by a current source at a first magnification to supply a mirror current to a load circuit. The current mirror circuit includes a first transistor and a second transistor that share a power supply, and a drain potential mirror unit that amplifies the reference current at a second magnification to generate a first current, that amplifies a generated first current at a third magnification to generate a second current, and that supplies a predetermined potential determined based on the second current to a drain of the second transistor. The mirror current is supplied from the second transistor to the load circuit based on a potential of a gate of the first transistor determined based on the reference current.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: November 28, 2017
    Assignee: MegaChips Corporation
    Inventor: Ryota Yamahana
  • Patent number: 9780778
    Abstract: An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: October 3, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Mark L. Burgener, James S. Cable
  • Patent number: RE47312
    Abstract: An integrated circuit comprising an output driver including an output terminal, and a receiving circuit including a termination resistor connected between the output terminal and a ground. The output driver comprising a first NMOS transistor configured to pull up a voltage of the output terminal to a pull-up voltage in response to a pull-up signal, and a second NMOS transistor configured to pull down the output terminal to a ground voltage in response to a pull-down signal.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: March 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: David Moon, Yong Cheol Bae, Min Su Ahn, Young Jin Jeon