Abstract: A configuration memory for storing information which is in-system programmable. The programming of the configuration memory may be performed using JTAG (IEEE Standard 1149.1) instructions. Furthermore, the configuration of a programmable logic device using the configuration data in the configuration memory may be initiated with a JTAG instruction. Pull-up resistors are incorporated within the configuration memory package.

Abstract: A logic system is presented including multiple configurable logic blocks (CLBs) implementing a state machine having multiple states, each state being associated with one or more logic functions and one or more possible next states. Each CLB includes programmable logic circuitry, and is configurable to implement the logic functions required in any given state. A complex state machine may be implemented using only 1+s CLBs, where s is the maximum number of next states of any state, thereby using a minimum amount of configurable logic. The logic system also includes a memory unit, a control unit coupled to the memory unit and to each of the CLBs, and an interface unit coupled to the control unit and to each of the CLBs. The memory unit stores configuration data required to configure the CLBs and state transition information. The control unit generates and stores current state information. Following programming, a single "active" CLB implements the logic functions required in the current state.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract: A circuit and method for clocking for logic circuits use delay line techniques to time the clock signal. The inputs into a logic circuit are associated with a validity signal, which is delayed by a delay line for at least the propagation delay of the logic circuit. The delayed validity signal is used to latch an output signal produced by the logic circuit in response to the inputs.

Abstract: A byte accessible memory interface circuit using a reduced set of memory control signals. The present invention includes an interface circuit having a reduced set of memory control signals for performing word length reads and writes to an external memory module containing a plurality of integrated circuit (IC) memory chips. The interface circuit contains a respective multiplexer and a respective register circuit for each byte of the word length data. The multiplexers select a byte of data from either an on-chip data bus or from a bus carrying data read from the external memory module. To perform a full length word write, the data from the on-chip bus is loaded into the registers (via the multiplexers) and then written to the memory module. To perform a partial length word write, a pre-read operation is performed at the target address and a word length data is loaded into the registers. The new data is then received over the on-chip data bus and routed by the multiplexers into the byte locations to be changed.

Abstract: An asynchronous latch including a finite state machine (301) and a level-sensitive latch (304) in a feedback path of the finite state machine. The input to the level-sensitive latch (304) is a signal generated by decoding the state of the finite state machine (301). The level-sensitive latch output is fed back to the finite state machine inputs to control next-state transitions. An asynchronous input line couples an asynchronous signal to the level-sensitive latch so that the asynchronous signal is used as a latching signal.

Abstract: A sequential logic circuit having a series of data signal bistable elements is described. Each data signal bistable element is clocked by a corresponding qualified clock. The qualified clocks are generated by a series of AND gates that each have one input coupled to a global clock and the other input coupled to a valid signal such that the data signal bistable element is only clocked when valid data is present. A series of valid signal bistable elements, one for each data signal bistable element, are used to provide the valid signal to each AND gate. Since the data signal bistable elements are clocked only when valid data is present instead of continuously, the invention provides for a significant reduction in the power consumption of the sequential logic circuit.

Abstract: A synchronizing circuit processes a plurality (N) of input signals to generate a synchronizing circuit output signal, and provides the synchronizing circuit output signal synchronous to a system clock, wherein the N input signals are asynchronous to the system clock. Input stage circuitry samples the N asynchronous input signals. Combinatorial logic circuitry receives and combines the sampled asynchronous input signals to generate the synchronizing circuit output signal. First polarity edge flip flop circuitry to receive, as first polarity edge flip flop input, a first output of at least a first portion of the combinatorial logic circuitry, wherein the first polarity edge flip flop circuitry processes the first polarity edge flip flop input responsive to a first polarity edge of the system clock signal to provide a first polarity edge processed output signal.

Abstract: A gate array in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers. The function block includes a logic circuit with a first bit storage unit, which is selectively configurable to behave as combinational logic or to store a first bit, and a second bit storage unit, which is also selectively configurable to behave as combinational logic or to store a second bit. The matrix of function blocks in accordance with the invention is also useful to properly distribute clocks throughout the gate array.

Abstract: The invention concerns an asynchronous state machine with a programmable tSKEW which may be used to generate a half-empty and half-full flags in a synchronous FIFO buffer. The present invention may reduce the delay associated in producing the half-full or half-empty flags from a typical eight gate delays, to as little as no gate delays. The reduction may be accomplished by using a first state machine which can make an internal flag go low, or active, and a second state machine which can make the internal flag go high, or inactive. The functioning of the first and second state machines may be controlled by a blocking logic. The output of each of the state machines may be stored in a latch. The output of the latch may be presented to an input of the blocking logic, which may be used by the blocking logic to control the activity of the state machines.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract: A state machine that can be tested easily is disclosed. A state machine has a latch for storing data representing an intended state and a state control unit for producing data representing a subsequent state according to an intended state provided by the latch and a detection signal, and makes state transitions consecutively. The state machine comprises a state data input unit for inputting data representing an intended state directly from an external unit, a selector for selecting either data provided by the state control unit or data provided by the state data input unit so as to supply selected data as data representing a subsequent state to the latch, and a control data input unit for externally inputting control data for use in controlling the selection performed by the selector.

Abstract: Configurable logic circuit (10,110) and method may comprise a control circuit (12,112) and a logic circuit (14,114). The control circuit (12,112) may generate an intermediate clock function (36,136) in response to selection of one of a first (30,130) and a second (32,132) clock input based on a clock control input (34,134), generate a first control function (46,146) in response to selection of one of a first (40,140) and a second (42,142) control input based on the intermediate clock function (36,136) and generate a second control function (56,156) in response to selection of one of the second (42,142) and a third (52,152) control input based on the intermediate clock function (36,136). The logic circuit (14,114) may be coupled to the control circuit (12,112) and configured into one of a plurality of logic modes in response to a combination of the first (46,146) and second control functions (56,156).

Abstract: The present invention provides an asynchronous state machine with a programmable tSKEW that is used to generate an empty and full flag in a synchronous FIFO buffer. The present invention reduces the delay associated in producing the full or empty flags from a typical eight gate delays, to as little as no gate delays. The present invention accomplishes this by using a set state machine which can only make an internal flag go low, or active, and a reset state machine which can only make the internal flag go high, or inactive. The functioning of the set state machine and the reset state machine is controlled by a blocking logic. The output of each of the state machines is stored in a latch. The output of the latch is presented to an input of the blocking logic, which is used by the blocking logic to control the activity of the state machines.

Abstract: A semiconductor integrated circuit device incorporates logical arithmetic circuits (11) in order to set the internal circuits (7, 10) to a stable state. Each logical arithmetic circuit (11) is placed between each of input terminals (5, 9) that are not used during a boot operation mode, and each of internal circuits (7, 10).

Abstract: The present invention allows the behavior of a state machine to be readily modified by software after it has been fabricated in silicon. To perform these modifications, the present invention uses special patch registers, multiplexers, and comparators to bypass certain states within the sequence of states within the combinatorial logic of the state machine and/or add new state sequences. Each patch register stores a state to be patched, a next state, and outputs. The state to be patched is the state that will be modified, while the next state is the state the state machine transitions into from the state to be patched, and the outputs are the outputs generated and asserted by the state machine while within the next state. Many such patch registers can be used by the present invention to define many modifications. Using this patch mechanism, the present invention allows new states to be added and existing states to be removed from the sequence of states that the state machine cycles through.

Abstract: A structure in which blocks of random access memory, or RAM, are integrated with FPGA configurable logic blocks. Routing lines which access configurable logic blocks also access address, data, and control lines in the RAM blocks. Thus, the logic blocks of the FPGA can use these routing lines to access portions of RAM. In one embodiment, dedicated address and data lines access the RAM blocks of the present invention and are connectable to routing lines in the interconnect structure. These lines allow RAM blocks and arrays of RAM blocks to be configured long, wide, or in between, and allow logic blocks to conveniently access RAM blocks in a remote part of the chip. Access to the RAM blocks is efficient in any RAM configuration. Bidirectional buffers or pass devices segment the address and data lines at each RAM block so that a selectable number of RAM blocks can operate together as a RAM.

Abstract: A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

Abstract: A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

Abstract: The invention concerns an asynchronous state machine with a programmable tSKEW which may be used to generate a half-empty and half-full flags in a synchronous FIFO buffer. The present invention may reduce the delay associated in producing the half-full or half-empty flags from a typical eight gate delays, to as little as no gate delays. The reduction may be accomplished by using a first state machine which can make an internal flag go low, or active, and a second state machine which can make the internal flag go high, or inactive. The functioning of the first and second state machines may be controlled by a blocking logic. The output of each of the state machines may be stored in a latch. The output of the latch may be presented to an input of the blocking logic, which may be used by the blocking logic to control the activity of the state machines.

Abstract: A pipeline-able asynchronous logic circuit is provided that implements a subfunction of a logic function that is distributed into multiple sequential subfunctions. Each subsequent subfunction is applied to a result of an immediately preceding subfunction of the sequence. The asynchronous logic circuit has an output node and a differential logic circuit connected to the output node via a first path. The differential logic circuit applies a particular subfunction to an inputted signal to produce a result signal. The asynchronous logic circuit also has a sense amplifier that is connected to the output node via a second path which is distinct from the first path. The sense amplifier, in response to being enabled, amplifies the result signal produced by the differential logic circuit. The sense amplifier outputs the amplified result signal onto the output node.

Abstract: An apparatus and method of handling short setup and hold time input signals. The apparatus separates the processing of the data signals into an input flip-flop portion, a state machine portion, a combinatorial logic mapping portion and a rapid selecting circuit. The input flip-flops capture the signals allowing processing when the hold times are very small. The state machine portion generates a new current state from the input signals. The combinatorial logic mapping circuit generates a set of possible outcomes based on the result of the state machine and moderate setup time inputs. A rapid selecting circuit quickly chooses among the possible outcomes based on received short setup and hold time signals.

Abstract: A reprogrammable state machine which allows the state flow and control outputs to be reprogrammed without requiring modification of the state machine. The reprogrammable state machine uses a reprogrammable logic unit to generate the state transitions and output transitions for each state of the reprogrammable state machine. A memory control unit is used to program the state machine reprogrammable logic unit with default settings for the state transitions and output transitions for each state of the reprogrammable state machine. The memory control unit is also used to reprogram the state machine reprogrammable logic unit with modified settings for the state transitions and output transitions for each state of the reprogrammable state machine which needs to be modified.

Abstract: A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

Abstract: An LSI chip is mounted on an LSI board. Sub-buffer circuit areas where input buffers, output buffers or input/output buffers are to be formed are provided in signal lines extending from the pad to the internal circuit of the LSI chip. Each sub-buffer circuit area has a plurality of basic elements, such as transistors and resistors, connected in parallel to one another so that different combinations of those elements can be selected by switches. A latch controller is incorporated in the LSI chip, and it has latch circuits serially connected to form a shift register structure. This latch controller sends a program signal for determining the buffer circuit characteristic to the sub-buffer circuit areas. This program signal is generated when program data is input to the latch controller. The program data is given serially via input buffers from the pads on the LSI chip. The latch controller transfers the program data to the latch circuits one after another in synchronism with a clock signal.

Abstract: A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

Abstract: A state machine that can be tested easily is disclosed. A state machine has a latch for storing data representing an intended state and a state control unit for producing data representing a subsequent state according to an intended state provided by the latch and a detection signal, and makes state transitions consecutively. The state machine comprises a state data input unit for inputting data representing an intended state directly from an external unit, a selector for selecting either data provided by the state control unit or data provided by the state data input unit so as to supply selected data as data representing a subsequent state to the latch, and a control data input unit for externally inputting control data for use in controlling the selection performed by the selector.

Abstract: A method of eliminating signal contention during reconfiguration of a programmable logic device includes the steps of: arranging a plurality of memory cells in sets and selectively programming the memory cells one set at a time, either in a first direction or a second direction. A structure for providing that selective programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flops, whereas the control signal in a second logic state provides a second signal propagation direction through the flip-flops.

Abstract: An improved method and system for creating state machines in microcode. State machines are typically defined by a plurality having at least a combinations of current state, next state. Each one of the current states and next states are typically assigned unique values to distinguish them from other current states and next states, respectively. Upon an examination of the binary bit representations for the combinations, certain repetitive patterns become apparent between certain sections of the combinations. These recognized repetitive bit patterns are grouped and represented by linked lists and associated with one another to form the necessary relationship to define the represented combinations. Thus, saving memory and/or storage resources.

Abstract: Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell.

Abstract: A first pseudo random number generating circuit sequentially provides an output signal to a matching detecting circuit in response to a clock signal. A second pseudo random number generating circuit generates an initial value, and then, sequentially provides an output signal to a storage device in response to an output signal from the matching detecting circuit and the clock signal. Data with the output signal as an address is provided as an output signal from the storage device. When the matching detecting circuit detects matching between the output signals, the matching detecting circuit provides the output signals to the second pseudo random number generating circuit and an AND logic circuit. As described above, when the output signal of the matching detecting circuit is provided, the output signals from the storage device are provided as respective output control signals.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract: In a semiconductor device including a logic gate combination circuit and a plurality of scan registers or flip-flops, a scan path is provided to serially connect the flip-flops to each other. Scan clock signals are sequentially generated and transmitted to the scan registers. A delay time among the scan clock signals is approximately smaller than an operation time of each of the scan registers.

Abstract: A method of identifying potential clock qualifiers in netlist description of an integrated circuit, the netlist comprising logic elements. The method comprises the steps of initializing every net of the netlist to a speed of zero, identifying all potential clock nets so that all signals with a path to a clock source has a speed of one, computing the maximum speed of each output net of each of the logic elements in the netlist, and marking as a potential clock qualifier any net of the netlist that is input to the logic elements in the netlist that is slower than the maximum speed of any net that is input to the logic elements.

Abstract: A bus interface system and method for communication between different computer components having buses with different speeds, data widths, or protocols. A first state machine communicates with the first bus and a second state machine communicates with the second bus. Each of the buses communicates with a data storage device. The first and second state machines are in selective communication using an asynchronous handshaking protocol, whereby data is transferred between said first and second buses. The handshaking protocol comprises an asynchronous request signal from the first bus requesting a data transfer and an asynchronous reply signal from the second bus indicating that data has been sent or is available.

Abstract: A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering and output driver sizing as a function of signal propagation distance.

Abstract: The present invention relates to a configurable IC device pin. The IC device pin may be a device clock input pin or a digital I/O pin in one embodiment of the present invention, or a reset pin or a digital I/O pin in another embodiment of the present invention. Both embodiments of the present invention use a memory device to store information to configure the IC device pin. Input/Output logic is also used in both embodiments in order to transfer data to and from the IC device pin when the IC device pin is configured as a digital I/O pin.

Abstract: A clock switching circuit responsive to at least one clock select signal switches to a selected one of a plurality of clock signals while minimizing transients generated during the switching. The circuit includes at least one flip-flop receiving a corresponding one of the at least one clock select signal; a plurality of flip-flops individually receiving an output of a corresponding one of the at least one flip-flop, and an inverted version of a corresponding one of the clock signals; a plurality of AND gates individually receiving the output of a corresponding one of the at least one flip-flop, the output of a corresponding one of the plurality of flip-flops, and a corresponding one of the plurality of clock signals; and an OR gate receiving the outputs of the AND gates so that the selected one of the plurality of clock signals is provided at an output of the OR gate, and fed back to an inverted clock input of the at least one flip-flop.

Abstract: An integrated circuit with programmable transistors is programmed via a state machine on the integrated circuit. For example, the integrated circuit may be a programmable logic device, and the state machine may be a JTAG state machine. Each integrated circuit may have on it a register containing data indicating how long a particular programming operation should continue in order to be successful for that circuit. External programming control apparatus first reads that data and then at least partly bases the timing of programming instructions applied to the integrated circuit on that data. The integrated circuit may have an on-board programming voltage generating circuit which is turned on only by appropriate instructions from the external programming control apparatus. The external programming control apparatus controls the sequence and timing of all programming operations via the state machine port of the integrated circuit.

Abstract: To obtain a semiconductor integrated circuit reduced in hardware size, by avoiding duplication of a common constitution. A logic block (100) comprises logic means (A), logic means (B), and logic means (C), and the output of a pipeline register (11) is connected to the logic means (A) through a signal line (a), and the logic means (A) and logic means (B) are connected through a signal line (b). The logic means (A) is also connected to the logic means (C) through a signal line (c), and the logic means (C) is connected to the input of a pipeline register (21) through a signal line (d). When performing the same logic action in the first half period and second half period of a clock signal, it is not necessary to install two identical logic means, so that the size of the hardware may be reduced as compared with the constitution of installing two identical logic means.

Abstract: A latch may be formed as a two-part structure, one part for data input and one part for feeding back the data to form the latch. A clock signal controls whether data from a data input terminal will be forwarded to the output or whether the output signal will be provided as input and forwarded, thus forming the latch. A problem called the static ones hazard, namely registering a logical 0 when data input is logical 1, can occur with a latch of this logic structure when the circuit is entering the latch mode. In accordance with the invention, this static ones hazard is avoided by controlling trip points in the gates of the cell and input buffers of the cell so that the cell implements a make-before-break transition.

Abstract: A method and apparatus for generating an asynchronously clocked signal in a synchronously clocked programmable device is described. A programmable logic device having synchronously clocked or product term clocked registers receives an input signal and an event signal. The input signal and the event signal can be any externally or internally generated signals. The event signal signifies the occurrence of a particular event by transitioning from one signal state to another. The input signal is asynchronously clocked through the synchronously clocked PLD without utilizing the synchronously clocked or product term clocked registers. The input signal is asynchronously clocked in response to an edge transition of the event signal. The edge transition of the event signal being either a failing edge or a rising edge.

Abstract: A method of time multiplexing a programmable logic device (PLD) includes inputting a design for the PLD and dividing an evaluation of the logic of the design into a plurality of micro cycles. The method further includes identifying the logic not within a critical path of the design and rescheduling the identified logic for evaluation in other micro cycles. Alternatively, if the PLD includes a plurality of combinational logic elements, the method further includes scheduling a combinational logic element in a micro cycle no earlier than all the combinational logic elements that generate the input signals to said combinational logic element.

Abstract: An LED driver pin which can be used for programming a memory element in a first mode, and can be used for driving the LED in a second mode is provided. The invention includes the pin and the LED driver connected to the pin, and additionally provides an input buffer for receiving the programmable input signal. The programmable memory element is connected to the input buffer, and a control circuit is provided for enabling the input of a voltage on the pin to the programmable memory element during the first mode, and enabling the LED driver to function during a second mode.

Abstract: The invention describes an asynchronous state machine with a programmable tSKEW that is used to generate an empty and full flag in a synchronous FIFO buffer. The present invention reduces the delay associated in producing the full or empty flags from a typical eight gate delays, to as little as no gate delays. The present invention accomplishes this by using a set state machine which can only make an internal flag go low, or active, and a reset state machine which can only make the internal flag go high, or inactive. The functioning of the set state machine and the reset state machine is controlled by a blocking logic. The output of each of the state machines is stored in a latch. The output of the latch is presented to an input of the blocking logic, which is used by the blocking logic to control the activity of the state machines.

Abstract: A bistable logic network of the sequential type, responsive to the edges of input signals, comprising first and second input SR flip-flops which are connected to an output SR flip-flop through two transfer and block logic gates.Each of said logic gates has two input terminals connected to the output terminal and to one input terminal of an input flip-flop.The output terminals of the output flip-flop are feedback connected to the other input terminals of the two input flip-flops.

Abstract: An iterative logic circuit for iteratively performing a logic function includes a two-input logic gate and a D-type flip-flop. The flip-flop receives and time-delays the output signal from the logic gate to provide a feedback signal as one of the input signals to the logic gate. By sequentially processing the feedback signal together with a serial input data signal, the logic gate iteratively performs an associative logic function (e.g. EXCLUSIVE-OR) upon the serial input data signal, thereby performing a parallel logic function by executing a serial logic operation.

Abstract: A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.

Abstract: A method of state splitting in a state machine includes determining a number N of logic levels, i.e. CLB levels, for each state in a state machine. Number N is equal to N.sub.i-1 +log.sub.k f.sub.i wherein "k" is the number of input lines to a CLB, "i" is a particular node in a particular hierarchial level in the Boolean logic, and "f" is the number of fanin transitions to the particular node. An average number N(AV) as well as a maximum number N(MAX) of CLBs to implement the states in the state machine are also determined. Then, predetermined exit criteria are checked. One exit criterion includes determining that the maximum number N(MAX) is not associated with a state register, but is instead associated with an output, for example. Another exit criterion includes providing a ratio by dividing the maximum number N(MAX) by the average number N(AV). If the ratio is less than or equal to a split-factor, then this exit criterion is met. In one embodiment, the split factor is between 1.5 and 2.0.

Abstract: The device comprises a first chain of scanning cells located at the stimulation input of each respective functional block of the integrated circuit and a second chain of scanning cells located at the assessment output of each respective functional block of the integrated circuit. Each cell comprises a master part, a slave part and switching circuit to alternately enable the master and slave parts under the control of respective master clock and slave clock signals coincident with opposite phases of a scanning clock signal having a substantially square wave. With each pair of chains of scanning cells there are associated clock generators to locally obtain the master and slave clocks from the scanning clock.