Abstract: A 6-input LUT architecture includes 64 memory cells, which store 64 corresponding data values. A set of 64 transmission gates is configured to receive the 64 four data values. A first input signal is applied to the set of 64 transmission gates, thereby routing 32 of the 64 data values. A set of 32 transmission gates is coupled to receive the 32 data values routed by the set of 64 transmission gates. A second input signal is applied to the set of 32 transmission gates, thereby routing 16 of the 32 data values. A 16:1 multiplexer receives the sixteen data values routed by the set of 32 transmission gates. Third, fourth, fifth and sixth input signals are applied to the 16:1 multiplexer, thereby routing one of the 16 data values as the output of the LUT.

Abstract: In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to adaptively idle until the bus settles, making it amenable for a wide variety of bus sizes and topologies. In this way, oscillation of the bus is avoided without slowing the speed of the state machine clock.

Abstract: A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is provided. The system may include a single set of storage elements connected to the inputs of multiple decoders, and the storage elements may be concurrently accessed by the decoders to provide simultaneous multiple outputs thereto.

Abstract: A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus has changed logic state. If a bit has changed state, the comparison logic asserts an enable signal which causes the clock logic to clock the register. Accordingly, data from the bus is not clocked through the register unless the data has actually changed state and the comparison logic itself determines whether different data is present on the bus.

Abstract: A programmable logic device (PLD), such as a field programmable gate array (FPGA) has a logic core surrounded on one or more sides by an input/output (I/O) interface having one or more programmable I/O buffers (PIBs). At least one PIB can be programmed to perform two or more of (a) a pass-through data input mode, (b) an input register mode; (c) a double data rate (DDR) input mode, (d) one or more demux input modes, (e) one or more DDR demux input modes. In addition or alternatively, at least one PIB can be programmed to perform two or more of (a) a pass-through data output mode, (b) an output register mode, (c) a DDR output mode, (d) one or more mux output modes, and (e) one or more DDR mux output modes. As such, devices of the present invention are flexible enough to support both low-rate and high-rate interface applications, while efficiently using device resources.

Abstract: A programmable logic device (PLD) includes a compare-select circuitry. The compare-select circuitry includes logic elements 1 through N. Each logic element comprises a compare circuitry and a selector circuitry. The compare circuitry compares two inputs of the logic element and generates a compare output signal of the logic element. The selector circuitry provides one of the two inputs of the logic element as an output in response to a selection signal. The selection signal for all logic elements (i.e., logic elements 1 through N) constitutes the compare output signal of the Nth logic element. A median-calculation apparatus is also disclosed. The median-filter apparatus includes at least one insertion-sort circuitry. The at least one insertion-sort circuitry performs insertion-sorting of a set of input numbers corresponding to that insertion-sort circuitry to generate a corresponding set of sorted numbers. Each of the sorted set of numbers includes a median value of the corresponding set of input numbers.

Abstract: Programmable logic device interconnection resources include bus wires. A bus wire provides a programmable signal path across the programmable logic device from several logic device outputs to several other logic device inputs. Serializing circuitry multiplexes multiple device output signals and drives time-multiplexed data signals on the bus wires. Bus registers placed at the ends of bus wires register or buffer the data signals transmitted over the bus wires. The registered signals are passed on to deserializing circuitry for demultiplexing data signals to provide parallel device input signals. The bus registers, and the serializing/deserializing circuitry are clocked at a rate faster than the device system clock to schedule the use of the bus wires for transmission of multiple device input/output signals over the bus wires within a system clock cycle.

Abstract: During a reset condition or prior to system initialization of an FPGA-based system (100), a FPGA (102) can be pre-configured by loading a value from a memory cell (108) into at least one flip-flop (312) of the FPGA, which represents a configuration register for an FPGA memory controller (106). The FPGA memory controller can be configured using the value loaded in the flip-flop. The value loaded into the flip-flop from the memory cell can be a default value previously stored in the memory cell.

Abstract: A non-volatile product term cell is provided having a first floating gate located over a first p-channel transistor and a first n-channel transistor, and a second floating gate located over a second p-channel transistor and a second n-channel transistor. A control gate is located over the first and second floating gates. A first tunnel oxide capacitor is coupled to the first floating gate and a second tunnel oxide capacitor is coupled to the second floating gate. A first transistor pair is coupled between the first p-channel transistor and the second n-channel transistor, and a second transistor pair is coupled between the second p-channel transistor and the first n-channel transistor. The first and second floating gates are programmed and/or erased. Complementary input signals are applied to the first and second transistor pairs. An output signal is provided in response to the programmed/erased states of the first and second floating gates.

Abstract: The configurable electronic device comprises a configurable electronic device includes at least one configurable basic assembly. The basic assembly includes a programmable circuit having a plurality of programmable elements, and a first configurable interconnection network for mutually connecting the programmable circuits. A plurality of configurable arithmetic cells are mutually connected by a second configurable interconnection network. A third configurable interconnection network links the programmable circuit and the configurable arithmetic cells. A control bus is between the programmable circuit and the configurable arithmetic cells, and also extends within the configurable arithmetic cells.

Abstract: A programmable logic device configurable to implement a finite state machine includes a hardwired microsequencer for executing microinstructions to sequence the finite state machine. The hardwired microsequencer includes a sequence memory for storing the microinstructions and a program counter.

Abstract: A teacher-pupil flip-flop with reduced register delay including a gate circuit, a stack circuit, a keeper circuit, a teacher output circuit, a latch circuit and a pupil output circuit. The gate circuit switches after a setup delay in response to transitions of a clock signal. The stack circuit, coupled to the gate circuit output and to an input, switches an intermediate node pair to a preliminary state when the clock signal is low, and to a data state indicative of the input after the setup delay when the clock signal goes high. The keeper circuit maintains the data state and the teacher output circuit drives the output based on the data state while the clock is high. The latch circuit stores the data state and the pupil output circuit drives the output with valid data from the latch circuit after the clock signal goes low.

Abstract: A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is re-configuring function region with the next functional block and re-configuring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

Abstract: A programmable logic device (PLD), such as a field programmable gate array (FPGA) has a logic core surrounded on one or more sides by an input/output (I/O) interface having one or more programmable I/O buffers (PIBs). At least one PIB can be programmed to perform two or more of (a) a pass-through data input mode, (b) an input register mode; (c) a double data rate (DDR) input mode, (d) one or more demux input modes, (e) one or more DDR demux input modes. In addition or alternatively, at least one PIB can be programmed to perform two or more of (a) a pass-through data output mode, (b) an output register mode, (c) a DDR output mode, (d) one or more mux output modes, and (e) one or more DDR mux output modes. As such, devices of the present invention are flexible enough to support both low-rate and high-rate interface applications, while efficiently using device resources.

Abstract: A method and apparatus to synchronize signals between different clock domains are described.

Abstract: The invention CONCERNS a device for reconfiguring an assembly of N basic electronic modules associated with k redundant modules comprising: N multiplexers each having a first terminal (di) capable of being connected to k+1 second terminals connected to the k+1 input/output terminals of a sequenced group of modules consisting of a basic module (Ui) and k other modules; N+k triggers (Fi) indicating a good or faulty condition of one of the N+k modules; and logic means associated with each multiplexer of rank j, where j is an integer ranging between 0 and N, to determine the number of triggers of rank 0 to j indicating a faulty condition, to determine the number of modules of the sequenced group associated with the module of rank j, to be counted to find a number of good modules equal to the first number, and to convert the first terminal of the multiplexer to its second terminal of rank equal to the second number.

Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Abstract: A system and method for creating a built-in self-testing (BIST) state machine to test random access memories (RAMs) are disclosed. The BIST state machine can be simplified to a simple four-state state machine while accommodating a large group of test suites by programming each state to have the capability of performing one of four necessary operations. These operations include a write operation, a read operation, a read/write operation and a null operation. Further bits and signals can be added to the state machine to enable an even larger array of test suites to be performed.

Abstract: A programmable logic device is programmed to implement a finite state machine that may sequence through a plurality of states in a single clock cycle of the programmable logic device. The programmable logic device includes a plurality of programmable blocks programmed to instantiate memories. Each memory is programmed to determine a next state of the finite state machine based upon a current state of the finite state machine and current input conditions for the finite state machine.

Abstract: A programmable flip-flop is presented for outputting data. The flip-flop includes a first latch for latching a first input value in response to a rising edge of a clock signal. A second latch latches a second input value in response to a falling edge of the clock signal. A selection function controlled by the clock signal selectively supplies outputs of the first and second latches to the input of a third latch. A control circuit for the third latch accepts as inputs the clock signal and an inverted clock signal. The programmable flip-flop is configurable to operate in at least first and second modes selectable by the selection function and third latch control circuit, such that in the first mode the output of the third latch is the first and second input values multiplexed together and output at twice the clock rate.

Abstract: A semiconductor integrated circuit having a system bus divided into stages and configured to transfer signals, stage elements configured to connect the stages in series and operate in a divided mode transferring signals from a stage on an input side to a stage on an output side in synchronization with a clock signal and in a through mode that always passes signals from the stage on the input side to the stage on the output side, and a plurality of function modules connected to the different stages.

Abstract: In the present invention, an input terminal of a flip-flop circuit in master slave form which is formed by connecting two inverters in a loop shape is connected to a first terminal via a first switch circuit, an output terminal of the flip-flop circuit is connected to a second terminal via a second switch circuit, a third switch circuit is provided between the path from the first switch circuit to the input terminal and the second terminal, a fourth switch circuit is provided between the path from the output terminal to the second switch circuit and the first terminal, and through turning ON the first and second switch circuits and turning OFF the third and fourth switch circuits the first terminal is rendered operable as an input terminal and the second terminal is rendered operable as an output terminal, and through turning OFF the first and second switch circuits and turning ON the third and fourth switch circuits the second terminal is rendered operable as an input terminal and the first terminal is rende

Abstract: The present invention relates to a finite field multiplier used for implementing an encrypting algorithm circuit, thereby minimizing power consumption and circuit area in implementing the finite field multiplier with a LFSR (Linear Feedback Shift Register) structure. The Finite field multiplier of the present invention is an operator performing a modular operation on the multiplication result of two data represented on a polynomial basis in a Galois Field into an irreducible polynomial. The LFSR structure is a serial finite field multiplication structure, and has a merit over an array structure and a hybrid structure in application to systems that are limited in size and power due to its simplicity of circuits and also its capability of being implemented in a small size.

Abstract: A semiconductor device includes a state code register that stores a state code representing a present internal state. A state transition logic unit is configured to determine a state code for a next internal state to be transited in accordance with a predetermined logic, based on a state code provided from the state code register and an input command instructing transition to a required state, and to set the determined state code into the state code register with synchronizing an internal clock. An expected value register is configured to hold an internal state to be detected, as an expected value code and a comparing unit compares the state code set in the state code register by the state transition logic unit to the expected value code in the expected value register and supplying an equal state signal when they coincide.

Abstract: A register-file bit read apparatus includes a decoder operable to receive a number of address-bit signals and responsively assert a select signal on one of M select lines. Each select line corresponds to a respective one of M register-file cells. The apparatus also includes a multiplexer having Q output nodes and M selectors. Each selector is coupled to one of the select lines and that select line's corresponding register-file cell. The selectors are in Q groups, each coupled to a respective one of the multiplexer's output nodes. The apparatus also includes an output logic gate having Q inputs, coupled to respective ones of the multiplexer output nodes. The multiplexer includes Q pull-ups, each of which is coupled to a respective one of the multiplexer output nodes and is operable to drive its multiplexer output node responsive to one of the address-bit signals.

Abstract: A bidirectional signal transmission circuit includes: a buffer element for reducing the impedance of a signal line; a signal line disposed between input terminals in both ends of the bidirectional signal transmission circuit; and a signal line disposed between output terminals in these ends. The signal lines are parallel to each other. A signal supplied from the exterior of the bidirectional signal transmission circuit is sequentially transmitted from one end to the other end of this circuit and is then output as an output signal from the other end in order to confirm the sequential transmission at the exterior. The transmitting direction is changeable between these ends in response to a switching signal supplied from the exterior. The buffer element for reducing the impedance of the signal line is disposed in at least one end of the signal line arranged between the output terminals.

Abstract: A method and respective hardware logic circuit for implementing partially programmable Finite State Machines in the hardware of digital systems which use finite state machines to implement the control logic of the hardware design. In order to provide a partly reprogrammable Finite State Machine (FSM), which can be reprogrammed in a limited way such that no costly new physical re-build of the chip including said FSM is required, a hardwired FSM includes circuit means that allow that each hardwired product term to be disabled, and further includes means that add programmable product terms which allow adding new behavior to the state machine. Scan-Only SRLs are preferably used to program the required behavior of those programmable product terms.

Abstract: At least one column of a latch array includes a tri-state buffer in the upper portion of the column that receives the output of the uppermost group of latches of the column as its input, and which is enabled by a dump signal when a latch in the upper portion is addressed. When the dump signal that triggers the tri-state buffer is active, whatever is at the input of the tri-state buffer is driven by the buffer to the bottom of the latch array column, thereby providing the driven signal with sufficient strength to obviate transition timing and signal integrity problems. When the dump signal that triggers the tri-state buffer is not asserted, the tri-state buffer output exhibits high impedance, which isolates the lower portion of the latch array column from the upper portion of the latch array column, thereby preventing the capacitance associated with the line connecting the tri-state buffer to the output of the uppermost latch from affecting the driving ability of the latches in the lower portion of the column.

Abstract: An apparatus comprises a buffer comprising a plurality of entries, an insert pointer, a delete pointer, a plurality of first control circuits coupled to the buffer, and a second control circuit coupled to the buffer. The entries are logically divided into a plurality of groups. Each of the first control circuits corresponds to a respective group and selects an entry from the respective group for potential reading from the buffer. Furthermore, each of the first control circuits, in the event that the delete pointer indicates a first entry in the respective group and the insert pointer wraps around the buffer and indicates a second entry in the respective group, selects the first entry if the first entry is eligible for selection. The second control circuit selects a first group, and the entry selected from the first group by the first control circuits is the entry read from the buffer.

Abstract: A clock control circuit routes one of a plurality of clock signals to a clock output node, and employs an asynchronous state machine to switch between clock signals without introducing glitches. To switch from a first to a second clock, the control circuit samples the logic level of the first clock signal to obtain a sampled logic level. The control circuit then provides a constant version of the sampled logic level on the clock output terminal until the second clock signal transitions to the sampled logic level, at which point the control circuit routes the second clock signal to the clock output node.

Abstract: A method and apparatus for converting a full-rate digital clock circuit to a fractional-rate clock circuit. The combinatorial and sequential functions of the full rate design are duplicated, with a first combinatorial function responsive to even input logic vectors and a second combinatorial function responsive to odd input logic vectors. Output vectors from the first and the second combinatorial function are provided as input vectors to the respective first and second sequential function, which operate at a fractional clock rate and provide the output block vectors.

Abstract: Described are circuits and methods for aligning data and clock signals. Circuits in accordance with some embodiments separate incoming data into three differently timed data signals: an early signal, an intermediate signal, and a late signal. The timing of the three data signals can be collectively moved with respect to the clock signal. In addition, the temporal spacing between the three signals can be adjusted so that the early and late signals define a window encompassing the intermediate signal. The three signals are aligned with respect to the clock edge to center the intermediate data signal on the clock edge. The early and late signals can be monitored to identify changes in the relative timing of the clock and data signals. Some embodiments automatically alter the timing of the data and/or clock signals to keep the intermediate data signal centered on the clock edge.

Abstract: A system for remotely/automatedly testing an ASIC and particularly to testing a user-designed circuit is disclosed. In general, a system in accordance with the invention includes a plurality of cells, where the cells are couplable to form a user-designed circuit, e.g., by customizing routing. Within the ASIC and prior to any knowledge of the user-designed circuit, the ASIC includes circuitry to enable internal remote/automated testing of the user-designed circuit to be later formed. The circuitry controls the input and mode of operation of the cells and the sequencing of multiple synchronous or asynchronous clock domain inputs thereby providing testing of the user-designed circuit at speed for stuck-at-faults and delay faults.

Abstract: A circuit to divide down the frequency of a clock signal, where embodiment circuits comprise a set-reset flip-flop feeding its output to a shift register, and combinational logic to provide feedback from the shift register to the set input port, reset input port, or both set and reset input ports of the set-reset flip-flop. The set-reset flip-flop and shift register are clocked by the clock signal. The output signal of the circuit may be taken at any output port of the shift register or the set-reset flip-flop. In one embodiment, the state of the shift register is represented by the set of Boolean values Q<i>, i=1, 2, . . . , N?1, and the combinational logic provides to the set input port of the set-reset flip-flop the Boolean value {Q#<M?1><Q#<M?2>. . .

Abstract: Systems and methods are disclosed to provide clock and data synchronization for input/output interfaces of a programmable logic device. In accordance with one embodiment, a phase-locked loop or a delay-locked loop is employed to synchronize signals for input/output circuitry. In accordance with another embodiment, a clock divider along with an edge clock distribution scheme is employed to distribute clock and reset signals for input/output circuitry.

Abstract: A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed 110 modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.

Abstract: A scannable storage circuit is provided that has a separate a scan output buffer for driving the scan output. The scan output buffer is coupled to the storage element in a parallel manner with the data output buffer so that normal data propagation is not delayed. The scan output buffer is gated by a scan enable input so that the scan output is quiescent when the storage circuit is not in scan mode. The selectively enabled scan output buffer is embodied with only four transistors.

Abstract: An apparatus and method for a pseudo-dynamic latch are disclosed. A deracer circuit includes a first logic gate configured to receive a data signal from a domino logic circuit and to invert the data signal. A second logic gate is configured to receive the inverted data signal and an inverted select signal and to generate a select signal. Thus, the deracer circuit is configured to prevent the select signal from being high when a precharge edge of a data signal arrives.

Abstract: A supply voltage is needed in conventional electronic circuits used for processing signals, such as counting pulses. The supply voltage supplies the logic circuit components. Especially apparatuses which have to be operated over a longer period of time or/and in remote sites of use and are dependent upon a supply voltage are impaired with the dependency-related disadvantages, such as the necessity of expensive EEPROMs or significantly increased maintenance expenditure.

Abstract: A latch is provided which includes: a transparent catch latch having a data input, a data output and a control node arranged to receive a catch signal; a transparent pass latch having a data input connected to the data output of the transparent catch latch at an internal storage node, a data output, and a control node arranged to receive a pass signal; and logic circuitry having an enable input and a clock input connected to provide a gated clock signal to provide one of said catch signal and said pass signal. In another aspect an integrated circuit is provided with input and output guard flops, each including a transparent catch latch and a transparent pass latch, and further including a logic gate with an enable input and a clock input connected to provide a gated clock signal to at least one of the transparent pass latch of the input guard-flop and transparent catch latch of the output guard flop.

Abstract: An integrated circuit includes non-volatile and volatile memory, with the volatile memory controlling the integrated circuit's functionality. Various techniques are disclosed for programming the different types of memory through one or more data ports to provide in-system programmability and dynamic reconfigurability. External configuration devices are not required if the data from the non-volatile memory is transferred directly to the volatile memory.

Abstract: A method and respective hardware logic circuit for implementing partially programmable Finite State Machines in the hardware of digital systems which use finite state machines to implement the control logic of the hardware design. In order to provide a partly reprogrammable Finite State Machine (FSM), which can be reprogrammed in a limited way such that no costly new physical re-build of the chip including said FSM is required, a hardwired FSM includes circuit means that allow that each hardwired product term to be disabled, and further includes means that add programmable product terms which allow adding new behavior to the state machine. Scan-Only SRLs are preferably used to program the required behavior of those programmable product terms.

Abstract: A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus has changed logic state. If a bit has changed state, the comparison logic asserts an enable signal which causes the clock logic to clock the register. Accordingly, data from the bus is not clocked through the register unless the data has actually changed state and the comparison logic itself determines whether different data is present on the bus.

Abstract: According to one form, a latch has an output node and sublatches. The sublatches each have an output node coupled to input circuitry and feedback circuitry coupled to the sublatch's output node for reinforcing an output signal of the sublatch. The sublatches are operable to receive a data signal at their respective input circuitry and to generate output signals on their respective output nodes. At least one sublatch output node is coupled to the latch output node. The output nodes of other ones of the sublatches are connected in the latch such that if any one of the sublatches is subjected to a radiation induced erroneous change of state the output signals of the other sublatches reduce an effect of the change on the latch output signal. The latch also includes a number of scanning-mode control switches coupled to ones of the sublatches for scanning data in or out.

Abstract: A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus has changed logic state. If a bit has changed state, the comparison logic asserts an enable signal which causes the clock logic to clock the register. Accordingly, data from the bus is not clocked through the register unless the data has actually changed state and the comparison logic itself determines whether different data is present on the bus.

Abstract: A semiconductor integrated circuit device which shortens the time required for testing a divided logic circuit to reduce test cost and a fault-detecting method therefor. The logic circuit is divided into N logic blocks using N+1 scan paths comprises of scan flip-flops each having selectors for selectively picking up the output signals of storage elements which are fed back to the storage elements. A common scan operation may then be carried out on these logic blocks (Logic 1-to Logic N), and a testing operation may be continuously carried out on the logic blocks. The present invention preferably eliminates the overlaps in conventional scan operations, resulting in a shorter test time.

Abstract: A programmable logic device (PLD) is disclosed that includes a state machine integrated into a block memory. The state machine includes state machine logic and memory elements from the block memory. The state machine logic and memory elements together may be used as an instruction unit of a processor. In such a case, the instruction unit is coupled to a processor execution unit to form a high-performance, embedded processor within a PLD.

Abstract: A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.

Abstract: A scan flip-flop circuit achieving higher operation speed, lower power consumption, and a simplified selector section, an array of the scan flip-flop circuits, and an integrated circuit device having therein the array are provided. In a scan flip-flop circuit, an output terminal is provided in addition to an output terminal. One of the output terminals is used for a logic circuit and the other output terminal is used for a scan flip-flop circuit of the next stage. At the output terminal for the scan flip-flop circuit 1 of the next stage, an output is fixed in a normal operation, thereby achieving higher operation speed in the normal operation and lower power consumption. A selector section can employ a relatively simple OR-AND-INVERTER structure.

Abstract: Method for multithread processing of a packet is described. A packet recognition thread is initiated responsive to receiving the packet to a port triggering a media access control (“MAC”) recognition thread. A network protocol recognition thread is activated responsive to the MAC recognition thread for an initiating an address lookup thread and a MAC write thread. The MAC recognition thread, the network protocol thread, the address lookup thread and the MAC write thread all may complete their respective executions prior to completion of the packet recognition thread, thereby reducing latency in packet handling.