Abstract: Described are systems for producing differential logic signals and circuits for biasing the voltages of the differential logic signals. These systems can be adapted for use with different loads by programming one or more programmable elements. One embodiment includes a series of driver stages, the outputs of which are connected to one another. The driver stages turn on successively to provide increasingly powerful differential amplification. This progressive increase in amplification produces a corresponding progressive decrease in output resistance, which reduces the noise associated with signal reflection. The systems can be incorporated into programmable IOBs to enable PLDs to provide differential output signals.

Abstract: A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including a CMOS multiplexer controlled by a fuse or anti-fuse, an NMOS or PMOS pass gate controlled by a fuse or anti-fuse, or even a fusible link which is severed to effect isolation. Additionally, a circuit is provided that switchably isolates one of two contact pads from a logic circuit.

Abstract: A zero hold time data input cell is realized by employing a programmable data delay line containing a series of delay stages. Since each delay stage contributes only a fraction of the total data delay required, the rise/fall times of each data delay stage can be very fast, under all PVT (process/voltage/temperature) conditions. As a result, any amount of data delay can be provided at any data rate, while still allowing the delayed data waveform to make complete voltage excursions between the ground voltage and the power supply voltage. This capability prevents data dependent hold violations from occurring.

Abstract: A programmable circuit and method of programming that provide an easily fabricated circuit that does not require specialize manufacturing or packaging techniques. The circuit provides for temporarily setting the circuit outputs which can then be used for testing. The circuit also provides for permanently setting the output by applying sufficient voltage and current to the transistor that permanent spiking of the metallized contact layer through the junction occurs.

Abstract: Method and apparatus for preconditioning and in-use conditioning of transistors formed on a semiconductor-on-insulator structure is described. More particularly, transistors of a programmable logic device (PLD), such as a field programmable gate array (FPGA), are preconditioned to take advantage of charge accumulation owing to a “floating body” effect. This preconditioning takes a form of switching transistors on and off prior to customer operation. Accordingly, semiconductor-on-insulator transistors accumulate charge during this switching period, so when customer operation takes place, transistor switching times are less variable over a period of operation of the PLD. Additionally, a design process and implementation is described for identification and in-use conditioning of transistors that may need conditioning during customer operation to control switching time variability.

Abstract: In accordance with one aspect of the invention, a method is provided for identifying multiple, series-connected pass FETs in an integrated circuit, by evaluating a current node in the netlist to determine whether the current node is a static gate input (or output). If the node is that of a pass gate input (or output), the method then identifies at least one pass FET that is channel-connected to the current node, and determines that an output node (input node) of the at least one pass FET is the same node as the current node. Thereafter, the method reassigns the current node to be an input node (output node) of the at least one pass FET, and repeats the foregoing steps (beginning with identifying at least one pass FET that is channel-connected to the current node). In accordance with another aspect of the present invention, a system is provided for identifying multiple, series-connected pass FETs in an integrated circuit by evaluating a netlist.

Abstract: Described are systems for producing differential logic signals. These systems can be adapted for use with different loads by programming one or more programmable elements. One embodiment includes a series of driver stages, the outputs of which are connected to one another. The driver stages turn on successively to provide increasingly powerful differential amplification. This progressive increase in amplification produces a corresponding progressive decrease in output resistance, which reduces the noise associated with signal reflection. The systems can be incorporated into programmable IOBs to enable PLDs to provide differential output signals.

Abstract: An output driver that may be configured to operate as a totem-pole driver, or as an open-drain driver. The output driver comprises a totem-pole driver coupled to an output pin. A control circuit is coupled to the output enable input of the totem-pole driver. The control circuit is supplied with an open-drain control signal controlled by the user interface. When the open-drain control signal is at a first logic level, the output driver operates as an open-drain driver. When the open-drain control signal is at a second logic level, the output driver is configured to operate as a totem-pole driver.

Abstract: It is an object of the present invention to provide a sequential circuit having nonvolatile characteristics capable of holding data therein even when the power supply is shut-off. An inverter circuit INV1 is formed by replacing a pair of transistors consisting the conventional CMOS inverters with transistors NT and PT both having an MFMIS structure. A polarization state corresponding to an ON state is held in a ferroelectric layer 32 of the transistor NT even when the power supply thereof is shut off, and another polarization state corresponding to an OFF state is held in a ferroelectric layer 32 of the transistor PT. The transistors NT and PT are turned into ON and OFF state respectively according to the polarization states held in their ferroelectric layers 32 when the power supply is turned ON again. In this way, the inverter circuit INV1 recovers its state to the state right before the shut-off by turning the power supply into the ON state again.

Abstract: A programmable circuit and method of programming that provide an easily fabricated circuit that does not require specialize manufacturing or packaging techniques. The circuit provides for temporarily setting the circuit outputs which can then be used for testing. The circuit also provides for permanently setting the output by applying sufficient voltage and current to the transistor that permanent spiking of the metallized contact layer through the junction occurs.

Abstract: A method and apparatus for implementing dynamic logic with programmable dynamic logic gates acts as a complement to programmable logic arrays (PLAs) used in high-speed microprocessor designs. A matrix of selectable cells provides powerful logic functions such as AND-OR gate capability with a minimum of inputs and transistors. By using programmable logic arrays and programmable dynamic gates, the efficiency of a logic block can be dramatically improved with little added circuit area.

Abstract: A method and apparatus for detecting a predischarge node in an integrated circuit. The apparatus comprises a computer capable of being configured to execute a rules checker program which analyzes information relating to the integrated circuit to determine whether a predischarge node exists in the integrated circuit. The rules checker program evaluates each node in the integrated circuit and determines whether or not an N field effect transistor (NFET) is connected to the node and, if so, whether the gate terminal of the NFET is connected to a clock and whether a drain or source terminal of the NFET is connected to ground. The rules checker program also determines whether or not a P field effect transistor (PFET) is connected to the node being evaluated and, if so, whether it has a gate terminal which is not connected to a clock and drain and source terminals which are not connected to a supply.

Abstract: The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA.

Abstract: The invention provides a programmable delay element and a programmable slew rate element to allow post-fabrication adjustment and programming of input delay and output slew rate to iteratively alter input delay and output slew rate without redesign and refabrication of the circuit. The invention provides programmable memory cells coupled to a capacitive load via a plurality of switches. The capacitive load is coupled to a signal path and comprises a plurality of capacitors. The programmable memory cells selectively turn on the switches coupled to the capacitive load. In one FPGA implementation, the programmable memory cells are implemented in IOBs and are loaded with appropriate data during a device configuration stage. Delay equalization can be achieved by programming the memory cells such that the delays seen by device I/O pins are equal between IOBs and pads. The invention also provides a slew rate control circuit for an inverter or a buffer to provide an optimal slew rate.

Abstract: The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.

Abstract: A programmable device, such as a field programmable gate array, includes at least one signature bit that is used to indicate whether the programmable device has fewer than all the logic blocks accessible to the user. The signature bit may be programmed after the manufacture of the programmable device or may be hard wired during the manufacture of the device. The programming unit recognizes the configuration of the signature bit and restricts access to particular logic blocks based on the configuration. Thus, a large programmable unit may become a smaller “virtual” programmable device by altering the configuration of the signature bit, which is recognized by the programming unit. Consequently, the manufacturer may test market programmable devices of differing sizes to determine demand without incurring the costs associated with producing a completely new product line.

Abstract: An input circuit has an inverter and a differential amplifier, which are respectively connected on an input side to an input and on an output side to an output of the input circuit. The input circuit has two operating modes defined by an activation signal, the differential amplifier being activated and the inverter being deactivated in a first operating mode, and the differential amplifier being deactivated and the inverter being activated in a second operating mode. In this manner, the input circuit has the advantage of selective operation with LVTTL or SSTL levels.

Abstract: The invention provides a programmable delay element and a programmable slew rate element to allow post-fabrication adjustment and programming of input delay and output slew rate to iteratively alter input delay and output slew rate without redesign and refabrication of the circuit. The invention provides programmable memory cells coupled to a capacitive load via a plurality of switches. The capacitive load is coupled to a signal path and comprises a plurality of capacitors. The programmable memory cells selectively turn on the switches coupled to the capacitive load. In one FPGA implementation, the programmable memory cells are implemented in IOBs and are loaded with appropriate data during a device configuration stage. Delay equalization can be achieved by programming the memory cells such that the delays seen by device I/O pins are equal between IOBs and pads. The invention also provides a slew rate control circuit for an inverter or a buffer to provide an optimal slew rate.

Abstract: A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including a CMOS multiplexer controlled by a fuse or anti-fuse, an NMOS or PMOS pass gate controlled by a fuse or anti-fuse, or even a fusible link which is severed to effect isolation. Additionally, a circuit is provided that switchably isolates one of two contact pads from a logic circuit.

Abstract: A programmable circuit is provided. The programmable circuit includes a programmable inverter circuit (PIC) that is configured to receive an input signal and to generate an output signal. The programmable circuit also includes a teaching circuit that is coupled to the PIC. The teaching circuit is configured to compare the output signal of the PIC to a desired output signal. Responsive to this comparison, the teaching circuit is configured to generate a control signal to the PIC. In response to the control signal the PIC is configured to generate the desired output signal.

Abstract: A programmable buffer circuit comprises a logical gate circuit having a second input terminal, a third input terminal and a first output terminal, and a first input terminal. The second input terminal is connected to the first input terminal. Further, a selective signal generating circuit for supplying two kinds of selective signals in logical level to the third input terminal is provided. A tri-state inverter circuit having a fourth input terminal and a second output terminal is provided and a tri-state buffer circuit having a fifth input terminal and a third output terminal is provided. The fourth input terminal and the fifth input terminal are connected to the first output terminal. A fourth output terminal is connected to the second output terminal and the third output terminal.

Abstract: The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuits presenting two parallel signal paths: a low-voltage path used in read mode, and a high-voltage path used in programming mode. A CMOS switch separates the two paths, is driven by high voltage via a voltage shifter in programming mode, and, being formed at predecoding level, involves no integration problems.

Abstract: The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.

Abstract: The invention provides a programmable delay element and a programmable slew rate element to allow post-fabrication adjustment and programming of input delay and output slew rate to iteratively alter input delay and output slew rate without redesign and refabrication of the circuit. The invention provides programmable memory cells coupled to a capacitive load via a plurality of switches. The capacitive load is coupled to a signal path and comprises a plurality of capacitors. The programmable memory cells selectively turn on the switches coupled to the capacitive load. In one FPGA implementation, the programmable memory cells are implemented in IOBs and are loaded with appropriate data during a device configuration stage. Delay equalization can be achieved by programming the memory cells such that the delays seen by device I/O pins are equal between IOBs and pads. The invention also provides a slew rate control circuit for an inverter or a buffer to provide an optimal slew rate.

Abstract: A multiple-power IC device comprising an input buffer circuit for receiving an input signal and a plurality of power voltages of different magnitudes. The input buffer circuit has an output associated with each of the plurality of power voltages for outputting the input signal in accordance with a predetermined threshold voltage. The device further comprises an internal circuit, a switching circuit interposed between the input buffer circuit and the internal circuit, and a power voltage determination circuit coupled to the switching circuit and receiving the plurality of power voltages. The power voltage determination circuit controls the switching circuit to selectively couple an output of the input buffer circuit to the internal circuit in accordance with the magnitude of the received power voltage. Thus, the input signal is coupled to the internal circuit according to the predetermined threshold voltage regardless of the power voltage applied to the input buffer circuit.

Abstract: The present invention provides a PLA structure having logic interposed between an AND plane and an OR plane, wherein the interposed logic provides an additional set of minterms to the OR plane such that any PLA output function can be implemented with substantially fewer input signals. In this way, parasitic loading for implementation of any particular logic function is reduced.

Abstract: A high speed, low power 3-2 adder (300, 500) with latchable outputs comprises a most significant bit (MSB) adder circuit (100) and a least significant bit (LSB) adder circuit (200). MSB adder circuit (100) includes three differential data inputs (A1, B1, and C1), a latch enable input (LE1), three separate bias points, and an MSB output. In addition the LSB adder circuit includes three differential data inputs (A2, B2, and C2), a latch enable input (LE2), three separate bias points and a LSB output. Internal latch circuits (172, 272) and latch enable circuits (174, 274) are provided in each adder stage. Internal latch enable inputs are connected in parallel in one configuration. Separate latch enable inputs are provide in a second configuration. Separate bias points are also provided in each adder stage.

Abstract: A programmable logic device includes a plurality of logic elements. Each logic element includes a raw of transistors formed between a bit line and a source line, elements for generating a complement signal to the bit line signal (the elements have an output complement line) and a differential sense amplifier. Each transistor of the row is connected to a different one of the input lines and has a predefined logic state. The complement line is based on the source line whose signal acts opposite to that of the bit line. The differential sense amplifier is connected to the bit line and to the complement line and indicates when the bit line signal crosses the complement line signal. In one embodiment, the source line signal is raised, in another, the bit line signal is lowered, both with offset circuitry.

Abstract: Logic devices of the present invention have one or more MOSFETs that are configured to operate in logic circuits, where voltages applied to the source and drain of each MOSFET are treated as logic inputs to the circuit and the resulting substrate current is treated as the logic output of the circuit. In one implementation, a MOSFET is configured in a circuit to operate as an XOR gate where a load resistor between the substrate and ground converts the substrate current into an output voltage. A sample-and-hold circuit samples and holds the output voltage to isolate the XOR gate thereby allowing DC power dissipation to be reduced. In another implementation, three MOSFETs are configured to operate as an "ORNAND" logic device that performs the logical addition of the OR function and the NAND function.

Abstract: A logic function module comprises a plurality of input nodes and an output node. A first control circuit has at least one input connected to one of the input nodes, a first output, and a second output which is the complement of the first output. A second control circuit has at least one input connected to one of the input nodes, a first output, and a second output which is the complement of the first output. A first switching circuit is connected between one of the input nodes and the output node and is controlled from the first output of the first control circuit the first output of the second switching circuit. A second switching circuit is connected between one of the input nodes and the output node and is controlled from the second output of the first control circuit the first output of the second switching circuit.

Abstract: An object of the present invention is to decrease the number of terminals of a semiconductor integrated circuit by utilizing one terminal for a plurality of purposes, and reduce the cost of it, suppressing the performance degradation of the semiconductor integrated circuit. The present invention can be adapted to a semiconductor integrated circuit in which at least one of power supply terminals or ground terminals connected on a power supply path of an output circuit of the semiconductor integrated circuit is installed independently of a power supply path of an internal circuit. In a normal operation mode in which a test mode input terminal .PHI. is low, power is supplied to an output circuit 5 through an output circuit power supply/testing signal input terminal OVDD/TIN. In a test mode in which the test mode input terminal .PHI.

Abstract: A semiconductor integrated circuit is provided, which decrease the circuit scale of an enabling circuit used for enabling and disabling an internal circuit. The enabling circuit has a first switching element with first and second terminals, a second switching element with first and second terminals, and a third switching element with first and second terminals. One of the first, second, and third switching elements is turned on and the remaining two ones thereof are turned off according to a program. The first terminal of the first switching element is applied with an enabling signal. The first terminal of the second switching element is applied with a disabling signal. The first terminal of the third switching element is applied with a Don't Care signal. The second terminals of the first, second, and third switching elements are connected in common to a node. One of the enabling signal, the disabling signal, and the Don't Care signal is selectively outputted to the node according to the program.

Abstract: A fuse-programmable circuit controllably enables or disables an electrical signal (S). The circuit includes a transmission gate (118) connected between the circuit's input and output terminals. The transmission gate is controlled by complimentary outputs OUTH, OUTL of a fuse-programmable latch (130). A PMOS transistor (Q41) and a fuse (F41) are connected in series between the output terminal and a power supply voltage (VCC). An NMOS transistor (Q42) and a fuse (F42) are connected in series between the output terminal and a reference voltage (ground). The gate of the PMOS transistor is connected to the latch output OUTH. The gate of the NMOS transistor is connected to the latch output OUTL. When OUTH is high and OUTL is low, the transmission gate couples the signal (S) from the input terminal to the output terminal. When OUTH is low and OUTL is high, the transmission gate is closed.

Abstract: There is disclosed an integrated circuit including a programmable driver circuit having first and second transistors. Each of the first and second transistors has first, second and third terminals. The first terminal of each of the first and second transistors are coupled together to form an input node. The second terminal of the first transistor is coupled to a power node. A third terminal of the first transistor is coupled to a first intermediate node. The second terminal of the second transistor is coupled to a second intermediate node. The third terminal of the second transistor is coupled to a reference potential. A first switch having at least one input is coupled between the first and second intermediate nodes. Third and fourth transistors each having first, second and third terminals. The first terminal of the third transistor is coupled to a third intermediate node. The first terminal of the fourth transistor is coupled to the second intermediate node.

Abstract: A variable logic circuit comprises a memory cell, a transistor which turns on or off depending on data stored in the memory cell, a transistor which is connected in series to the above-mentioned transistor and is turned on or off by an input signal, a transistor which produces a voltage depending on the conduction states of the above-mentioned transistors, and transfer means which conducts or does not conduct the produced voltage to the output terminal depending on a select signal.

Abstract: A programmable bidirectional interconnect circuit selectively provides either a buffered connection, a non-buffered connection, or a disconnection (tristate mode). The circuit includes six transistors coupled to a buffer and two signal lines.

Abstract: The invention provides a programmable delay element and a programmable slew rate element to allow post-fabrication adjustment and programming of input delay and output slew rate to iteratively alter input delay and output slew rate without redesign and refabrication of the circuit. The invention provides programmable memory cells coupled to a capacitive load via a plurality of switches. The capacitive load is coupled to a signal path and comprises a plurality of capacitors. The programmable memory cells selectively turn on the switches coupled to the capacitive load. In one FPGA implementation, the programmable memory cells are implemented in IOBs and are loaded with appropriate data during a device configuration stage. Delay equalization can be achieved by programming the memory cells such that the delays seen by device I/O pins are equal between IOBs and pads. The invention also provides a slew rate control circuit for an inverter or a buffer to provide an optimal slew rate.

Abstract: A digitally controlled trim circuit which includes a plurality of resistors connected in series between a circuit node and a reference voltage, a plurality of first solid-state switches (e.g., PMOS transistors) connected in series across respective ones of the resistors, a plurality of multiplexers each having an output coupled to the gate electrode of a respective one of the first switches, a plurality of first control lines coupled to a first input of respective ones of the multiplexers, a plurality of second control lines coupled to a second input of respective ones of the multiplexers, and a plurality of fuses coupled to respective ones of the first control lines. The trim circuit is operable in a trim test mode in response to a first logic level of a select control signal coupled to the select input of each of the multiplexers, and is operable in a fuse-program mode in response to a second logic level of the select control signal.

Abstract: A programmable high speed routing switch is provided which has a lower ON-resistance so as to increase its gate oxide reliability. The routing switch includes a non-volatile memory cell (12) having a floating gate (FG). The floating gate is selectively charged and discharged to provide either a net positive potential or a net negative potential. The routing switch also includes a memory transistor (14), a pass gate transistor (16), and a poly load element (18). The source of the memory transistor is connected to a first power supply potential. The gate of the memory transistor is connected to the floating gate of the memory cell, and the drain thereof is connected to the gate of the pass gate transistor and to a first end of the poly load element. The drain of the pass gate transistor is connected to a first signal line (PG1) and the source of the pass gate transistor is connected to a second signal line (PG2). The second end of the poly load element is connected to a second power supply potential.

Abstract: A circuit for a sense amplifier (14) for use with a memory device (10). The circuit includes two devices (40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second device (42) drives the sense amplifier (14) with a second current level, different from the first current level. The selector (44) is coupled to the first and second devices (40 and 42) so as to selectively couple one of the first and second devices (40 and 42) to the sense amplifier (14) based on a power supply voltage of the memory device (10).

Abstract: A selector circuit with symmetry is disclosed. It steers input transition events to one of two outputs according to the value of a data input signal. The selector circuit includes a first flip-flop and a second flip-flop. Depending on the state of a data input, one of the two flip-flops is enabled and the other is disabled. The disabled flip-flop will be in a tristate mode. The enabled flip-flop continues storing its data, and may load the disabled flip-flop with this data. The selector circuit further includes pass gates to couple the outputs of the flip-flops based on the state of the event input.

Abstract: The present invention provides a device for terminating a data bus. The present invention provides the proper termination without the use of external discrete components. The device can be programmed, at the chip level, to produce particular termination resistances that are commonly used. The present invention termination device uses a minimum of power dissipation which may be useful in applications that require minimum power consumption.

Abstract: A configurable NAND/NOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The NAND/NOR logic element (FIG. 3, 50) is configurable as either a NAND or a NOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). C inputs control p- and n-channel transistors. Depending on whether the C input is deasserted or asserted, respective internal nodes are shorted to effect the selected configuration. Specifically, deasserting C provides the NAND configuration, while asserting C provides the NOR configuration. In an alternative embodiment, the NAND/NOR logic element can be used in a full adder to provide the carry output.

Abstract: A configurable multi-directional buffer circuit for a programmable integrated circuit. The novel buffer circuit is a configurable multi-directional buffer circuit having one pair of inverters and having a first input/output line and a second input/output line and a third input line multiplexed with the first input/output line. The novel buffer circuit is configurable to allow a signal from the first input/output line to be driven over the second input/output line or configurable to allow a signal from the second input/output line to be driven over the first input/output line. The novel buffer circuit also allows a signal over the third input line to be driven over the second input/output line. In either case, only a single pair of inverter circuits are used. In an alternate embodiment, the novel buffer allows signal over a fourth input line to be driven over the first input/output line.

Abstract: A polarity control circuit for selectively providing a signal received at a data port to a first output port, and a second complementary output port, with a state as determined by a polarity selection signal provided to the polarity control circuit. The polarity control circuit includes circuitry configured to reduce gate delays.

Abstract: A multi-function resonant tunneling logic gate is provided in which a resonant tunneling transistor (12) includes a first terminal, a second terminal, and a third terminal. A plurality of signal inputs are coupled to the first terminal of the resonant tunneling transistor (12) through a summer (10). Furthermore, a biasing input is operable to apply a bias to the first terminal of resonant tunneling transistor (12) such that the transfer characteristic of the resonant tunneling transistor (12) can be shifted relative to the signal inputs.

Abstract: A system of interface circuits (15, 20-1 through 20-N) includes a mode sensing circuit (15) and one or more output circuits (20-1 through 20-N). The mode sensing circuit is arranged for producing control signals (on leads 22, 24) in response to an input signal (on lead 21). The output circuit (34-1) is arranged for producing an output data signal (DQ-1) dependent upon an input data signal (DATA) when the input signal (on lead 21) is in a first state and dependent upon the input data signal and the configuration of the connected output circuit (34-1) when the input signal is in a second state.

Abstract: First and second transistors are connected via a first switch. Second and third transistors are connected in parallel via a second switch. Either an input signal or an output ground voltage is applied to the gate of a third transistor via a third switch. In a LVTTL version, the first switch is on and the second switch is off. By the third switch, the output ground voltage is applied to the gate of the third transistor. As a result, first and second, transistors are arranged in series between the output power supply voltage and the output ground voltage, resulting in an output buffer circuit corresponding to a LVTTL. In a GTL version, the first switch is off and the second switch is on. An input signal is applied to the gate of the third transistor by the third switch. As a result, second and third transistors are arranged in parallel to form an open drain. This can be used as an output buffer circuit corresponding to a GTL.

Abstract: Electrical characteristics of the inputs to VLSI semiconductor chips can be modified after the chips are fabricated and mounted into multichip modules (packages), at which time the required characteristics are known accurately. The changes are accomplished by incorporating special circuitry at the chip inputs during their design combined with the use of `boundary-scan` type circuitry that has recently been put in place for device testing. The circuitry allows the impedance characteristics of the chip's receiver to be modified to match that of the driving source and the wiring interconnections between the chip and source. The test circuitry is used to provide the logical signals to selectively switch the circuits to the proper configuration. This enables optimally designed interconnections between the input and output circuitry on the chips and thereby avoids the necessity for costly re-designs.

Abstract: There is a zero power programmable logic device with a one time programmable and fully-testable anti-fuse cell architecture. Specifically, a half-latch and fuse cell circuit allows the PLD to use "zero power" during the standby period since the sense amps are not used to maintain the programmed logic. Additionally, the PLD is capable of being tested for logic gate and logic path integrity, and anti-fuse electrical parameters without permanently programming the anti-fuse.