Abstract: Numerous examples are disclosed for an output block coupled to a non-volatile memory array in a neural network and associated methods. In one example, a circuit for converting a current in a neural network into an output voltage comprises a non-volatile memory cell comprises a word line terminal, a bit line terminal, and a source line terminal, wherein the bit line terminal receives the current; and a switch for selectively coupling the word line terminal to the bit line terminal; wherein when the switch is closed, the current flows into the non-volatile memory cell and the output voltage is provided on the bit line terminal.

Abstract: Techniques are provided for calibrating signal currents in a radio frequency signal generator system, such as an arbitrary waveform generator system. A device comprises a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured, during a calibration process, to measure a first current in a first signal path of a radio frequency signal generator, and to measure a second current in a second signal path of the radio frequency signal generator. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current.

Abstract: A directional coupler includes a main line through which a signal is transmitted, first and second sub-lines that are selectively coupled to the main line, and a common output port that outputs a detection signal generated by the signal transmitted through the main line, wherein a first degree of coupling between the main line and the first sub-line is different than a second degree of coupling between the main line and the second sub-line.

Abstract: An electronic switch is composed of two anti-serially connected turn-off semiconductor switches having at least four terminals and at least three terminals, respectively. A method for detecting a turn-off current through the electronic switch for a DC voltage grid includes measuring a first voltage between an emitter terminal and an auxiliary emitter terminal at the first switch, measuring a second voltage between a collector terminal and an emitter terminal or between a drain terminal and a source terminal at the second switch, comparing the first and second measured voltage or a time integral of the first and second measured voltage with a reference value, and turning off at least one of the two turn-off semiconductor switches when the reference value is exceeded. An electronic switch for performing the method and a DC voltage grid with such an electronic switch are also disclosed.

Abstract: A bias circuit includes a linear core circuit CC with first and second mutually type corresponding transistors (M1; M2) and a current mirror CM with third and fourth transistors (M3; M4) of opposite type of M1 and M2. To obtain an equilibrium with a constant transconductance of the first transistor, first and second negative feedback loops (L1; L2) are applied, one including the linear core circuit CC, the other including the current mirror CM. In a first setting one loop suppresses differences between first and second drain voltages (Vd1; Vd2) and the other loop suppresses differences between one of of the first and second drain voltage Vd1 and Vd2 and a reference voltage Vref. In the second setting, one loop suppresses differences between the first drain voltage Vd1 and the reference voltage Vref and the other loop differences between the second drain voltage Vd2 and the reference voltage Vref.

Abstract: A digitally controlled grounded capacitance multiplier circuit system and method is disclosed. The capacitance multiplier (CM) circuit comprises an op-amp, a digitally controlled current amplifier and two resistors in addition to a reference capacitor. The CM circuit is designed using complementary metal-oxide-semiconductor (CMOS) technology. The value of the equivalent capacitance can be adjusted through digitally programming the gain of the current amplifier. The CM circuit provides a significant multiplication factor while using two active devices.

Abstract: One example includes a transconductor system. The system includes a first transconductance amplifier that generates a control current in response to a first input voltage. The system also includes a second transconductance amplifier that generates an output signal in response to a second input voltage. The system further includes an intermediate amplifier that generates a control voltage in response to the control current and a third input voltage. The control voltage can be provided to the first and second transconductance amplifiers to set a transconductance of each of the first and second transconductance amplifiers to be approximately equal.

Abstract: In a general aspect, a circuit can include an input circuit configured to receive an input signal, and an amplifier circuit coupled with the input circuit. The amplifier circuit can include an amplifier, and first and second feedback paths. The first feedback path can be from a positive output to a negative input of the amplifier, and the second feedback path can be from a negative output to a positive input of the first amplifier. The circuit can also include a loop circuit configured to provide a local feedback loop for the first amplifier and configured to control current flow into the positive input of the first amplifier and current flow into the negative input of the first amplifier. The circuit can also include a control circuit that is configured to enable the loop circuit in response to a magnitude of the input signal exceeding a threshold.

Abstract: Provided is an image sensor including: a pixel section configured to include a plurality of pixels arranged therein; and an AD conversion unit configured to perform analog-to-digital (AD) conversion on a pixel signal on the basis of a result of comparison between a first voltage of a signal, which is obtained by adding, via capacitances, the pixel signal of the pixel and a reference signal that linearly changes in a direction opposite to the pixel signal, with a second voltage serving as a reference.

Abstract: An apparatus for generating an output current including a first distortion current based on a first transconductance and a second distortion current based on a second transconductance is disclosed. The first distortion current may be generated by an amplifier and the second distortion current may be generated by a distortion compensator. The second transconductance may be less than the first transconductance. In some implementations, the second distortion current may reduce the first distortion current output by the apparatus.

Abstract: Current sensing in an on-die direct current-direct current (DC-DC) converter for measuring delivered power is disclosed. A DC-DC converter converts input voltage to output current at an output voltage coupled to a load circuit. The DC-DC converter includes a high side driver (HSD) circuit to drive the output current in a first stage, and a low side driver (LSD) circuit to couple the power output to a negative supply rail (GND) in a second phase, output current being periodic. The DC-DC converter includes an amplifier circuit to equalize an output voltage and a mirror voltage. Based on the mirror voltage, the current sensing circuit generates mirror current that corresponds to driver current. The mirror current can be measured as a representation of the output current delivered to the load circuit. A plurality of the DC-DC converters can provide multi-phased current to the load circuit for providing power to the load circuit.

Abstract: A method and apparatus for sensing a common mode feedback current are provided. The common mode feedback current may flow through a common mode resistive divider of a piezoresistive bridge. A first current mirror mirrors the common mode feedback current and provides a first mirrored common mode current. A current aggregation stage receives the first mirrored common mode current and determines a bridge current of the piezoresistive bridge based on the first mirrored common mode feedback current. A second current mirror may be used to mirror the first current mirror before determining the bridge current.

Abstract: The present disclosure provides a serial port communication mode conversion method, system, and circuit for a serial port circuit, in which the serial port circuit includes a first serial port and a second serial port, a transmission signal line of the first serial port and a reception signal line of the second serial port are connected to form a half-duplex signal line. The method includes: configuring the second serial port to enable after a preset time; controlling the first serial port to transmit a control signal to an external device through the half-duplex signal line within the preset time; and controlling the second serial port to receive response data transmitted by the external device through the half-duplex signal line after the preset time. The present disclosure realizes the conversion of the full-duplex serial port to the half-duplex serial port.

Abstract: An apparatus to prevent supply-to-ground current in a comparator is disclosed. The apparatus includes circuitry to determine if first and second output nodes of the comparator have respectively reached first and second logic levels, and circuitry responsive to a determination that the voltage at the first and second output nodes of the comparator has reached the first and second logic levels, to generate a signal. In addition, the apparatus includes circuitry to supply the signal to a transistor, the signal to turn off the transistor and prevent the flow of supply-to-ground current through the comparator.

Abstract: An integrated circuit for measuring a signal, including a parametric pin measurement unit (PPMU) that sends a forced signal, the PPMU having a first amplifier, a second amplifier with an output terminal connected to the input terminals of the first amplifier through a common resistor; a voltage-to-current convertor connected to a PPMU output and having a first output and a second output; n channel MOSFETs connected to the first output of the voltage-to-current converter; p channel MOSFETs connected to the second output of the voltage-to-current converter; a buffered amplifier connected to an output port between the n channel MOSFETs and the p channel MOSFETs; and a resistance divider connected to the output of the buffered amplifier.

Abstract: A low dropout amplifier may include an error amplifier having first and second inputs coupled to a reference signal and a feedback signal, respectively. The error amplifier may be configured to generate first and second error signals at first and second outputs, respectively, with the first and second error signals based upon a difference between the reference signal and the feedback signal. A sink stage may be coupled to the first output and configured to generate a sink current based upon the first error signal. A source stage may be coupled to the second output and configured to generate a source current based upon the second error signal. An output node may be coupled to receive the sink and source currents.

Abstract: The disclosed embodiments relate to the design of a system that implements an up-conversion mixer. This system includes a regulator-based linearized transconductance (gm) stage, which converts a differential intermediate frequency (IF) voltage signal into a corresponding pair of IF currents. It also includes a pair of current mirrors, which duplicates the pair of IF currents into sources of a set of switching transistors. The set of switching transistors uses a differential local oscillator (LO) signal to gate the duplicated pair of IF currents to produce a differential radio frequency (RF) output signal. Finally, a combination of capacitors and/or inductors is coupled to common source nodes of the set of switching transistors to suppress higher order harmonics in an associated common source node voltage signal.

Abstract: A temperature-dependent current generator includes a first transistor connected between first and second nodes and providing a first voltage potential at the second node that decreases first order linearly when ambient temperature increases. The generator further includes an operational amplifier having first and second input terminals and an output terminal. The first input terminal is coupled to a second voltage potential that is first order independent of the ambient temperature. The second input terminal is coupled to a third node. The generator further includes a second transistor with gate, source, and drain terminals. The gate terminal is coupled to the output terminal of the operational amplifier. One of the source and drain terminals is coupled to the third node. The generator further includes a resistor coupled between the second and the third nodes. A resistance value of the resistor is first order independent of the ambient temperature.

Abstract: A common mode feedback (CMFB) loop for a differential amplifier sense an output common mode of a differential circuit and provides feedback to the gates of tail current transistors. Many CMFB loops cannot easily adjust the output common mode voltage and the output common mode may vary over process, voltage, and temperature. An improved CMFB circuit adds a control circuit to control backgates of tail current transistor device(s) of the differential circuit such that the output common mode voltage can be made adjustable.

Abstract: A continuous-time delta-sigma modulator includes a loop filter, a quantizer, a finite impulse response (FIR) filter, and a digital to analog converter. The loop filter integrates a difference between an input signal and a feedback signal. The quantizer quantizes a signal output from the loop filter to convert the quantized signal into a digital signal. The FIR filter performs an FIR filtering process on the digital signal output from the quantizer. The digital to analog converter converts a signal output from the FIR filter into an analog signal and outputs the converted analog signal as a feedback signal.

Abstract: A current generator includes an amplifier having a first terminal configured to receive a first voltage, a tunable resistance circuit coupled to an output terminal of the amplifier through a first transistor, a calibration circuit coupled to the tunable resistance circuit, and a second transistor. The second transistor includes a gate terminal coupled to the output terminal of the amplifier and a drain terminal coupled to a load. The calibration circuit is configured to adjust a resistance setting of the tunable resistance circuit.

Abstract: A buffer circuit includes a first transistor, a second transistor, a feed-forward circuit and a resistive bias circuit. The first transistor has a first terminal, a second terminal and a third terminal, wherein the first terminal of the first transistor is served as an input terminal of the buffer circuit. The second transistor has a first terminal and a second terminal, wherein the second terminal of the second transistor is coupled to the third terminal of the first transistor and served as an output terminal of the buffer circuit. The feed-forward circuit has a first terminal and a second terminal respectively coupled to the first terminal of the second transistor and the second terminal of the first transistor. The resistive bias circuit has a first terminal and a second terminal respectively coupled to the second terminal of the first transistor and the first terminal of the feed-forward circuit.

Abstract: A redundant isolating switch control circuit comprises a working power supply, a power input end, a power output end, at least one field-effect transistor, a first transistor, and a second transistor. The field-effect transistor comprises a gate electrode, a source electrode connected to the power input end and a drain electrode connected to the power output end. The first transistor and the second transistor together with the associated circuits form a current mirror circuit. The redundant isolating switch control circuit further comprises a first electronic unit comprising a first connecting end connected to the first base electrode of the first transistor and a second connecting end connected to the second emitter electrode of the second transistor, and a second electronic unit comprising a third connecting end connected to the first collector of the first transistor and a fourth connecting end connected to the gate electrode.

Abstract: A multi-phase parallel converter can include: sampling circuits corresponding to power stage circuits to form a plurality of phases of the multi-phase parallel converter, where each sampling circuit samples an inductor current of a corresponding power stage circuit, and generates a sense signal; a current-sharing circuit that generates a current-sharing control signal according to a superimposed signal that is generated by adding the sense signal to a bias voltage signal; switching control circuits corresponding to the power stage circuits, where each switching control circuit receives the current-sharing control signal, and controls a switching operation of a corresponding power stage circuit; and a bias voltage generator that generates the bias voltage signal to gradually increase/decrease when a selected phase is to be disabled/enabled.

Abstract: A control arrangement is disclosed for a switch mode power supply (SMPS) operable in a burst mode and comprising an opto-coupler configured to transfer, from a secondary side to a primary side of the switch mode power supply by means of an LED current, a control signal indicative of a time-varying error between a reference signal and a signal indicative of an actual value of an output parameter, the control arrangement comprising: an error amplifier configured to operate as a proportional-integrating error amplifier to determine the LED current from the time-varying; and a feedback loop configured to adjust the magnitude of the LED current between bursts by modifying the time-dependant error. A SMPS comprising such a control arrangement, and a corresponding method is also disclosed.

Abstract: Two or more power converters are connected in parallel to supply power current to a joining node through connecting resistors. An output voltage before the connecting resistor in each power converter is sampled and divided by a sampling ratio to generate sampled voltages for each power converter. A current sharing circuit for each power converter receives the local sampled voltage and another sampled voltage from another power converter. The current sharing circuit generates an adjustment voltage that is injected into a feedback loop. The adjustment voltage modifies the output voltage of the power converter, adjusting and balancing the power current delivered by that power converter. Power currents from several power converters are reduced and balanced when the same sampling ratio is used for all power converters. Current hogging by one power converter is prevented.

Abstract: The current-to-voltage converter includes an input for the current to be converted, an output for the converted voltage, a current-to-voltage conversion resistor arranged between the output and a reference potential, a processing circuit including a transistor, the input being connected to the output via the transistor, a twin circuit including components identical to and disposed in a similar way to those of the processing circuit, a voltage follower connected at the input to the processing circuit and at the output to the twin circuit, and means for reinjecting the current at the output of the follower into the processing circuit.

Abstract: To provide an oscillation circuit device capable of when detecting an input reference signal and making a transition from a self-running state to a PLL operation, suppressing a fluctuation in the frequency of an output signal CLK to thereby obtain a smoothly-synchronized and stable output signal CLK. There is provided an oscillation circuit device which is adapted to configure a negative feedback circuit by a V/I conversion element to which one end of a filter circuit is connected, and a buffer circuit in a self-running state, and has a configuration which enables a capacitance in the filter circuit to be charged rapidly in such a manner that an output signal CLK can be started from a frequency equal to that in the self-running state immediately after a transition to a PLL operation.

Abstract: An integrated circuit for measuring a signal, including a parametric pin measurement unit (PPMU) that sends a forced signal, the PPMU having a first amplifier, a second amplifier with an output terminal connected to the input terminals of the first amplifier through a common resistor; a voltage-to-current convertor connected to a PPMU output and having a first output and a second output; n channel MOSFETs connected to the first output of the voltage-to-current converter; p channel MOSFETs connected to the second output of the voltage-to-current converter; a buffered amplifier connected to an output port between the n channel MOSFETs and the p channel MOSFETs; and a resistance divider connected to the output of the buffered amplifier.

Abstract: A voltage adjustment circuit for adjusting a voltage to be supplied to scanning lines of a display device includes a slope adjustment circuit configured to adjust a slope of a decrease in the voltage based on data that is externally input, and a clamp voltage adjustment circuit configured to adjust a voltage value at which the voltage is clamped based on the data.

Abstract: Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes. The first bias voltage is provided to a gate of a first transistor among a plurality of transistors coupled in series. The first and second circuit branches are arranged to provide a second bias voltage to gate of a second transistor among the plurality of transistors. The value of the second bias voltage is based on a value of the first bias voltage.

Abstract: A variable gain amplifying circuit incorporates an operational amplifier, an input device, a feedback device, a transconductance circuit, and a dynamic biasing circuit. The operational amplifier has an output terminal providing an amplified difference output signal. The input device has a first terminal receiving a first input signal, and a second terminal coupled to a first input terminal of the operational amplifier. The feedback device is coupled between the first input terminal of the operational amplifier and the output terminal of the operational amplifier. The dynamic biasing circuit generates a bias current according to a set value. The transconductance circuit converts the difference between the first input signal and a second input signal into an analog output current flowing through the feedback device. The analog output current of the transconductance circuit is varied according to the bias current.

Abstract: A semiconductor device in which current sensing accuracy is maintained while ruggedness of a current sensing region is improved. The semiconductor device includes a semiconductor substrate; a main element provided on the semiconductor substrate and having a first trench gate structure including a first trench disposed on a first main surface side of the semiconductor substrate; a gate insulating film disposed along an inner wall of the first trench; and a gate electrode disposed inside the first trench; and a current detecting element for detecting a current flowing into the semiconductor substrate when the main element is operating provided on the semiconductor substrate and having a second trench gate structure including a second trench disposed on the first main surface side of the semiconductor substrate; the gate insulating film disposed along an inner wall of the second trench; and the gate electrode disposed inside the second trench.

Abstract: The embodiments described herein include systems with a variable reluctance sensor (VRS) interface and methods of their operation. Embodiments of VRS interfaces include a clearing signal generator configured to generate a clearing signal corresponding with the timing of a noise event. The clearing signal may be configured to clear a post-processing circuit.

Abstract: An electronic device and an integrated circuit thereof are provided. The integrated circuit includes a voltage generator and a current generator with a negative temperature coefficient. The voltage generator generates a reference voltage proportional to an absolute temperature based on a predetermined value. The current generator with the negative temperature coefficient receives the reference voltage and generates a reference current based on the reference voltage.

Abstract: Disclosed herein are techniques for generating a temperature independent reference current, which may be used during calibration. The temperature independent reference current may be generated based on a current through an on-chip calibration resistor. This alleviates the need for an off chip calibration resistor, which can be costly and cause slow calibration. A voltage at one terminal of the on chip calibration resistor may be modulated to substantially cancel a temperature coefficient of the on chip calibration resistor. This may result in the current passing through the on chip calibration resistor being temperature independent. The temperature independent reference current may be based on a reference voltage and a target calibration resistance.

Abstract: Disclosed is a digital-analog converter including a current generation section, a current source transistor bias voltage keeping section, a cascade transistor group switch section, and a conversion section. The current generation section has at least one current source transistor group including a plurality of current source transistors and generates an output current based on a value of a digital input signal. The current source transistor bias voltage keeping section has a plurality of cascade transistor groups each including cascade transistors connected in series to the current source transistors and keeps bias voltages of the current source transistors constant. The cascade transistor group switch section selects one of the plurality of cascade transistor groups. The conversion section performs current-voltage conversion of the output current supplied via the selected cascade transistor group.

Abstract: A circuit comprises a first path, a second path, a current generating circuit, and a sense amplifier. The first path has a first current having a first current value. The second path has a second current having a second current value. The current generating circuit is configured to generate a reference current having a reference current value based on the first current value and the second current value. The sense amplifier is configured to receive a third current having a third current value and to generate a logical value based on the reference current value and the third current value.

Abstract: Disclosed herein is a signal processing apparatus for a wheel speed sensor, which monitors a current input to a wheel speed sensor so as to prevent the current from being excessively supplied to the wheel speed sensor. That is, the present disclosure relates to the signal processing apparatus for a wheel speed sensor, which monitors the current input to the wheel speed sensor in a duplex manner. The signal processing apparatus for a wheel speed sensor include a sensor input terminal unit to which a sensing signal of a wheel speed sensor is input, and a normality determination block determining whether or not the sensing signal is normal.

Abstract: A DC-DC converter, having an input voltage and an output voltage, includes an inductor and a switch switching the input voltage to an input side of the inductor, where a feedback path controlling initiation of closing the switch includes capacitive coupling of the voltage at the input side of the inductor.

Abstract: A current source includes a first current path including a first current mirror transistor and an input current source coupled in series, a second current path including a second current minor transistor, wherein control terminals of the first and second current minor transistors are connected, a first circuit configured to provide a controlled auxiliary current in the second current path, and a second circuit configured to provide a controlled output current in the second current path when or after the auxiliary current has reached steady state. The current source may include one or more cascode transistors in the first current path and one or more cascode transistors in the second current path. The first circuit may be activated before the second circuit is activated.

Abstract: A transmitter is provided that includes a voltage-mode driver and a current-mode driver. The current-mode driver includes a plurality of transconductors biased by high-pass filtered versions of a differential output voltage from the voltage-mode driver.

Abstract: In one implementation, a voltage converter includes a driver providing a gate drive for a power switch and a sense circuit coupled across the power switch. The gate drive provides power to the sense circuit, and the sense circuit provides a sense output to the driver corresponding to a current through the power switch. In one implementation, the sense circuit includes a high voltage (HV) sense transistor coupled between a first sense input and a sense output, a delay circuit configured to be coupled to the gate drive to provide power to the HV sense transistor when the gate drive is high, and a pull-down transistor configured to couple the sense output to a second sense input when the gate drive is low.

Abstract: A dummy MOSFET is connected in series with a device under test to form cascode structure. The conductance of the low conductance MOSFET is derived from the measurements done on the cascode structure. An open loop gain stage is connected to the cascode structure in case the signal at the internal node of the cascode structure is extremely small to be measured directly and accurately. Impedance measurements can also be done on high impedance MOS devices without noise distortion with the help of the cascode arrangement.

Abstract: The compact CMOS current-mode analog multifunction circuit is based on an implementation using MOSFETs operating in a sub-threshold region and forming two overlapping translinear loops capable of performing multiplication, division, controllable gain current amplifier, current mode differential amplifier, and differential-input single-output current amplifier.

Abstract: A dB-linear voltage-to-current (V/I) converter is amenable to implementation in CMOS technology. In a representative embodiment, the dB-linear V/I converter has a voltage scaler, a current multiplier, and an exponential current converter serially connected to one another. The voltage scaler supplies an input current to the current multiplier based on an input voltage. The current multiplier multiplies the input current and a current proportional to absolute temperature and supplies the resulting current to the exponential current converter. The exponential current converter has a differential MOSFET pair operating in a sub-threshold mode and generating an output current that is proportional to a temperature-independent, exponential function of the input voltage.

Abstract: An inverting amplifier according to a first embodiment includes an inverter circuit, a first voltage generating circuit, and a second voltage generating circuit. The inverter circuit has an input terminal, an output terminal, a first first-conductivity transistor, and a first second-conductivity transistor. The first (second) voltage generating circuit has a first (second) current source, a second first (second)-conductivity transistor, and a third first (second)-conductivity transistor. The first (second) current source supplies a predetermined current. The second first (second)-conductivity transistor has a control terminal with a predetermined bias voltage applied, and two ends connected to the other end of the first first (second)-conductivity transistor and the first (second) current source, respectively.

Abstract: A current generation circuit includes a mirroring circuit suitable for being charged by using a bias voltage, wherein a voltage level of the charged voltage varies corresponding to changes in a voltage level of a power voltage, a comparison circuit suitable for comparing the charged voltage with a feedback voltage, and a current driving circuit suitable for generating a current based on a voltage output from the comparison circuit.

Abstract: The present disclosure discloses an active mixer capable of improving linearity while giving consideration to both gain and noise reduction, including: a voltage-to-current converting circuit operable to generate a conversion signal according to an input signal; a switching circuit operable to carry out a switching action according to a clock signal and thereby electrically connect the voltage-to-current converting circuit with a load circuit; the load circuit operable to provide an output signal for a first and a second output nodes according to the conversion signal through the switching action; a first supplement current source, coupled to a first node between the switching circuit and the first output node, operable to supply a first supplemental current to the switching circuit; and a second supplement current source, coupled to a second node between the switching circuit and the second output node, operable to supply a second supplemental current to the switching circuit.

Abstract: A circuit arrangement (3) is provided for operating at least one low-power lighting unit with a power supply (4) and in particular with a self-oscillating power supply. The circuit arrangement (3) comprises at least an input (12) for receiving an operating voltage (28) from said power supply (4) and an output (11) for connection to one or more low-power lighting units. To allow an efficient operation of said low-power lighting unit with the power supply (4), the circuit (3) comprises a pulse generator (17), connected with said input (12) and adapted to inject at least one trigger pulse (40a, 40b) into said power supply (4) during operation.