Abstract: Apparatus and methods for true power detection are provided herein. In certain embodiments, a power amplifier system includes an antenna, a directional coupler, and a power amplifier electrically connected to the antenna by way of a through line of the directional coupler. The power amplifier system further includes a first switch, a second switch, and a combiner that combines a first coupled signal received from a first end of the directional coupler's coupled line through the first switch and a second coupled signal received from a second end of the directional coupler's coupled line through the second switch.

Abstract: According to one aspect of the present disclosed subject matter, a receiver inductively powered by a transmitter for powering a load, the receiver comprising: a resonance circuit capable of tuning its resonance frequency for coupling with the transmitter and generate AC voltage; a power supply section configured to rectify the AC voltage and adjust a DC current and a DC voltage to the load; and a control and communication section designed to set parameters for the receiver and communicate operation points (OP) to the transmitter, wherein the parameters and the OP derived from determining a minimal power loss of the receiver.

Abstract: Circuit comprising: a first switch (1S) having: a first side (FS) connected to an input node (IN); and a second side (SS); a first capacitor (FC) having: FS connected to SS of 1S; and SS; a second switch having: FS connected to SS of FC; and SS connected to a voltage level node; a third switch having: FS connected to SS of FC; and SS connected to a voltage output node; a fourth switch (4S) having: FS connected to IN; and SS; a second capacitor (SC) having: FS connected to SS of 4S; and SS; a fifth switch having: FS connected to SS of SC; and SS connected to the voltage level node; a sixth switch having: FS connected to SS of SC; and SS connected to the voltage output node; a first connection node connected to FS of FC; and a second connection node connected to FS of SC.

Abstract: A semiconductor transistor device includes a GaN transistor including a drain, a gate, and a source, the GaN transistor having a driving voltage applied across the gate and the source and configured to switch between an on-voltage associated with an on-state of the GaN transistor and an off-voltage associated with an off-state of the GaN transistor. The semiconductor transistor device further includes a variable gate-source resistor connected between the gate and the source and having a variable resistance that varies in response to changes in the driving voltage when switching between the on-state and the off-state of the GaN transistor.

Abstract: A system includes a high side transistor switch coupled to a first voltage node and a low side transistor switch coupled to the high side transistor switch at a switch node. The system further includes a unidirectional decoupling capacitor circuit including a capacitive component. The unidirectional decoupling capacitor circuit is coupled between the first voltage node and a common potential. Responsive to a voltage on the first voltage node being more than a threshold greater than an input voltage to the first voltage node, the unidirectional decoupling capacitor circuit is configured to sink current from the first voltage node to the capacitive component. The capacitive component can therefore be charged, with the charge used to subsequently power a load.

Abstract: A one-way conduction device includes a first transistor and a driving circuit. The driving circuit includes a first circuit, a second circuit and a detection circuit. The first transistor is coupled between an input end and an output end of the one-way conduction device. In the first circuit, a first conduction unit is coupled between the input end of the one-way conduction device and a first resistor. In the second circuit, a second conduction unit is coupled between the output end of the one-way conduction device and a second resistor. In the driving circuit, the detection circuit detects whether a current flows from the first circuit to the second circuit, and accordingly turns on or turns off the first transistor. In this manner, the driving circuit can control the turning on and off of the one-way conduction device.

Abstract: A non-polar rectifying circuit includes two input terminals, two output terminals, two P-channel MOS transistors, and two N-channel MOS transistors. The two input terminals are respectively connected with a drain of one of the two P-channel MOS transistors and a drain of one of the two N-channel MOS transistors. One of the output terminals is electrically connected with the source of two P-channel MOS transistors, and the other output terminal is electrically connected with the source of two N-channel MOS transistors. In application, regardless of the two input terminals which is the positive polarity or negative polarity, one of the output terminals will output high level, and another will also output low level. As a result, it make the power plug no need to divide the positive and negative, which can reduce the installation time of LED lamps, especially for installing a large number of LED lightings.

Abstract: A high-voltage filter for an alternating-current (AC) to direct current (DC) power adapter of the type having a rectifier providing an internal ground and a high voltage DC, the high voltage DC coupled to drive a DC-DC converter providing a power adapter output, the high voltage filter coupled to filter the high voltage DC, has a first capacitor coupled between the high-voltage DC and an intermediate node. A second capacitor is coupled between the intermediate node and the internal ground. A source follower transistor has a drain coupled to the high-voltage and a source coupled to the intermediate node, with gate coupled to a reference supply. In a particular embodiment, the reference supply has a resistor coupled between the high voltage DC and the gate of the source follower, and at least one zener diode coupled between the gate of the source follower and internal ground.

Abstract: The rectifier circuit includes: three terminals A, K, VR; voltage comparator including a positive input terminal, a negative input terminal, and a comparative output terminal; current switching unit including source terminal, drain terminal, and control terminal; first switching unit that conducts or cuts off between source terminal and control terminal of the current switching unit; second switching unit that conducts or cuts off between control terminal of the current switching unit and terminal VR; and reference voltage generator that uses terminal A and terminal VR as input terminals, and includes a voltage output terminal.

Abstract: In general, in one aspect, one or more embodiments relate to a peripheral device that includes a single charging terminal configured to couple to an active electrode driven with an alternating current (AC) signal, a diode for rectifying the AC signal from the active electrode to obtain a rectified signal, and a charging circuitry for charging an energy storage device using the rectified signal and a connection between the peripheral device and free space.

Abstract: A method of measuring blood glucose of a patient is presented here. In accordance with certain embodiments, the method applies a constant voltage potential to a glucose sensor and obtains a constant potential sensor current from the glucose sensor, wherein the constant potential sensor current is generated in response to applying the constant voltage potential to the glucose sensor. The method continues by performing an electrochemical impedance spectroscopy (EIS) procedure for the glucose sensor to obtain EIS output measurements. The method also performs a nonlinear mapping operation on the constant potential sensor current and the EIS output measurements to generate a blood glucose value.

Abstract: For a circuit path to be represented in a timing model, a set of propagating waveforms substantially converges through waveform stabilization to a uniform waveform at a waveform invariant node and all pins following. The circuit path is decomposed at the waveform invariant node into first and second portions, which are characterized as first and second timing arcs. In computing output slew and delay values, the first timing arc generation factors only a single output load of the waveform invariant node, and the second timing arc generation factors only the uniform waveform. Similarly, a setup arc employs the uniform waveform rather than multiple clock input waveforms in computing setup/hold values. Simulation of waveform propagation is also simplified by simulating only the uniform waveform for the second portion. Additionally, the first arc may be shared between a plurality of circuit paths which share an input pin and the waveform invariant node.

Abstract: Measuring device (1; 15) for determining the composition of the liquid phase of a liquid-gas mixture includes a duct (2) defining a flow direction (X) of the mixture parallel to the longitudinal development axis (Y) of the duct (2) and a measuring element (4) arranged in the duct (2) and suited to determine the composition of a liquid layer that flows in contact with the internal surface (3) of the duct (2). The internal surface (3) of the duct (2) includes an intercepting surface (5, 5?) suited to convey part of the liquid layer towards the measuring element (4), arranged so that it is incident on the flow direction (X) and developed according to a conveyance trajectory that has a helical section and whose tangent to the outlet end (7, 7?) intersects the measuring element (4).

Abstract: There is provided a solid-state imaging device including an imaging unit including a plurality of image sensors, and an analog to digital (AD) conversion unit including a plurality of AD converters arranged in a row direction, each AD converter performing AD conversion of an electrical signal output by the image sensor. Each of the AD converters includes a comparator having a differential pair at an input stage, the differential pair including a first transistor and a second transistor, the first and second transistors are each divided into an equal number of a plurality of division transistors, and an arrangement pattern of the plurality of division transistors constituting the comparator in a predetermined column and an arrangement pattern of the plurality of division transistors constituting the comparator in an adjacent column adjacent to the predetermined column are different from each other.

Abstract: An FET RF signal detector circuit comprising two unbalanced differential transistor pair circuits is disclosed. A current mirror output circuit is included for generating an output current derived from currents flowing in the differential transistor pair circuits. The first unbalanced differential transistor pair circuit comprises two branches, each with a respective tail, and a first variable resistor between the branch tails. The first unbalanced differential transistor pair circuit connects to a first current source tail arrangement. The second unbalanced differential transistor pair circuit comprises two branches, each with a respective tail, and a second variable resistor between the branch tails. The second unbalanced differential transistor pair circuit connects to a second current source tail arrangement.

Abstract: A method for operating a circuit includes providing a three terminal main transistor and a four terminal sense transistor having a field plate. The method includes simultaneously applying a gate pulse on a gate terminal of the sense transistor and a gate terminal of the main transistor, and applying a field plate pulse on a field plate of the sense transistor. The field plate pulse is synchronous and in phase with the gate pulse.

Abstract: An active diode driver for operating a switch of an active rectifier using an active diode is provided. The active diode driver may first control a soft turn-on of the switch and secondly control a hard turn-on of the switch, thereby making it possible for the switch to be softly turned-on.

Abstract: An active diode that features improved control of transistor turn-off is provided. Such an active diode may include a comparator to compare voltages between opposite ends of a parasitic diode, and a gate driver to control a gate terminal of the transistor according to the comparison result of the comparator. Furthermore, the active diode may further include an off-timing controller to control the transistor to be turned off at a point in time when voltages of the opposite ends of the parasitic diode turn positive. Thus, the active diode may be turned off when required.

Abstract: A semiconductor device comprising a rectifier circuit, wherein the rectifier circuit includes first and second input wires to which AC signals whose phases are inverted from each other are transmitted; a first transistor of a first conductive type which has a first power wire connected with a first transistor terminal and a gate connected with the first input wire; a second transistor of the first conductive type which has the first power wire connected with a first transistor terminal, and a gate connected with the second input wire; a third transistor of a second conductive type which has a second power wire connected with a first transistor terminal, a second transistor terminal connected with a second transistor terminal of the first transistor and a gate connected with the first input capacitor; and a fourth transistor of the second conductive type which has the second power wire connected with a first transistor terminal.

Abstract: A first and second hybrid envelope detector and full-wave rectifier is provided. The first hybrid envelope detector and full-wave rectifier includes a first P-channel Field Effect Transistor (PFET); a second PFET; a first N-channel Field Effect Transistor (NFET); a second NFET; a third NFET; a fourth NFET; a fifth NFET; a controller; a variable transistor; and a variable capacitor. The second hybrid envelope detector and full-wave rectifier includes a first N-channel Field Effect Transistor (NFET); a second NFET; a first P-channel Field Effect Transistor (PFET); a second PFET; a third PFET; a fourth PFET; a fifth PFET; a controller; a variable transistor; and a variable capacitor.

Abstract: An integration circuit according to one embodiment includes a first capacitance element, a capacitance circuit, a comparison circuit, a memory circuit and an operation circuit. The first capacitance element receives a current signal. The capacitance circuit includes a first switch and a second capacitance element, and is connected in parallel to the first capacitance element. The second capacitance element receives a current signal via the first switch. The comparison circuit compares a voltage of the first capacitance element with a reference voltage to obtain a comparison result. The memory circuit stores the comparison result, and opens or closes the first switch based on the comparison result. The operation circuit outputs a residual signal based on a difference between the integrated value obtained by the first capacitance element and the second capacitance element and a value based on the comparison result.

Abstract: An apparatus comprises at least one transmit amplifier and rectification circuitry located in the at least one transmit amplifier, which is configured to receive a RF signal and provide a rectified voltage, which is selectably added to a voltage supplied by a battery to generate a DC voltage supply signal that is a function of RF power level. A controller is configured to select between providing the VBAT or the VSupply signal to a transmit switch depending on one or more of a logic state and a mode of operation. An alternate apparatus comprises a charge pump circuit configured to quickly raise a voltage supplied to it and store the output voltage on a capacitor and then either shift a first frequency provided by a charge pump oscillator to a lower second frequency or turn off a charge pump clock to maintain a voltage on the capacitor during a transmit mode.

Abstract: Various active diode circuits are described. In one example, there is provided an active diode circuit having an active diode and a control circuit. The active diode includes an anode terminal, a cathode terminal and a control terminal. The control circuit is configured to generate a control current of the active diode on the control terminal proportional to the diode current of the active diode. The control circuit is also configured to control the diode voltage of the active diode below a predetermined threshold.

Abstract: A detector circuit, has a first diode, to an anode of which an AC signal is input and to which a constant voltage is supplied, a second diode, to an anode of which the constant voltage is supplied, and a difference current generation circuit, which generates the difference current between a first current flowing in the first diode and a second current flowing in the second diode.

Abstract: A detector circuit, has a first diode, to an anode of which an AC signal is input and to which a constant voltage is supplied, a second diode, to an anode of which the constant voltage is supplied, and a difference current generation circuit, which generates the difference current between a first current flowing in the first diode and a second current flowing in the second diode.

Abstract: A circuit is configured to receive an input signal and to produce an output signal measuring a power of the input signal. The circuit includes a multiplier cell configured to multiply first and second signals, where each of the first and second signals includes a component related to the input signal and a component related to the output signal. The circuit also includes a controlled amplifier configured to amplify an intermediate signal produced by the multiplier cell, where an amplification provided by the controlled amplifier is a function of the output signal. The circuit could further include at least one first converting amplifier configured to generate the component related to the input signal and at least one second converting amplifier configured to generate the component related to the output signal. Transconductances of the converting amplifiers could be selected to configure the circuit as a linear or logarithmic RMS power detector.

Abstract: A time-domain voltage comparator for an analog-to-digital converter includes a first voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; a second voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; and a phase comparator configured to determine a difference between times outputted from the first voltage-to-time converter and the second voltage-to-time converter.

Abstract: A physical vapor deposition system may include an RF generator configured to supply a pulsing AC process signal to a target in a physical vapor deposition chamber via the RF matching network. A detector circuit may be coupled to the RF generator and configured to sense the pulsing AC process signal and to produce a corresponding pulsing AC voltage magnitude signal and pulsing AC current magnitude signal. An envelope circuit may be electrically coupled to the detector circuit and configured to receive the pulsing AC voltage and current magnitude signals and to produce a DC voltage envelope signal and a DC current envelope signal. A controller may be electrically coupled to the envelope circuit and the RF matching network and configured to receive the DC voltage and current envelope signals and to vary an impedance of the RF matching network in response to the DC voltage and current envelope signals.

Abstract: In response to turning-on of a lock-type power switch, an initial controller outputs a first voltage for a first period and a gate is turned on for the period via a first driver responsive to the first voltage, then DC power is supplied to a main circuit. During the period, a control processor causes a voltage output section to start outputting a second voltage so that the gate is turned on via a second driver to continue the DC power supply. When no event has been generated for a second period, the second voltage from the voltage output section is stopped to turn off the gate, thus the power supply to the main circuit is shut off. Once a power from outside is switched from OFF to ON while the power switch kept ON, the power supply to the main circuit is resumed via the controller and first driver.

Abstract: The present invention introduces a diode circuit which achieves ideal diode characteristics which observe an enough reverse breakdown voltage, and whose forward voltage is nearly 0 V. An active diode has an anode terminal and a cathode terminal. The active diode includes a transistor which has a gate terminal, a drain terminal connected to one of the anode terminal and the cathode terminal, and a source terminal connected to the other one of the anode terminal or the cathode terminal; and a gate voltage generating circuit which delivers a gate voltage to the gate terminal, the gate voltage being adjusted to be equal to a threshold voltage of the transistor.

Abstract: Embodiments of a potential converter circuit include a converter for converting a bipolar input signal to a unipolar output signal that only consumes current at a change of potential of the input signal.

Abstract: A data driver including a first digital-to-analog converter configured to select first and second reference voltages depending on upper bits of data and supply the first and the second reference voltages to a first line and a second line, respectively, a second digital-to-analog converter having the first line and the second line to receive the first and the second reference voltages, respectively, a first group of voltage dividing resistors between the first line and the second line and configured to generate a plurality of gray scale voltages, a voltage dividing resistor unit between the first line and the second line, and at least one switch positioned between the voltage dividing resistor unit and one of the first line and the second line, and including a decoder unit configured to control on and off state of the at least one switch depending on lower bits of data.

Abstract: A detection circuit includes a current source with no temperature coefficient; a current generation circuit that generates a VBE proportional reference current from the current source with no temperature coefficient; a current mirror circuit that returns an output current of the current generation circuit; a reference voltage generation circuit that generates a VBE proportional voltage with a negative temperature coefficient on the basis of the current returned by the current mirror circuit so that the VBE proportional voltage is used as a reference voltage of a comparator; and a full-wave rectifying means, having a differential pair and a rectifier circuit, using the current source with no temperature coefficient, having an alternating current signal supplied as an input signal, for generating a direct current voltage with a negative coefficient on the basis of a voltage obtained by full-wave rectifying the alternating current signal, and for using the generated voltage as a comparative voltage of the compar

Abstract: An implantable sensor includes electronic circuitry for automatically performing on a periodic basis, e.g., every 1 to 24 hours, specified integrity tests which verify proper operation of the sensor.

Abstract: A half-wave rectifier including an input port for receiving an incoming AC signal, an output port for outputting a half-wave rectified signal, an operational amplifier including inverting and non-inverting input terminals and an output terminal, the inverting input terminal connected to a ground reference and a non-inverting input terminal coupled to a negative feedback loop and a first resistor. The negative feedback loop including a second resistor coupled between a first node and a second node, the first node coupling the output terminal and the output port and the second node coupling the non-inverting input terminal and the second resistor. A capacitor is coupled to the input port and in series with the first resistor.

Abstract: A Bluetooth® enhanced data rate receiver (1) has a DC offset estimation circuit (9) comprising a detector (10) for identifying turning points in a demodulated signal and measuring the signal level at these turning points. The detector (10) discards measured levels of maxima that are not sufficiently different to a level of a preceding minimum and levels of minima that are not sufficiently different to a level of a preceding maximum. The detector (10) also discards levels that are smaller than certain thresholds. An averaging means (11) calculates the average of each adjacent maximum and minimum levels of the signal output by the detector (10). A processing means (12) selects a high, low and medium value of the calculated averages and estimates a DC offset value as the average of this set of calculated averages.

Abstract: A precision voltage rectifier comprises a source voltage input and a voltage reference. The rectifier comprises switching elements that, according to the sign of the source signal, change the connections to the inputs of a differential difference amplifier that is connected as a voltage inverter. Embodiments of the invention are fully-integrated and CMOS compatible with high-input impedance such that the invention can be operated in low-power situations. A preferred application involves the integration of several similar circuits in a high-density, low-power implantable medical device. Particular embodiments of the invention can be used to rectify nerve signals collected by electrodes for use in a system for manipulating a prosthetic device.

Abstract: Hot swappable pulse width modulation power supply circuits preferably realized in integrated circuit form. The hot swap circuits provide for de-bouncing, controlled charging of the input capacitor of the power supply circuit and soft-start of the pulse width modulator after charging the input capacitor. Other features include a low voltage lockout, and an output for coupling to a synchronous rectifier driver to synchronize synchronous rectifiers on the secondary side of a coupling transformer in isolated systems. The hot swap capability may be disabled through an enable pin, or not implemented by not connecting the integrated circuit in a manner to use the hot swap capability.

Abstract: A reference ladder is configured to have improved feedback stability. The reference ladder includes a resistor ladder having a plurality of taps that produce a plurality of reference voltages. The resistor ladder is driven by a first current source at a first tap of the plurality of taps and by a second current source at a second tap of the plurality of taps. A first feedback network senses a voltage at the first tap and controls the first current source based on the first sensed voltage. A second feedback network senses a voltage at the second tap and controls the second current source based on the second sensed voltage. The first and second taps each operate as both a force tap and a sense tap of the resistor ladder. Differential input stages that are connected to the plurality of taps are at least partially isolated from the feedback networks by converging the force and sense taps, thereby improving the stability of the feedback networks.

Abstract: An apparatus and a method to control an output signal from a DAC-driven amplifier-based driver are disclosed. The apparatus includes an amplifier and a driver. The amplifier has a negative input terminal, a positive input terminal, and a first output terminal. The driver has an input terminal and a second output terminal, the input terminal coupled to the first output terminal of the amplifier and the second output terminal coupled to the positive input terminal of the amplifier to provide a positive feedback to the amplifier.

Abstract: A label printer-cutter includes a frame and a print head assembly connected to the frame. The print head assembly includes a print head for printing to a label media. The label printer-cutter includes a cutting assembly connected to the frame, and the cutting assembly is for catting the label media. The printer-cutter also includes a controller in operative association with the print head assembly and cutting assembly. The controller can be programmed to control the print head assembly and the cutting assembly such that printing to and cutting of the label media does not occur simultaneously in the label printer-cutter. Printing by the print head is controlled to correspond to cutting assembly rollers being positioned in a non-cutting position. Advantageously, printing to and cutting of a label media in a single label printer-cutter unit is accomplished in an efficient and cost-effective manner.

Abstract: A temperature stable, integrated circuit full wave level detector incorporating a single stage operational amplifier design which does not require, as in prior art implementations, two operational amplifiers to perform a full wave rectification function on an input alternating current (“AC”) signal followed by a comparator to detect the resultant signal level. The full wave level detector of the present invention utilizes but a single amplifier and some additional peripheral components resulting in a saving in on-chip die area in an integrated circuit (“IC”) implementation while also exhibiting excellent temperature stability characteristics.

Abstract: An RMS-DC converter generates a series of progressively amplified signal pairs which are then multiplied and weighted in such a way as to cancel uncorrelated noise while still providing true square-law response. The converter includes two series of gain stages for generating the amplified signal pairs, and a series of four-quadrant multipliers for multiplying and weighting the amplified signal pairs in response to a series of weighting signals. The outputs from the multipliers are summed and averaged, and a final output signal is generated by integrating the difference between the averaged signal and a reference signal. To preserve the square-law response over a wide range of input voltages, the system is servoed by feeding the final output signal back to an interpolator which generates the weighting signals as a series of continuously interpolated, overlapping, Gaussian-shaped current pulses having a centroid that moves along the length of the interpolator as the final output signal varies.

Abstract: The present invention relates to a weighted mean calculation circuit that comprises an inverting amplifier; a plurality of capacitors C1 through Cn connected to the input terminal thereof; switches SW1 through SWn that connect the capacitors C1 through Cn to the input and output terminals of the inverting amplifier; and a switch SW0 that is provided between the input and output of the inverting amplifier. A signal voltage is applied to respective capacitors while making the SW0 conductive when inputting a signal, and the capacitors C1 through Cn are connected in parallel between the input and output of the inverting amplifier while making the SW0 non-conductive when outputting a signal, whereby an output signal Vout is read, and a weighted mean value output that does not include any offset and is normalized as a normal polarity output can be obtained.

Abstract: A diode detection circuit is capable of obtaining an ideal rectification voltage even the case of a minute input high-frequency voltage. The circuit includes a first diode that accepts an AC signal; a first parallel circuit consisting of a resistor and a capacitor, the first parallel circuit accepting a detection output from the first diode; a first operational amplifier having a positive input terminal that accepts a charging voltage for the capacitor of the first parallel circuit; a second diode that accepts an output from the first operational amplifier; a first switching circuit consisting of a first switch and an oscillator, the first switching circuit providing a control of the ratio of conduction to non-conduction of the first and second diodes; a second parallel circuit consisting of a resistor and a capacitor, the second parallel circuit accepting an output from the first switching circuit.

Abstract: An implantable sensor includes electronic circuitry for automatically performing on a periodic basis, e.g., every 1 to 24 hours, specified integrity tests which verify proper operation of the sensor.

Abstract: A circuit includes an analog-to-digital (A/D) converter for multiplexing between a number of analog input signals and converting the selected analog input signals to a digital code representation. The A/D converter includes a comparator having a first input terminal connected to receive the first signal having a number of levels, a second input terminal connected to receive a multiple number of analog input signals, and a third input terminal for receiving a multiple number of input select signals. The comparator includes a multiplexer coupling the multiple number of analog input signals to a multiple number of corresponding input signal paths. The multiplexer selects one of the multiple number of input signal paths based on the multiple number of input select signals. In one embodiment, the A/D converter is applied in a digital image sensor for performing pixel-level analog-to-digital conversion using a multi-channel bit serial ADC technique.

Abstract: A current level detector device for protecting a circuit against alternating current overcurrents includes resistor arrangements that are inserted into the circuit to be protected and two detector cells, one for each half-wave of the current. The detector cells are similar to each other and are connected to the terminals of the resistor arrangements. By means of a crossover circuit, the two detector cells are both connected to the terminals of the same resistor arrangements. Applications include protecting circuits using power semiconductors.

Abstract: A read channel circuit includes a digital partition and a analog portion coupled by an ADC. This digital portion and the analog portion are on different chips and the analog portion is positioned on the flex.

Abstract: The present invention provides a detector comprising a microstrip line having one end being grounded and another end connected to a main transmission line, a detection diode connected to the microstrip line, and a smoothing circuit for smoothing a signal detected by the detection diode.