Abstract: A circuit includes an analog-to-digital (A/D) converter for multiplexing between a number of analog input signals and converting the selected analog input signals to a digital code representation. The A/D converter includes a comparator having a first input terminal connected to receive the first signal having a number of levels, a second input terminal connected to receive a multiple number of analog input signals, and a third input terminal for receiving a multiple number of input select signals. The comparator includes a multiplexer coupling the multiple number of analog input signals to a multiple number of corresponding input signal paths. The multiplexer selects one of the multiple number of input signal paths based on the multiple number of input select signals. In one embodiment, the A/D converter is applied in a digital image sensor for performing pixel-level analog-to-digital conversion using a multi-channel bit serial ADC technique.

Abstract: A current level detector device for protecting a circuit against alternating current overcurrents includes resistor arrangements that are inserted into the circuit to be protected and two detector cells, one for each half-wave of the current. The detector cells are similar to each other and are connected to the terminals of the resistor arrangements. By means of a crossover circuit, the two detector cells are both connected to the terminals of the same resistor arrangements. Applications include protecting circuits using power semiconductors.

Abstract: A read channel circuit includes a digital partition and a analog portion coupled by an ADC. This digital portion and the analog portion are on different chips and the analog portion is positioned on the flex.

Abstract: The present invention provides a detector comprising a microstrip line having one end being grounded and another end connected to a main transmission line, a detection diode connected to the microstrip line, and a smoothing circuit for smoothing a signal detected by the detection diode.

Abstract: A low power switched rectifier circuit is realized using P-MOS and N-MOS FET switches that are turned ON/OFF at just the right time by a detector and inverter circuit (which form an integral part of the rectifier circuit) to rectify an incoming ac signal in a highly efficient manner. Parasitic diodes and transistors that form an integral part of the FET circuitry respond to and rectify the incoming signal during start up, i.e., when no supply voltage is yet present, thereby providing sufficient operating voltage for the FET switches to begin to perform their intended rectifying function. In the absence of an incoming ac signal, i.e., during the time between biphasic pulses, the rectifier circuit is biased with an extremely small static bias current; but in the presence of an incoming ac signal, at a time when the positive and negative phases of the incoming signal are to be connected to positive and negative supply lines, a much larger dynamic bias current is automatically triggered.

Abstract: A control circuit for distributed electrical equipment includes a relaxation oscillator configured for voltage to frequency conversion whereby the output frequency is proportional to the input voltage signal. An opto-coupler provides voltage isolation to the circuit and a standard 8-bit counter translates the frequency signals to a low voltage count data.

Abstract: A signal-processing arrangement includes a conversion circuit CONV which converts an input signal Sin into sub-ranging signals Sc(1)..Sc(N) corresponding to different amplitude sub-ranges of the input signal Sin. Each sub-range signal is supplied to a respective one of an array of sampling circuits SC(1)..SC(N) which supplies successive samples thereof to a processing circuit PROC for processing in accordance with operations which may constitute or include A/D conversion. Such an arrangement is particularly suitable for use in a television receiver, multimedia or other video image display apparatus, and various types of disc-players and tape-recorders.

Abstract: A full-wave rectifier circuit (70) includes a first transistor (N1) and a second transistor (N2) in combination to form a first transistor pair (N1 and N2) for minimizing the voltage drop between ground (88) and the transponder substrates. A third transistor (P1) and a fourth transistor (P2) operate in combination to form a second transistor pair (P1 and P2) for minimizing the voltage drop between the alternating current peak voltage (118 and 120) and the output voltage (V.sub.DD) of the full-wave rectifier (70). The first transistor pair (N1 and N2) and second transistor pair (P1 and P2) are controlled by alternating current voltage input signals (118 and 120). A series regulator circuit (70) decouples the first transistor pair (N1 and N2) and the second transistor pair (P1 and P2) from capacitive loads (C1 and C2) of the full-duplex transponder circuitry (14).

Abstract: An input expansion for a crosspoint switch module incorporates a plurality of crosspoint switch ICs within the switch module so that the crosspoint switch module may receive a plurality of input differential signals. The crosspoint switch module includes a module driver circuit which, when enabled by a module enable signal, couples a differential current signal to an output. Each crosspoint switch includes an emitter follower configured transistor circuit for receiving one of the input differential signals and providing an output differential signal and a switch transistor circuit configured as a saturated switch for receiving the output differential signal and providing the differential current signal when enabled by a switch enable signal. Only one of the crosspoint switches is enabled at a time so that only one of the crosspoint switches carries current.

Abstract: An integrated circuit arrangement with a diode characteristic including a source-drain section of a first transistor arranged in the current path between the input and output sides of the arrangement; a first inverter stage with an output fed back to its input, and whose supply voltage is provided by the voltage on the output side of the circuit arrangement; a second inverter stage to the input of which the output signal from the first inverter stage is fed and whose supply voltage is provided by the voltage on the input side of the circuit arrangement; and a third inverter stage having an input to which the output signal from the second inverter stage is fed, whose voltage supply is provided by the voltage on the output side of the circuit arrangement, and whose output signal is fed to the gate electrode of the first transistor, and thus regulates the current flow in the current path of the circuit arrangement.

Abstract: The switch of this invention has two conduction terminals and basically consists of the parallel coupling, across the two conduction terminals, of a first N-channel MOS transistor and second P-channel MOS transistor. The first MOS transistor will be conducting when the signal applied to the conduction terminals has a first polarity, and the second MOS transistor will be conducting when the signal applied to the conduction terminals has a second polarity. Advantageously, if two unidirectional conduction circuit elements are respectively connected in series with the main conduction paths of the two MOS transistors, the drain/body junctions of the latter will never be conducting regardless of the way the switch is connected.

Abstract: A method and apparatus are provided for sensing a common mode signal of a differential circuit. A first full wave rectifier samples the differential signal and generates a first rectified signal. A second full wave rectifier samples the differential signal and generates a second rectified signal. An averaging circuit coupled to the first and second full wave rectifiers averages the first and second rectified signals and generates the common mode signal.

Abstract: An inputted signal applied to an input terminal of a detecting circuit is rectified in a positive amplitude range thereof by a rectifier block and stored in a capacitor. In a negative amplitude range, the electric energy stored in the capacitor is discharged through a load block. The rectifier block and the load block have equal impedances, and hence a time constant when the capacitor is charged is equal to a time constant when the capacitor is discharged. A DC signal outputted from an output terminal of the detecting circuit has a level which is the same as the average power level of the inputted signal. The detecting circuit is capable of outputting a DC signal which is accurately representative of the power level of the inputted signal.

Abstract: A method of designing improved CMOS input circuits by understanding and selecting appropriate drive strength for a CMOS output from a previous stage. The method involves modeling the net using HSPICE and including a transit time term to accurately model charge storage, then size drivers as needed to keep the V.sub.ss clamps out of forward conduction. Excessive ringing can cause data errors in the input stage if unterminated, falling edge transitions in such a net can turn on a receiver's V.sub.ss clamp diode (stored charge in the V.sub.ss clamp diode combined with the line's inductance and the receiver's capacitance form an energized resonant circuit which can release energy at a time to cause a data glitch). Currently, XNS simulation miscalculates the ring amplitude by a factor of three. Driver scaling and termination can eliminate the problem by keeping the receiver's V.sub.ss clamp out of forward conduction. Driver sizing can control the problem.

Abstract: AC to DC signal conversion for use in applications including conditioning of signals supplied by inductive position sensors that are employed in aircraft electrical and electronic systems. First and second switching circuits (14 and 16) are synchronously switched between operational states in which an applied AC signal is supplied to the switching circuits and a second operational state in which the switching circuits supply charge (current). When one switching circuit (e.g., 14) is in the first operational state, the second switching circuit (e.g., 16) is in the second operational state so that one switching circuit senses the AC signal during positive half cycles and the other switching circuit senses the AC signal during negative half cycles. A pair of capacitors (18 and 20) are connected between a pair of output terminals.

Abstract: A highly efficient compact multiple output voltage generation circuit is designed for use in integrated circuit devices such as DRAMs which require multiple internal voltage supplies for optimum performance. An oscillator is connected to a primary coil of a microtransformer. The microtransformer secondary coil has multiple taps one of which is connected to ground. A second transformer tap is connected to a transformer output node. The oscillating transformer output signal is capacitively coupled to a voltage rectifier. The input to the rectifier is biased to one diode drop below Vcc. The output of the rectifier is an internal supply voltage greater than ground. Another transformer tap is connected to a negative oscillation output node. The negative oscillating signal is rectified to produce a negative internal supply voltage. The voltage generation circuit operates effectively at low Vcc input levels where capacitor based voltage pumps often fail. The circuit is compatible with CMOS manufacturing processes.

Abstract: Herein disclosed are a mean value detecting apparatus and a mean value detecting integrated circuit, having a mean value detecting unit formed with a resistance and a capacitance for detecting a mean value of an input signal, and an offset voltage adjusting unit connected in parallel to the mean value detecting unit at a connecting point of the resistance and a capacitance of the mean value detecting unit. With the above arrangement, this invention allows a large reduction of a size of the circuit.

Abstract: An absolute value circuit according to the present invention has a configuration wherein a switch is connected directly to an output of an amplifier and an output terminal. Owing to this configuration, the absolute value circuit can be realized which is capable of providing full-wave rectification with less distortion.

Abstract: A balanced current amplifier mirrors either a fully differential or single ended input signal into common output circuits in a manner to generate a fully differential output signal without any d.c. bias. Input signal nodes are maintained at a desired voltage by circuit elements other than those of the current mirror circuits, thus freeing the current mirroring elements from having to be sized for this purpose. The sizes of the output transistors are adjustable in order to set the gain of the circuit. In addition to amplifier circuits, a full-wave rectifier, a comparator, and a filter, all operating with current signals, are described. A single circuit module may include all of these circuits with a user provided the capability to program the module to perform any one or more of these functions.

Abstract: A serial-type A/D converter uses magnitude amplifiers("magamps") and comparators for effecting the conversion of analog signals to Gray scale code signals that are then converted to binary digital signals by a Gray scale code-to-binary portion of the serial-type A/D converter. More specifically, a serial-type A/D converter uses an n-bit converter that has n-1 magamps and n-comparators. The n-1 magamps are cascaded such that the V.sub.OL and V.sub.OH outputs of a stage are the inputs to the next stage. The output of the comparators are input to the Gray scale code-to-binary portion of the serial A/D converter. The latching of the comparators occurs outside of the magamps. This allows for the parallel latching of the n comparators. The speed of the serial-type A/D converter is determined by the bandwidth of the magamps. The serial-type A/D converter includes an offset method that significantly reduces the effects of early voltage, V.sub.A, on the output waveforms.

Abstract: A microwave monolithic integrated circuit (MMIC) RF-generated bias circuit and method includes an input for receiving an RF signal. A rectifier coupled to the input and to electrical ground produces a rectified RF signal in response. A voltage divider coupled to the rectifier and to the electrical ground receives the rectified RF signal and produces a DC voltage therefrom. An output is coupled to the voltage divider for applying the DC voltage to a MMIC field effect transistor (FET) for biasing. No separate bias battery is required, and efficiency is optimized because the generated bias voltage increases to the point where the amplifier voltage begins to decrease, which in turn reduces the generated bias voltage. The derived bias voltage may be used to control other circuits (e.g., other amplifiers, oscillators, mixers, etc.) which require detection of RF presence.

Abstract: An impedance-steerable circuit for an industrial phase controller inserts precise steerable trigger pulses in the sine and cosine excursions of a sine wave of high-energy capacitive and related discharge systems. Multiple pulses and Barkhausen effects are eliminated. The controller can lock capacitive discharge systems into precise phase or, in extended embodiments, serve as a power controller for radar systems, laser systems, and beam weapons. Thyristors and thyratrons provide steered elements (pulses) activated in a pulse-feedback mode.

Abstract: A common dictionary definition of a "diode" is "any electronic device that restricts current flow chiefly to one direction." This definition covers not only the conventional two lead PN junction semiconductor device presently known in the prior art (referred to herein as a "conventional diode") but also the electronic device of this invention (referred to herein as a "low power diode"). A low power diode has a comparator for comparing the voltage present at the anode and cathode of the diode. When the comparator determines that the voltage present at the anode of the low power diode equals or exceeds the voltage present at the cathode of the low power diode by a predetermined forward voltage, a signal is generated. This signal turns on a transistor acting as a switch, which in turn electronically connects the anode and the cathode of the low power diode together. Unlike conventional diodes that have a forward voltage (dependent on the physical silicon junction property of the diode) of approximately 0.

Abstract: A full wave rectifier includes an amplifier having a minus input, a plus input and an amplifier output; an input resistor connected between a circuit input and the minus input; and a current bridge having an output terminal connected to the circuit output, a first terminal connected to the minus input and a second terminal connected to the amplifier output. The current bridge includes a first current mirror circuit and a second current mirror circuit. The first current mirror circuit includes a first current source and a second current source, a source end of each current source of the first and second current sources being connected to the first terminal, a drain end of the first current source being connected to the second terminal and a drain end of the second current source being connected to the output terminal.

Abstract: Peak and valley voltages of signals from at least two analog sensors are held by the circuit. A plurality of threshold voltages is generated from the previous peak and valley voltages of the respective analog sensors. The signal of each sensor is compared to the respective threshold voltages to produce a sequences of output transitions for each sensor. The output transitions are combined such that each sequence of output transitions from each analog sensor occurs between sequences of the other analog sensor (or sensors). An optional peak and valley reset is also disclosed.

Abstract: A signal isolation apparatus has a first transformer with a primary winding tap receiving an input signal and another primary winding tap receiving a first oscillating signal. A second transformer has a primary winding tap receiving the input signal and another primary winding tap receiving a second oscillating signal. The second oscillating signal is out of phase (typically 180 degrees out of phase) with the first oscillating signal. A rectifier electrically connected between a first secondary winding tap of the first transformer and a first secondary winding tap of the second transformer has a high output terminal and a low output terminal, the low output terminal being referenced to a second secondary winding of the first and second transformers. A signal across the high and low output terminals is an output signal galvanically isolated from the input signal with the same electrical characteristics as the input signal.

Abstract: A squaring amplifier circuit (300) generates a substantially rectangular output signal from an a.c. input signal. An amplifier stage (303) is biased at a low quiescent current by a current source network (305) and a coupling network (306). Since the amplifier stage (303) current is a non-linear function of its input voltage, application of a low-level a.c. input signal (313), through an input signal coupling network (302), results in a substantially rectangular output signal having frequency and duty cycle that are substantially identical to the frequency and duty cycle of the input signal.

Abstract: The present invention is directed to a full wave rectifying circuit where a single input a.c. signal is used to perform full wave rectification with enhanced accuracy. An a.c. signal is transmitted from an a.c. signal source (1) via a coupling capacitor (3) to bases of transistors (Q1, Q4) of first and second differential gain stages (S1, S2). Outputs from the first and second differential gain stages (S1, S2) are received on input terminals of first and second current mirror circuits (K1, K2). Output currents (I.sub.011, I.sub.012) from the first and second current mirror circuits (K1, K2) are converted by load resistances working as current-voltage converting means, and then, output voltage V.sub.OUT1 rectified on the full wave basis is output from an output terminal (12). Portions of the a.c. signal out of phase from each other are rectified on the half wave basis by the first and second differential gain stages (S1, S2) and then they are added, so that a single input a.c.

Abstract: A clipper includes an amplifier having a non-inverting input node, an inverting input node, and an output node. A feedback transistor has its base connected to the amplifier output node and its emitter connected to the inverting input node for providing unilaterally conductive degenerative current feedback between the output node and the inverting input node. A resistor is connected between the inverting input node and an input terminal for conducting a current supplied via the collector-to-emitter path of the feedback transistor which is proportional to the amplitude of an unclipped portion of the signal applied between the input terminal and the non-inverting input node. When a reference potential is applied to the non-inverting input node and an AC input signal varying about the reference potential is applied to the input terminal, the stage functions as a negative half-wave rectifier.

Abstract: An absolute value circuit for analog type processing combines an analog inverter circuit and a maximum circuit. The inverter circuit uses an operational amplifier comprised of CMOS inverters which are connected in a cascade with a gain of 1. The maximum circuit includes a pair of nMOS transistors, the source follower outputs of which are connected to a common output.

Abstract: A clipper includes an amplifier having a non-inverting input node, an inverting input node, and an output node. A feedback transistor has its base connected to the amplifier output node and its collector connected to the non-inverting input node for providing unilaterally conductive degenerative current feedback between the output node and the non-inverting input node. A resistor is connected between the non-inverting input node and an input terminal for conducting a current supplied via the collector-to-emitter path of the feedback transistor which is proportional to the amplitude of an unclipped portion of the signal applied between the input terminal and the inverting input node. When a reference potential is applied to the inverting input node and an AC input signal varying about the reference potential is applied to the input terminal, the stage functions as a negative half-wave rectifier.