Abstract: An injection locked frequency divider and a PLL circuit, having a wide operating frequency bandwidth and capable of reducing the influence of any parasitic capacitance, are provided. Injection locked frequency divider (100) includes ring oscillator 140 that cascade-connects first amplifier circuit (141) including N-channel MOS transistor (111) and P-channel MOS transistor (112), and second amplifier circuit 142 and third amplifier circuit (143) that have the same configuration as first amplifier circuit (141) in three stages in a ring; N-channel MOS transistor 150 in which the sources of N-channel MOS transistors (111, 121, 131) in the respective stages are connected to the drain thereof; and differential signal injection circuit (160) that injects injection signal I1 to the gates of P-channel MOS transistors (112, 122, 132) in the respective stages and injects a reverse phase signal of injection signal I1 as a differential signal to the gate of N-channel MOS transistor (150).

Abstract: An apparatus for dividing a frequency by 1.5 to produce a quadrature signal is disclosed. The apparatus includes a divider that receives a differential input signal with a first frequency and two phases and creates a six-phase signal at a second frequency. The second frequency is the first frequency divided by 3. The apparatus also includes precision phase rotation circuitry that receives the six-phase signal and produces an eight-phase signal. The apparatus also includes a doubler that receives the eight-phase signal and produces a quadrature signal. The quadrature signal has a third frequency that is the first frequency divided by 1.5.

Abstract: The invention pertains to a latch circuit comprising a sensing arrangement with one or more sensing transistors adapted to sense an input signal and to provide a first signal based on the sensed input signal, and a sensing arrangement switch device connected or connectable to a first current source, the sensing arrangement switch device being adapted to switch on or off a current to the one or more sensing transistors based on a first clock signal.

Abstract: A divider has a clock generation circuit which combines a first trigger clock and a second trigger clock having a first phase difference, so as to generate a third clock having pulse edges corresponding to pulse edges of the first trigger clock and the second trigger clock; an output dividing circuit which divides the frequency of the third clock in half so as to generate a first differential output clock and a second differential output clock having a duty ratio corresponding to the first phase difference; and a phase correction circuit which detects a phase of the first output clock or the second output clock at a timing of the pulse edge of the first trigger clock or the second trigger clock, so as to generate a phase correction signal for resetting the output dividing circuit when the detected phase is not a normal phase.

Abstract: An injection-locked frequency divider (ILFD) including a signal injector, an oscillator (OSC), and a buffer stage is provided. The signal injector is configured for receiving an injection signal. The OSC is configured for dividing the frequency of the injection signal, so as to generate a first divided frequency signal, where there is an integral-multiple relation between the frequency of the first divided frequency signal and that of the injection signal. The buffer stage is configured for receiving and boosting the first divided frequency signal, and performing a push-push process on the first divided frequency signal, so as to output a second divided frequency signal, where there is a fractional-multiple relation between the frequency of the second divided frequency signal and that of the injection signal.

Abstract: An apparatus includes an injection locking frequency divider, which includes a first resonant tank that has a first resonance frequency and a common mode path that includes a second resonant tank, and has a second resonance frequency that is a harmonic of the first resonance frequency. The second resonant tank is adapted to receive a first signal having an oscillation frequency near the harmonic of the first resonance frequency to cause the first resonant tank to provide a second signal that is locked to the first signal.

Abstract: A low-voltage high-speed frequency divider substantially reduces the power required to generate a half-rate in-phase clock signal and a half-rate quadrature-phase clock signal by reducing the number of pairs of transistors that respond to a full-rate clock signal and a full-rate inverse clock signal.

Abstract: An injection-locked frequency divider is provided and which includes an injection transistor, an oscillator, a current source and a transformer. The injection transistor is used to receive an injection signal. The oscillator is used to divide the injection signal to generate a divided frequency signal. The current source is coupled to the oscillator to provide a current to the oscillator. The transformer is coupled between the injection transistor and the oscillator to increase the equivalent transconductance of the injection transistor, and thus increasing the locking range of the injection-locked frequency divider.

Abstract: A method for dividing the frequency of a signal using a configurable dividing ratio is disclosed. An input signal with a first frequency is received at clocked switches in a frequency divider with a configurable dividing ratio. Non-clocked switches inside the frequency divider are operated to select one of multiple dividing ratios. An output signal is output with a second frequency that is the first frequency divided by the selected dividing ratio.

Abstract: A divider circuit for dividing the frequency of a multi-phase clock signal, which can ensure a sufficient data latch time even if the multi-phase clock signal has a high frequency, includes a main latch circuit which generates an inverted data signal using, for example, two of eight clock signals of an eight-phase clock signal, and a sub-latch circuit which uses the eight clock signals as a trigger to receive the inverted data signal as a common data signal.

Abstract: A divider of an input multiphase signal by a given division factor so as to obtain an output multiphase signal, the divider having a circuit adapted to divide a first signal component of an input multiphase signal by an given division factor to obtain a first component of a output multiphase signal, and a plurality of N?1 devices including a first device adapted to sample the first component with a component of the input multiphase signal to obtain the component of the output multiphase signal corresponding to the one component of the input multiphase signal. Every other device of the plurality of N?1 devices is adapted to sample the component of the output multiphase signal of the preceding device with another component of the input multiphase signal, phase shifted by a further constant factor to obtain the corresponding component of the output multiphase signal.

Abstract: A divider circuit includes a shift register which generates 2X (X is a natural number greater than or equal to 2) pulse signals in accordance with a first clock signal or a second clock signal and outputs them, and a divided signal output circuit which generates a signal to be a third clock signal with a cycle X times longer than a cycle of the first clock signal in accordance with the 2X pulse signals and outputs it. The divided signal output circuit includes X first transistors which control whether voltage of the signal to be the third clock signal is set to first voltage; and X second transistors which control whether voltage of the signal to be the third clock signal is set to second voltage.

Abstract: A mask circuit (10) masks the clock pulses of a clock S in accordance with an input mask signal (50), generating and outputting a clock B. A mask control circuit (20) generates a mask signal (50) which assigns mask timings to mask (M?N) clock pulses, to timings other than communication timings to perform data communication, out of the timings of M successive clock pulses of the clock S, based on communication timing information (30) indicating the communication timings of data communication that is performed with a circuit A by a circuit B using the clock B. The mask control circuit (20) then outputs the mask signal (50) to the mask circuit (10).

Abstract: A circuit includes first and second frequency divider circuits and first storage circuits. Each of the first and the second frequency divider circuits receives periodic input signals and generates a periodic output signal having a frequency of one of the periodic input signals in a bypass mode. The periodic output signal of each of the first and the second frequency divider circuits has a fraction of a frequency of one of the periodic input signals in a frequency divider mode. Each of the first storage circuits stores an enable signal in response to the periodic output signal of one of the first frequency divider circuits. The enable signals stored in the first storage circuits enable the second frequency divider circuits in the frequency divider mode. The circuit may include second storage circuits storing enable signals that enable a subset of the first frequency divider circuits in the frequency divider mode.

Abstract: There are numerous types of dividers that have been employed at various frequency ranges. For many very high frequency ranges (i.e., above 30 GHz), dividers in CMOS have been developed. However, many of these designs use multiple stages. Here, however, a single stage divider has been provided that is adapted to operate at very high frequencies (i.e., 120 GHz). To accomplish this, it uses parasitic capacitances in conjunction with inductor(s) to form an LC tanks so as to take advantages of parasitics that normal degrade performance.

Abstract: A clock divider circuit. The clock divider receives m input clock signals each of the same frequency. Each input clock signal after the first has a phase offset of 2 ?/m from the previous input clock signal. The clock divider divides the frequency of the input clock signals by an integer of division K. The clock divider includes a counter that receives the first input clock signal and provides one or more count signals. The clock divider also includes m flip-flops, of which a first flip-flop receives the first input clock signal at its clock input and provides a first clock output signal. Each flip-flop after the first receives an input clock signal at its clock input and provides a clock output signal, each clock output signal after the first having a 2 ?K/m phase offset from the previous clock output signal.

Abstract: The invention includes a harmonic suppression circuit, an injection-locked frequency divider circuit (ILFD) and associated methods. The harmonic suppression circuit comprises a source voltage, two suppression modules, two input terminals, two smoothed output terminals and a ground. The ILFD comprises a ground, an input transistor, an input terminal, two divider legs, two output terminals and a source voltage. The associated method to improve harmonic suppression comprises acts of synthesizing differential-phase signals and simultaneously suppressing second harmonics of in-phase signals. The method to extent an ILFD's locking range comprises acts of decreasing quality factor while keeping resonance frequency constant.

Abstract: A quadrature output high-frequency RF divide-by-two circuit includes a pair of differential complementary logic latches. The latches are interconnected to form a toggle flip-flop. Each latch includes a tracking cell and a locking cell. In a first embodiment, the locking cell includes two complementary logic inverters and two transmission gates. When the locking cell is locked, the two gates are enabled such that the locked (i.e., latched) signal passes through both transmission gates and both inverters. In one advantageous aspect, the tracking cell only involves two transmission gates. Due to the circuit topology, the first embodiment is operable from a low supply voltage at a high operating frequency while consuming a low amount of supply current. In a second and third embodiment, the tracking cell involves a pair of inverters. The sources of the transistors of the inverters are, however, coupled together thereby resulting in performance advantages over conventional circuits.

Abstract: A representative injection-locked frequency divider includes a differential direct injection pair that is configured to receive and mix differential injection signals and an oscillator that is electrically connected to the differential direct injection pair and produces an operating frequency based on the mixed differential injection signals.

Abstract: The present invention provides a CMOS-inverter-type frequency divider circuit that can further reduce power consumption. The CMOS-inverter-type frequency divider circuit includes: a plurality of CMOS inverters that contribute to realizing a frequency division function; a frequency division control section for performing control such that some or all of the plurality of CMOS inverters are intermittently driven at the respective different timings in accordance with an input signal; and a drive power supplying section for supplying powers for driving the plurality of CMOS inverters, and for, based on state information indicating whether VCO sub band selection or normal transmission is performed, switching some or all of the powers for the plurality of CMOS inverters between the VCO sub band selection and the normal transmission.

Abstract: A latch module comprising a sense pair of transistor elements coupled together for sensing a differential input signal at input terminals, a level-shift module for producing a differential output signal at output terminals, and a regenerative pair of transistor elements coupled together and with the input pair for holding the output signal through the level-shift module. The latch module also includes a pair of gate transistor elements connected in series respectively with the sense pair of transistor elements and with the regenerative pair of transistor elements and responsive to an alternating differential gate signal to activate alternately the sense pair during sense periods and the regenerative pair during store periods. A current injector provides asymmetric operation by injecting current between at least one of the gate transistors and the corresponding sense or regenerative pair of transistor elements so that the sense periods are of different duration from the store periods.

Abstract: A prescaler circuit according to an exemplary aspect of the present invention includes a first flip-flop circuit that detects second output data and outputs the detected data as first output data, and a second flip-flop circuit that detects the first output data and outputs the data as the second output data. The first flip-flop circuit includes a master-side latch circuit that generates intermediate data, a slave-side latch circuit that detects the intermediate data and outputs the data as the first output data, and a control signal switching circuit that selects and outputs the first output data as a control signal in a mode where the frequency is divided by 3, and selects and outputs a predefined fixed signal as a control signal in a mode where the frequency is divided by 4. The master-side latch circuit generates the intermediate data based on the second output data and the control signal.

Abstract: A system including a first frequency divider, a plurality of second frequency dividers, and a control module. The first frequency divider includes a first plurality of components and is configured to divide an input frequency of an input signal to generate a first signal having a first frequency and a first phase. Each of the plurality of second frequency dividers includes a second plurality of components and is configured to divide the input frequency of the input signal to generate a second signal having the first frequency and a second phase. The control module is configured to connect the second plurality of components of one of the second frequency dividers to the first plurality of components of the first frequency divider.

Abstract: An injection-locked frequency divider is provided and which includes an injection transistor, an oscillator, a current source and a transformer. The injection transistor is used to receive an injection signal. The oscillator is used to divide the injection signal to generate a divided frequency signal. The current source is coupled to the oscillator to provide a current to the oscillator. The transformer is coupled between the injection transistor and the oscillator to increase the equivalent transconductance of the injection transistor, and thus increasing the locking range of the injection-locked frequency divider.

Abstract: A parallel path frequency divider (PPFD) includes a low power frequency divider and a high speed latch. A first portion of an oscillating input signal present on an input node of the PPFD is communicated to the divider and a second portion is communicated to the latch. The divider generates a frequency divided enable signal that is communicated to the latch. The latch generates a divided down output signal based on the oscillating input signal and the enable signal. The output signal is insensitive to phase noise present on the enable signal as long as the phase noise on the enable signal is less than one-half of the period of oscillation of the oscillating input signal. Because the noise generated by the low power frequency divider is not propagated to the output signal generated by the PPFD, the PPFD generates low noise, frequency divided signals with relatively low power consumption.

Abstract: Frequency divider circuits and architectures, and methods of implementing and using the same, are disclosed. In one embodiment, the frequency divider circuit includes a dynamic section that receives an input signal and outputs an intermediate signal that has a frequency lower than that of the input signal; and a static section that receives the intermediate signal and outputs a signal having a frequency that is lower than that of the intermediate signal. Stages in the dynamic and/or static section can be implemented using thin film transistors (TFTs). Embodiments of the present invention advantageously provide an approach that takes overcomes problems associated with the leakage and speed characteristics of TFTs.

Abstract: Various embodiments of a flip-flop and a frequency dividing circuit are provided. In one aspect, a flip-flop includes an input stage and a latch stage. The input stage is capable of converting an input signal to an output signal under the control of a first clock signal and a second clock signal. The latch stage is capable of latching the output signal under the control of a third clock signal and a fourth clock signal. The first clock signal, the second clock signal, the third clock signal and the fourth clock signal have different phases.

Abstract: Phase-coherent differential structures contain a phase-coherent transformer having two pairs of phase-coherent coupled differential inductors.

Abstract: A frequency doubler receiving an in-phase oscillating signal and an inverse oscillating signal and generating an output signal oscillating at a multiplied frequency, accordingly. The frequency doubler has a first transistor, a second transistor, a first inductor and a second inductor. A first terminal of the first transistor and a first terminal of the second transistor are at a common voltage. The frequency doubler receives the in-phase oscillating signal and the inverse oscillating signal via control terminals of the first and second transistors. The first and second inductors couple a second terminal of the first transistor and a second terminal of the second transistor to an output terminal of the frequency doubler, respectively. The first and second inductors may be separate inductance devices or, in another case, be implemented by a symmetric inductor.

Abstract: A master stage 101 comprises a differential circuit composed of transistors 1 and 2, a differential circuit composed of transistors 3 and 4, a differential circuit composed of transistors 5 and 6, a load circuit 7 (a first load circuit), a load circuit 8 (a second load circuit), and a current source transistor 9. The load circuit 7 (the first load circuit) is composed of an inductor 7A (a first inductor), an inductor 7B (a fifth inductor), and a capacity 7C (a first capacity). The inductor 7B and capacity 7C cooperates together in forming a parallel resonance circuit (a first LC parallel resonance circuit), while the parallel resonance circuit is connected in series to the inductor 7A.

Abstract: A buffer circuit buffers incoming signals, from a local oscillator generator to a mixing circuit and has a push-pull circuit having two inputs, a first being coupled to a first incoming signal, and a second of the inputs being coupled to one of the buffered versions of the incoming signals, having a phase related to that of the first incoming signal. By coupling a second input to a buffered version rather than to the incoming signal, the load presented to the preceding circuit can be halved, while maintaining reduced power consumption. By using as a second input, a signal which is phase related to the first incoming signal, the normal operation of the push-pull circuit can be maintained. The incoming signals from the LO generator can be differential IQ signals and the buffered version of the further incoming signal be in phase with the first incoming signal.

Abstract: There is provided a true single phase logic clock divider that is configured to selectively divide a clock signal by increments of two, three, four, or six. Because the true single phase logic clock divider is based on true single phase logic instead of static logic, the true single phase logic clock divider is able to reliably divide clock signals that could not reliably be divided by clock dividers based on static logic gates. The true single phase logic clock divider is capable of reliably operating at frequencies of greater than or equal to two gigahertz.

Abstract: A digital programmable frequency divider is constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ non-destructive readout cell (NDRO), RSFQ D flip-flop and an RSFQ T flip-flop. A digital word comprising N bits is used to control the amount of frequency division and the frequency divider selectively imparts a respective frequency division for any of 2n states that can be represented by the digital word. The RSFQ logic elements utilize Josephson junctions which operate in superconducting temperature domains.

Abstract: A clock system includes a phase locked loop, a phase divider, and a control module. The phase locked loop (PLL) produces a plurality of phase-offset output oscillations. The phase divider generates a clock signal from one or more of the plurality of phase-offset output oscillations based on a phase divider control signal. The control module generates the phase divider control signal based on a desired setting for the clock signal.

Abstract: A frequency divider having a plurality of programmable latches connected in a feedback shift register configuration. A programmable latch of said plurality of latches comprises a program input to receive a program signal configured to select a polarity of the programmable latch among two opposite polarities. The frequency divider having a configuration module structured to provide at least the program signal to the program input to modify a divisor parameter of the frequency divider.

Abstract: A frequency divider involves a plurality of Injection-locked Ring Oscillators (ILRO). A first ILRO includes a pair of cross-coupled N-channel transistors, a pair of load resistors, an integrating capacitor, and a current injection circuit. The drain of each transistor is coupled to the gate of the other transistor. Each load resistor couples the drain of each transistor to a circuit voltage source. The integrating capacitor couples the sources of each transistor. The current injection circuit alternately opens and closes a path from the source of each transistor to circuit ground in response to an oscillatory input signal of a first frequency. In response, the voltage state at the drain of each transistor is alternately latched and toggled, generating a differential pair of oscillating signals frequency divided by two. A first and second ILRO driven in antiphase generate two differential output signals in phase quadrature.

Abstract: A multimode millimeter-wave frequency divider circuit with multiple selectable frequency dividing modes is proposed, which is designed for integration with a millimeter wave (MMW) circuit system, such as a phase-locked loop (PLL) circuit, for providing multimode frequency dividing functions. In actual application, the millimeter wave frequency divider circuit of multi frequency dividing mode provides at least three frequency dividing operational modes, including modes of dividing two, dividing 3 and dividing four. In practice, the millimeter wave frequency divider circuit of multi frequency divider mode may be integrated with a millimeter wave phase-locked circuit to provide a frequency synthetic function having multi frequency sections, such as including 38 GHZ, 60 GHZ and 77 GHZ, and may use reduced circuit layout surfaces and operational power.

Abstract: A frequency synthesizer includes first and second frequency dividers for receiving and frequency-dividing a signal generated by a voltage-controlled oscillator, a frequency mixer for mixing output signals of the first and second frequency dividers, and a third frequency divider for receiving and frequency-dividing a signal having one frequency of two frequencies that are output by the frequency mixer. The first, second third and frequency dividers and the frequency mixer are provided in a feedback loop within a PLL circuit between the voltage-controlled oscillator and the phase comparator. The phase comparator has a first input terminal to which a signal to which a signal that is output by the third frequency divider is input and a second input terminal to which a reference clock signal that is output by a reference signal generator is input. A loop filter supplies the voltage-controlled oscillator with a voltage that is based upon result of the phase comparison by a phase comparator.

Abstract: A divider circuit for dividing the frequency of a multi-phase clock signal, which can ensure a sufficient data latch time even if the multi-phase clock signal has a high frequency, includes a main latch circuit which generates an inverted data signal using, for example, two of eight clock signals of an eight-phase clock signal, and a sub-latch circuit which uses the eight clock signals as a trigger to receive the inverted data signal as a common data signal.

Abstract: A latch module comprising a sense pair of transistor elements coupled together for sensing a differential input signal at input terminals, a level-shift module for producing a differential output signal at output terminals, and a regenerative pair of transistor elements coupled together and with the input pair for holding the output signal through the level-shift module. The latch module also includes a pair of gate transistor elements connected in series respectively with the sense pair of transistor elements and with the regenerative pair of transistor elements and responsive to an alternating differential gate signal, to activate alternately the sense pair during sense periods and the regenerative pair during store periods. A current injector provides asymmetric operation by injecting current between at least one of the gate transistors and the corresponding sense or regenerative pair of transistor elements so that the sense periods are of different duration from the store periods.

Abstract: A high frequency divider involves a plurality of differential latches. Each latch includes a pair of cross-coupled P-channel transistors and a variable resistance element. The latch is controlled to have a lower output resistance at high operating frequencies by setting a multi-bit digital control value supplied to the variable resistance element. Controlling the latch to have a reduced output resistance at high frequencies allows the 3 dB bandwidth of the latch to be maintained over a wide operating frequency range. The variable resistance element is disposed between the two differential output nodes of the latch such that appreciable DC bias current does not flow across the variable resistance element. As a consequence, good output signal voltage swing is maintained at high frequencies, and divider current consumption does not increase appreciably at high frequencies as compared to output signal swing degradation and current consumption increases in a conventional differential latch divider.

Abstract: A frequency divider includes a transmission gate, a first inverter, a first switch circuit, a second switch circuit, and a second inverter. The transmission gate transmits a clock signal according to an inverted enable signal. The first inverter inverts the clock signal outputted from the transmission gate. The first switch circuit generates a first control signal according to the inverted clock signal and an output signal of the frequency divider. The second switch circuit generates a second control signal according to the clock signal, the inverted clock signal, and the first control signal. The second inverter inverts the second control signal to generate the output signal. The frequency of the clock signal is a multiple of the frequency of the output signal.

Abstract: An apparatus includes an injection locking frequency divider, which includes a first resonant tank that has a first resonance frequency and a common mode path that includes a second resonant tank, and has a second resonance frequency that is a harmonic of the first resonance frequency. The second resonant tank is adapted to receive a first signal having an oscillation frequency near the harmonic of the first resonance frequency to cause the first resonant tank to provide a second signal that is locked to the first signal.

Abstract: A prescaler circuit according to an exemplary aspect of the present invention includes a first flip-flop circuit that detects second output data and outputs the detected data as first output data, and a second flip-flop circuit that detects the first output data and outputs the data as the second output data. The first flip-flop circuit includes a master-side latch circuit that generates intermediate data, a slave-side latch circuit that detects the intermediate data and outputs the data as the first output data, and a control signal switching circuit that selects and outputs the first output data as a control signal in a mode where the frequency is divided by 3, and selects and outputs a predefined fixed signal as a control signal in a mode where the frequency is divided by 4. The master-side latch circuit generates the intermediate data based on the second output data and the control signal.

Abstract: A multimode millimeter-wave frequency divider circuit with multiple selectable frequency dividing modes is proposed, which is designed for integration with a millimeter wave (MMW) circuit system, such as a phase-locked loop (PLL) circuit, for providing multimode frequency dividing functions. In actual application, the millimeter wave frequency divider circuit of multi frequency dividing mode provides at least three frequency dividing operational modes, including modes of dividing two, dividing 3 and dividing four. In practice, the millimeter wave frequency divider circuit of multi frequency divider mode may be integrated with a millimeter wave phase-locked circuit to provide a frequency synthetic function having multi frequency sections, such as including 38 GHZ, 60 GHZ and 77 GHZ, and may use reduced circuit layout surfaces and operational power.

Abstract: A fully differential frequency divider includes a first fully differential single-stage latch circuit configured to receive an input signal and provide a corresponding output signal upon transition of a clock signal, the output signal corresponding to an in-phase portion of a communication signal, and a second fully differential single-stage latch circuit coupled to the first fully differential single-stage latch circuit, the second fully differential single-stage latch circuit configured to provide a corresponding output signal upon transition of the clock signal.

Abstract: An injection-locked frequency divider for dividing a frequency of an injection signal and obtaining a frequency divided signal is provided. The injection-locked frequency divider includes a signal injection unit and an oscillator. The signal injection unit includes a first input terminal and a second input terminal for receiving the injection signal. The received injection signal exhibits a phase difference of 180° between the first input terminal and the second input terminal. The oscillator includes an inductor unit and a variable capacitance unit. The injection-locked frequency divider is featured with a wide injection locking range, and can be realized with a low operation voltage, and therefore can be conveniently used in different kinds of hybrid ICs.

Abstract: A fraction-N frequency divider includes a multi-phase clock generator, a first phase selector, a second phase selector, a glitch-free multiplexer, a control circuit, and a counter. The multi-phase clock generator is used for generating a plurality of clock signals with different phases. The first phase selector selects one of the clock signals as a first clock signal according to a first phase selecting signal. The second phase selector selects one of the clock signals as a second clock signal according to a second phase selecting signal. The glitch-free multiplexer is used for selectively outputting one of the first and second clock signals. The control circuit generates the first and second phase selecting signals and controls the clock switching timing of the glitch-free multiplexer according to a divisor setting. The counter is used for generating a frequency-divided signal according to the output of the glitch-free multiplexer.

Abstract: One embodiment relates to a frequency divider. The frequency divider includes an active mixer having a first mixer input, a second mixer input, and a mixer output. The first mixer input is adapted to receive an input signal having an input frequency, and the mixer output is adapted to provide a mixed signal based on the input signal. The frequency divider also includes an amplification element having an amplification input and an amplification output. The amplification input is adapted to receive the mixed signal and the amplification output is adapted to provide an amplification output signal having an output frequency. A feedback path, which includes an alternating current (AC) coupling element, couples the amplification output to the second mixer input. Other systems and methods are also disclosed.

Abstract: A clock generator is illustrated. The clock generator mentioned above includes a multimodulus frequency divider and a delta-sigma modulator. The multimodulus frequency divider is archived by switching the phase thereof. The multimodulus frequency divider increases the operating frequency of the clock generator effectively, and has a characteristic with half period resolution for reducing the jitter of an output clock signal when its spectrum is spread. Besides, the delta-sigma modulator increases the accuracy of the triangle modulation and reduces error of quantization by adding a few components therein. Thus, the clock generator could be expanded to a programmable clock generator.