Abstract: A display device capable of discharging residual charges includes a discharging circuitry to discharge charges remaining in a GIP driver, a Gate D-IC, a Source D-IC, a Gamma IC, etc. to a ground GND when a display panel is powered off, so that the display device protects the display panel by rapidly discharging residual charges that may accumulate on the display panel and a printed circuit board when power is off.

Abstract: A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.

Abstract: The DC voltage conversion circuit includes a booster circuit and a protection circuit. When the booster circuit is under EOS test, a detection circuit of the protection circuit obtains a second detection voltage from the voltage on the VGH line. A first adjustment circuit produces a third signal based on the comparison result of the second detection voltage and a reference voltage. A second adjustment circuit produces a fourth signal based on the comparison result of the second detection voltage and the reference voltage. The third and fourth signals adjust the equivalent resistances of a first and a second feedback circuits to a third and a forth equivalent resistances, respectively. Through the adjustment of the equivalent resistances of the first and second feedback circuits, the voltage of the VGH line is restored to that when no test signal is applied.

Abstract: The battery monitoring IC is provided with the short circuiting switch that includes the switching element that shorts the input side and the output side of the boosting circuit that boosts the power supply voltage to the driving voltage, that can drive the MOS transistor within the buffer amplifier in the saturated region, and supplies the driving voltage as the driving voltage of the buffer amplifier. An abnormality of the boosting circuit can be diagnosed by comparing the output voltage, that is measured when the short circuiting switch is turned off and the driving voltage boosted by the boosting circuit is supplied to the buffer amplifier, and the output voltage, that is measured when the short circuiting switch is turned on and the power supply voltage is, without going through the boosting circuit, supplied as is to the buffer amplifier.

Abstract: Various embodiments provide a Phase Interpolator (PI) that receives input clocks, and outputs intersymbol interference-equalized, phase-shifted output clocks. In one embodiment, the Phase Interpolator comprises two PI Conditioners and a PI Mixer. In one embodiment, a PI Conditioner receives input clocks and is controlled by a different phase-shifted input clock by using a suitable circuit element, such as a flip-flop. Collectively, the input clock-controlled PI Conditioner and Mixer act in concert to control the band limiting effect of the PI Conditioner which, in turn, equalizes intersymbol interference.

Abstract: In one embodiment, the invention can be a clock-generating circuit having one or more clock-processing circuits, each outputting a clock signal having an adjustable phase. Each clock-processing circuit comprises a divider and a divisor control circuit. Each divider divides an input clock signal by a respective divisor value and outputs a corresponding output clock signal whose period is determined by the divisor value and the period of the input clock signal. Each divider receives the respective divisor value from the corresponding divisor control circuit, wherein the divisor value is selected in order to achieve a desired frequency and phase for the corresponding output clock signal. Temporarily changing a divisor value can advance or delay the phase of the corresponding output clock signal without having to reset the divider.

Abstract: A frequency multiplier increases the frequency of an external clock and outputs a high-frequency external clock. A period determinator determines whether or not a predetermined period of the external clock elapses and outputs a period determination signal. A frequency selector selectively transmits the external clock or the high-frequency external clock to a clock input buffer under the control of a power-up signal and the period determination signal.

Abstract: A programmable frequency multiplier device which includes a frequency doubler section configured to receive an input signal having a frequency f, and to output doubled signals, each of the doubled signals having a frequency 2n×f (n=0, 1, 2, . . . ); a selector section configured to select a plurality of the doubled signals output from the frequency doubler section, and to output the plurality of the selected doubled signals as selected signals; and a frequency summation section configured to multiply the selected signals, and to output a multiplied signal having a frequency fout=f×(m020+m121+ . . . +mk2k+ . . . +mn2n), wherein mk=0 or 1, and k=0, 1, . . . , n.

Abstract: The present invention relates to a method for synchronizing a number of digital clocks to a synchronizing signal, said method comprising generating centrally a reference clock, synthesizing said digital clocks from said reference clock using a clock multiplier, respectively, resetting said clock multiplier in response to said synchronizing signal, and masking an output signal of said clock multiplier during settling time of said clock multiplier.

Abstract: A clock multiplication circuit simple in configuration, easy to adjust the characteristics thereof, and capable of shortening lockup time. The circuit delivers an output clock signal at a frequency that is a multiple of the frequency of a reference clock signal as inputted. A counter counts the number of rising edges of the output clock signal existing during a High level period of the reference clock signal, delivering a count value CN. A subtracter subtracts the count value from a reference value BN, delivering a difference value DN. An adder adds the difference value to a preceding integrated value, calculating a new integrated value. A DA converter delivers the analog control voltage corresponding to the integrated value. A VCO delivers the output clock signal at a frequency corresponding to the analog control voltage. The frequency of the output clock signal is controlled such that DN=BN?CN=0.

Abstract: A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1× double data rate memory speed, and means for receiving data and strobe signals via said pads at M× double data rate memory speed (M?2).

Abstract: A clock doubler including clock doubling circuitry for generating from a system clock a clock signal having a frequency substantially double that of the system clock and also having a pulse width and associated duty cycle is provided. Timing circuitry for generating a first signal indicative of the time the clock signal is low and a second signal indicative of the time the clock signal is high provides an input to comparison circuitry for comparing the first signal and the second signal. Pulse width varying circuitry varies the pulse width of the clock signal based on the result of comparing the first signal and the second signal.

Abstract: A clock multiplier circuit which generates a multiple clock having a stable frequency from a reference clock without using analog devices. The clock multiplier circuit includes ring oscillator which oscillates at a higher frequency than that of the multiple clock; a reference clock counter for counting the sampling output of the reference clock by the output clock of the ring oscillator to obtain a count value of the half cycle of the reference clock; and a multiple clock counter which, in case the value obtained by dividing the count value of the half cycle of the obtained reference clock by the multiplication factor externally given is defined as a multiple count value, inverts the multiple clock output each time it counts the multiple count value by the output clock of the ring oscillator.

Abstract: A clock multiplier circuit is receives an input signal and generates a clock output signal. The clock multiplier circuit generates a number of pulses to be used as the clock output signal, wherein the pulses have a pulsewidth that is independent of the number of pulses generated and independent of the frequency of a clock control signal used for masking. The clock multiplier circuit includes an oscillator, a storage device for synchronization of the masking signal to the pulses and a logic circuit to generate the clock output signal. The clock multiplier circuit causes a number of unmasked pulses to be output as the output clock signal in response to the clock control signal, while other pulses are masked.

Abstract: A signal peaking circuit for selectively emphasizing, or boosting, the higher frequencies of an incoming signal. A frequency emphasis circuit with an overall high pass transfer characteristic selectively emphasizes higher frequency signal components over lower frequency signal components. The transfer characteristic is selectively variable to allow the number and peak values of the emphasized signal components to be selectively variable.

Abstract: A frequency multiplier circuit and a controlling method thereof, which measures a period of a waveform by counting cycles of a fixed frequency timing signal, and reproduces the period by adding a number of prefixed length subperiods of the fixed frequency to the cycle count, making it as equal as possible to the period, so to minimize the reproduction error.

Abstract: A digital frequency multiplier provides non-integer frequency multiplication of an input signal. A multiplexer receives the input signal and an integer multiple of the input signal. A multiplexer control signal selects/toggles which signal the multiplexer will output and how long. A counter, clocked by one of the signals, provides the multiplexer control signal. The multiplexer outputs a pre-determined number of clock cycles of each signal to produce the desired non-integer frequency multiplied input signal. The present invention generates frequency multiplication without a phase locked loop (PLL).

Abstract: A DC-DC voltage boosting method is capable of reducing power consumption by detecting a margin of a boosting voltage, even if the display mode of a liquid crystal panel or a displayed content changes. Included are the steps of (a) boosting an input voltage by using clock signals to generate a boosted voltage, (b) generating a stabilized operating voltage by using the boosted voltage, (c) detecting a margin voltage between the boosted voltage and the operating voltage, and (d) based on the detected result in step (c), adjusting the frequency of the clock signals used in step (a) or fixing at least one of the clock signals which control switching components.

Abstract: A delayed matching signal generator and frequency multiplier using scaled delay networks for providing precisely delayed matching signals and multiplied frequency signals is provided. The system and method of phase shifting a periodic input digital signal comprises a reference delay line, a replica delay line, and a matched characteristics control system. The reference delay line is composed of multiple reference delay stages through which the input signal is propagated, and the replica delay line is composed of replica delay stages scaled in proportion to the multiple reference delay stages by a scaled delay factor wherein the input signal is propagated. The matched characteristics control system is coupled to the reference delay line and the replica delay line for extracting a phase shifted signal from the replica delay line based upon the scaled delay factor and a scaled propagation of the input signal through the reference delay line.

Abstract: A digital frequency-doubling circuit includes a pair of cascaded first delay circuits, each including a plurality of cascaded delays, and a first stage of the cascaded first delay circuits receiving an input signal to be frequency-doubled, and an exclusive-OR circuit receiving the input signal and a delayed output signal outputted from the first stage of the cascaded first delay circuits, for generating a frequency-doubled signal. A delay amount comparator receives a first delayed output signal outputted from a second stage of the cascaded first delay circuits and a second delayed output signal outputted from a second delay circuit of a small delay receiving the first delayed output signal, for performing comparison at a transition timing of the input signal, to discriminate whether the obtained frequency-doubled signal advances or delays in comparison of an optimum duty ratio.

Abstract: In a frequency multiplier circuit, a first delaying section delays a reference signal and generates an output signal when the reference signal has been delayed by a predetermined delay time. A second delaying section generates n (n is an integer more than 0) delayed signals from the reference signal. The first delayed signal of the n delayed signals has a first delay time with respect to the reference signal, and an m-th delayed signal (m is a positive integer and m.ltoreq.n) of the n delayed signal has an m-th delay time with respect to the reference signal. The first through n-th delay times are integer multiples of the first delay time and the predetermined delay time is equal to (n+1) times the first delay time. The second delaying section has a plurality of different input locations for receiving the reference signal and one of the input locations is set to receive the reference signal in accordance with a setting signal from the first delaying section.

Abstract: In a semiconductor integrated circuit, a CMOS logic circuit receives a voltage from a power-source line, while releasing a current through a ground line. A constant-voltage auxiliary circuit is disposed in parallel with the CMOS logic circuit. The constant-voltage auxiliary circuit receives an output signal from the CMOS logic circuit. The constant-voltage auxiliary circuit consumes power when the output signal from the CMOS logic circuit is stable to maintain a potential difference between the power-source line and the ground line at a specified voltage and halts power consumption when the output signal from the CMOS logic circuit is inverted, i.e., when the potential difference is decreasing, thereby suppressing the decrease of the potential difference. Accordingly, voltage fluctuations on the power-source line are suppressed.

Abstract: A harmonic generator (20) converts an input signal (24) at a fundamental frequency (28) into an output signal (32) at a harmonic frequency (34). A non-linear device (22) converts the input signal (24) into an intermediate signal (38) in which the harmonic frequency (34) has a maximized amplitude (40) determined by a conduction angle (26). A harmonic filter (68) produces a filtered signal (70) proportional to the amplitude (40) of the harmonic frequency (34) within the intermediate signal (38). A detector (80) produces a control signal (82) proportional to the amplitude of the filtered signal (70). A control circuit (84) produces a variable bias signal (50) for non-linear device (22), bias signal (50) being proportional to the amplitude of the control signal (82) and determining the conduction angle (26). An output filter (88) converts the intermediate signal (38) into an output signal (32) at the harmonic frequency (34).

Abstract: A booster circuit device comprises: a liquid crystal drive circuit (14) whose dissipated current changes; a timing circuit (11) for outputting a select signal according to the dissipated current of the liquid crystal drive circuit; a drive signal select circuit (12) for selecting and outputting any one of at least two drive signals CLK of different frequencies on the basis of the select signal outputted by the timing circuit (11); and a booster circuit (13) for supplying a supply voltage to the liquid crystal drive circuit (14) on the basis of the drive signal CLK outputted by the drive signal select circuit (12). Since any of the drive signals CLK of different frequencies can be selected and applied to the booster circuit (13) according to the dissipated current of the liquid crystal drive circuit (14), it is possible to reduce the current dissipation of the booster circuit, that is the current dissipation of the whole booster circuit device can be reduced markedly.

Abstract: A DDS type variable frequency signal generator generates a jitter free and stable output signal regardless of the address interval. If the total number of addressable memory locations of a memory storing digital data is divisible without remainder by an initial address interval, then the memory is read every initial address interval with a clock signal of a predetermined frequency. If the total number of addressable memory locations is not divisible without remainder by the initial address interval, then the address interval is modified to a value that is divisible without remainder into the total number of addressable memory locations and the clock frequency is modified in accordance with this modification of the address interval. The memory is read every modified address interval with the modified clock signal.

Abstract: A sine wave oscillator provides an input signal to a step-recovery diode (SRD). The SRD produces a wideband series of harmonics of the frequency of the sine wave oscillator that are represented as "lines" in a power r.f. frequency plot. The output of the SRD is supplied to one or more bandpass filters or lowpass filters which provide selection windows so that only a specified number of harmonic lines are passed within a selection window. These specified harmonic lines are then coupled to one or more high speed input switches which are coupled to one or more high speed selection switches. The high speed selection switches are each coupled to a separate bandpass filter that is tuned to a different bandpass frequency range. Each bandpass filter corresponds to one or to several adjacent lines of the selection windows.

Abstract: A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.