Frequency Multiplication (e.g., Harmonic Generation, Etc.) Patents (Class 327/119)
  • Patent number: 11940552
    Abstract: An electrical circuit for providing an output signal based on a first input signal and a second input signal has: a mixer which is configured to receive and mix the first and second input signals in order to generate a mixer output signal and to switch on or off based on the first input signal, wherein a DC signal component of the mixer output signal depends on whether the mixer is switched on or off; and a downstream circuit which is configured to switch on or off based on the DC signal component of the mixer output signal and to provide the output signal based on the mixer output signal.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: March 26, 2024
    Assignee: Infineon Technologies AG
    Inventors: Alexander Leibetseder, Andreas Stelzer, Christoph Wagner
  • Patent number: 11838025
    Abstract: In an embodiment a radiofrequency doubler includes a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source configured to provide a bias current, a second terminal of the current source being connected to a first supply potential, a third transistor connected between the first terminal of the current source and a second differential output, a circuit configured to apply an AC component of a first differential input and a first DC voltage to a gate of the first transistor, apply an AC component of a second differential input and the first DC voltage to a gate of the second transistor and apply a second DC voltage to a gate of the third transistor, and a feedback loop configured to control the first voltage or the second voltage from a difference between DC components of the first and second differential outputs so as to equalize the DC components.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: December 5, 2023
    Assignee: STMICROELECTRONICS SA
    Inventor: Lionel Vogt
  • Patent number: 11810953
    Abstract: A sensor for performing measurements is disclosed. It comprises: a substrate; a plurality of graphene field-effect transistors (GFET) deposited on a central area of the substrate; at least one source electrode connected to the GFETs through at least one first metal track, wherein the at least one source electrode is disposed at the periphery of the substrate; at least one drain electrode connected to the GFETs through at least one second metal track, wherein the at least one drain electrode is disposed at the periphery of the substrate; and at least one gate electrode, disposed at least in part at the center of the substrate, wherein, in use of the sensor, when a sample is deposited in contact with the gate electrode and the GFETs, the sample allows gating between the gate electrode and the GFETs.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: November 7, 2023
    Assignee: GRAPHENEA SEMICONDUCTOR SLU
    Inventors: Torres ElĂ­as, Txoperena Oihana, Zurutuza Amaia
  • Patent number: 11733658
    Abstract: The invention relates to a method for the two-position control of an actuator (1) on the basis of a binary sensor signal (y) of a sensor unit (2), which senses a process variable (P), which can be influenced by the actuator (1), in such a way that the sensor unit outputs a first sensor signal value (y1) when a first switching value (Sw1) is exceeded and a second sensor signal value (y0) when a second switching value (Sw1, Sw2) is fallen below, wherein: the actuator (1) is controlled with a manipulated variable (u), which assumes either a first control value (u1) or a second control value (u2); the first control value (u1) and the second control value (u2) are dynamically adapted during the operation of the actuator (1), in dependence on a fall time (t_fall) corresponding to the duration of the first sensor signal value (y1) and a rise time (t_rise) corresponding to the duration of the second sensor signal value (y0), in such a way that the first and second control values converge.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: August 22, 2023
    Assignee: RUHR-UNIVERSITAT BOCHUM
    Inventors: Sebastian Leonow, Martin Moennigmann
  • Patent number: 11652455
    Abstract: A signal processing system may include a signal path and a chop management circuit. The signal path may comprise a chopper configured to chop a differential input signal to the signal path at a chopping frequency and a low-pass filter downstream of the chopper and configured to filter out intermodulation products of a direct current offset of the signal path and intermodulation products of an aggressor on the differential input signal in order to generate an output signal. The chop management circuit may be communicatively coupled to the chopper and configured to, based on operational parameters associated with the signal path, dynamically manage energy of one or more clock signals used to define the chopping frequency.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: May 16, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: Ravi K. Kummaraguntla, Christophe J. Amadi, John L. Melanson, Axel Thomsen, John C. Tucker, Eric J. King
  • Patent number: 11621840
    Abstract: A method is provided for determining a unique identifier of a device, the device including a quantum tunnelling barrier unique to the device. The method comprises applying a potential difference across the quantum tunnelling barrier, the potential difference sufficient to enable tunnelling of charge carriers through the quantum tunnelling barrier. The method further comprises measuring an electrical signal, the electrical signal representative of a tunnelling current through the quantum tunnelling barrier, the tunnelling current characteristic of the quantum tunnelling barrier. The method further comprises determining, from the measured electrical signal, a unique identifier for the device. Related apparatuses, systems, computer-readable media and methods are also provided herein.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 4, 2023
    Assignee: Crypto Quantique Limited
    Inventors: Shahram Mossayebi, Patrick Camilleri, Henry Edward William Montagu
  • Patent number: 11616502
    Abstract: A phase interpolator capable of preventing a glitch from being generated during a clock signal switching operation and a clock signal selector thereof are provided. The clock signal selector includes a selector and a selection signal generator. The selector receives multiple clock signals with different phases. The selector selects one of the clock signals according to a selection signal to generate a selected clock signal. The selection signal generator is coupled to the selector and generates the selection signal. When the selector switches from selecting a first clock signal to selecting a second clock signal as the selected clock signal, the selection signal generator generates a set time point according to a transition point of one of the first clock signal and the second clock signal whose phase lags behind a phase of the other, and generates the selection signal according to the set time point.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: March 28, 2023
    Assignee: ALi Corporation
    Inventors: Yi Ting Chen, Ming-Ta Lee
  • Patent number: 11595028
    Abstract: An apparatus can implement a frequency doubler with duty cycle correction in conjunction with, for instance, a phase-locked loop (PLL) to decrease phase noise. In an example aspect, an apparatus has a frequency doubler including a signal combiner, a first signal pathway, and a second signal pathway. The frequency doubler also includes a doubler input node and a doubler output node. The signal combiner is coupled to the doubler output node. The first signal pathway is coupled between the doubler input node and the signal combiner and includes a first adjustable delay cell. The second signal pathway is also coupled between the doubler input node and the signal combiner and includes a second adjustable delay cell.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 28, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Masoud Moslehi Bajestan, Marco Zanuso, Razak Hossain, Hasnain Lakdawala
  • Patent number: 11588453
    Abstract: A signal receiver includes a data sampler receiving a differential input signal having first and second input signals and determining bit values of the differential input signal based on first and second reference voltages, and a reference voltage generator performing a pre-tuning operation and a post-tuning operation to generate the reference voltages. The reference voltage generator performs the pre-tuning operation by generating first and second initial voltages and adjusting one of the initial voltages to generate third and fourth voltages. After the pre-tuning operation, the reference voltage generator performs the post-tuning operation by increasing or decreasing the third voltage to generate the first reference voltage and decreasing or increasing the fourth voltage to generate the second reference voltage based on a comparison result between the third voltage and the first input signal and a second comparison result between the fourth voltage and second input signal.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: February 21, 2023
    Inventors: Kyoungho Kim, Chulwoo Kim, Hyunsu Park, Jin-Cheol Sim
  • Patent number: 11509317
    Abstract: Systems and methods for integrating injection-locked oscillators into transceiver arrays are disclosed. In one aspect, there is provided an injection-locked oscillator (ILO) distribution system including a master clock generator configured to generate a master clock signal. The ILO distribution system also includes an ILO distribution circuit including an ILO and configured to receive the master clock signal. The ILO is configured to generate a reference clock signal based on the master clock signal. The ILO distribution circuit is further configured to generate an output signal indicative of an operating frequency of the ILO. The ILO distribution system further includes an injection-locked detector (ILD) configured to receive the master clock signal and the output signal. The ILD is further configured to determine whether the ILO is in a locked state or in an unlocked state based on the master clock signal and the output signal.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: November 22, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventors: Sanjeev Jain, Foad Arfaei Malekzadeh
  • Patent number: 11444610
    Abstract: A variable frequency multiplier circuit for frequency multiplying an input signal provided by an ultra-low phase noise signal source includes a tone generator configured to generate a multiple tones from the input signal; a signal separating circuit configured to separate the multiple tones into tones of interest and idler tones, where the tones of interest are separated into one or more groups and outputted from the signal separating circuit, and the idler tones are terminated; an amplification circuit configured to amplify each group of the tones of interest to optimize small and large signal responses; and a switched filter bank configured to selectively connect a selected tone from the tones of interest to a circuit output.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: September 13, 2022
    Assignee: Keysight Technologies, Inc.
    Inventors: Alex Grichener, Naveed Edalati, Leonard M. Weber, Xiaohui Qin, Ryan Michael Avella, David Massie, Stuart Horsburgh, Cameron Blatter, Nicholas Brennan, Michael John Harriman, Andy Ferrara, Harrison Statham, Scott A. Hovland
  • Patent number: 11139841
    Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-Generation (4G) communication system such as long-term evolution (LTE). According to various embodiments of the present disclosure, an apparatus of a transmitter in a wireless communication system may include an oscillating circuit for providing an oscillating signal, and a radio frequency (RF) circuit for converting a frequency of a transmit signal using the oscillating signal, and transmitting the transmit signal. The oscillating circuit may generate a base oscillating signal of a differential signal form, by multiplying a first signal and a second signal which constitute the different signal, generate a first signal set from the first signal and a second signal set from the second signal, and generate a signal in which at least one harmonic component adjacent to an intended frequency component is suppressed using the first signal set and the second signal set.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: October 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jooseok Lee, Woojae Lee, Daeyoung Lee
  • Patent number: 11108328
    Abstract: Systems and methods are provided for signal processing. An example error amplifier for processing a reference signal and an input signal associated with a current of a power conversion system includes a first operational amplifier, a second operational amplifier, a first transistor, a second transistor, a current mirror component, a switch, a first resistor and a second resistor. The first operational amplifier includes a first input terminal, a second input terminal and a first output terminal, the first input terminal being configured to receive a reference signal. The first transistor includes a first transistor terminal, a second transistor terminal and a third transistor terminal, the first transistor terminal being configured to receive a first amplified signal from the first output terminal, the third transistor terminal being coupled to the second input terminal.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: August 31, 2021
    Assignee: On-Bright Electronics (Shanghai) Co., Ltd.
    Inventors: Liqiang Zhu, Jiqing Yang, Yaozhang Chen, Zhuoyan Li, Qiang Luo, Lieyi Fang
  • Patent number: 11031962
    Abstract: Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively. Each of the first and second carrier receivers may further include a digital mixer for further translating the frequencies of the receive signal in the digital domain.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-hyun Oh, Chilun Lo, Barosaim Sung, Jae-hoon Lee, Jong-woo Lee
  • Patent number: 10790838
    Abstract: Dynamic voltage frequency scaling to transition to a target clock frequency and associated target voltage is provided. Dynamic voltage frequency scaling to a different clock frequency is performed by gradually changing the clock frequency using discrete variable-size steps, while dynamically switching to faster or slower reference clock frequencies as appropriate to harmonize the frequency trajectory with system requirements.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Praveen Mosalikanti, Vaughn J. Grossnickle, Syed Feruz Syed Farooq, Mark Neidengard, Nasser A. Kurd
  • Patent number: 10686474
    Abstract: One illustrative dual mode frequency multiplier embodiment includes: a first and a second nonlinear element, a summation node, and a switchable phase shifter. The first and second nonlinear elements are driven by a differential signal to produce a first and a second branch signal each having even and odd harmonics, the even harmonics being in-phase and the odd harmonics being out of phase. The first and second branch signals combine at the summation node to form a combined signal. The switchable phase shifter couples the first nonlinear element to the summation node, providing the first branch signal with a phase shift switchable between 0 and 180° to suppress either the odd or the even harmonics from the combined signal.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 16, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Roee Ben-Yishay
  • Patent number: 10573370
    Abstract: Apparatuses and methods for triggering row hammer address sampling are described. An example apparatus includes an oscillator circuit configured to provide a clock signal, and a filter circuit. The filter circuit includes a control circuit configured to receive pulses of the clock signal and provide an output signal that represents a count number by counting a number of pulses of the clock signal and control a probability of enabling the output signal based on the count number. The filter circuit further includes a logic gate configured to pass one of the pulses of the clock signal responsive to the output signal from the control circuit being enabled and filter another of the pulses responsive to the output signal from the control circuit being not enabled.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yutaka Ito, Yuan He
  • Patent number: 10396805
    Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: August 27, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Liang Gu, Yuming Cao, Yen Dang, Gong Lei, Yifan Gu, Hung-Yi Lee, Mamatha Deshpande, Shou-Po Shih, Miao Liu
  • Patent number: 10211819
    Abstract: An input buffer circuit is disclosed, which relates to a technology for a receiver circuit including a plurality of input buffers having different characteristics. The input buffer circuit includes a first buffer configured to output a first input signal by buffering a command address received based on a flag signal, a second buffer configured to output a second input signal by buffering the command address based on the flag signal, a first delay matching circuit configured to output a first matching signal by delaying the first input signal by a first delay time, a second delay matching circuit configured to output a second matching signal by delaying the second input signal by a second delay time, and a selection circuit configured to select any one of the first matching signal and the second matching signal based on a selection signal.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 19, 2019
    Assignee: SK hynix Inc.
    Inventor: Kwang Hun Lee
  • Patent number: 10090881
    Abstract: The present invention provides a semiconductor device realizing suppression of increase in consumption power. A semiconductor device has a signal line, a reception buffer circuit which is coupled to an end of the signal line and to which a signal is supplied from the signal line, and a delay element which is wired-OR coupled to an end of the signal line and shapes waveform of a signal at the end of the signal line.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: October 2, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Ryuichi Oikawa
  • Patent number: 10027089
    Abstract: An example system includes a first ring resonator element for imparting optical gain to a light signal. The example system farther includes a second ring resonator element optically coupled to the first ring resonator element for modulating the light signal. A waveguide can be optically coupled to one of the first ring resonator element or the second ring resonator element for receiving the light signal output from the one of the first ring resonator element or the second ring resonator element, and transmitting the received light signal.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: July 17, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Di Liang
  • Patent number: 9722818
    Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: August 1, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tao Wen Chung, Yuwen Swei, Chih-Chang Lin, Tsung-Ching Huang
  • Patent number: 9590562
    Abstract: A semiconductor amplifier bias circuit includes a first transmission line, a first grounded capacitor, a second transmission line and a power supply terminal. The first transmission line is connected to an output end part of the output matching circuit and the external load. The second transmission line includes one end part connected to the first transmission line and the other end part connected to the first grounded shunt capacitor. An electrical length of the second transmission line is approximately 90° at a center frequency of a band. The one end part is connected to the first transmission line at a position apart from the output end part by an electrical length of approximately 45° at the center frequency. The power supply terminal is connected to a connection point of the first grounded shunt capacitor and the other end part of the second transmission line.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: March 7, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 9391654
    Abstract: Systems and methods are provided for processing a time-domain signal in rectangular coordinates. The signal can include a low power desired signal and a high power, approximately constant envelope interference signal that spectrally overlaps the desired signal. A rectangular to polar converter can obtain magnitude and phase of the time-domain signal in polar coordinates. An interference estimator can estimate a magnitude of the interference signal based on the magnitude of the time-domain signal in polar coordinates. A subtractor can obtain a difference magnitude in polar coordinates based on the magnitude of the time-domain signal and the estimated magnitude of the interference signal in polar coordinates. A polar to rectangular converter can obtain the desired signal with reduced power of the interference signal based on the difference magnitude and phase of the time-domain signal in polar coordinates.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: July 12, 2016
    Assignee: The Aerospace Corporation
    Inventors: Peter S. Wyckoff, Philip Dafesh
  • Patent number: 9306548
    Abstract: A pulse generator generates a square-wave pulsed signal that has a variable pulse width. The pulse width, which is defined by the delay through a delay line, varies in response to variations in an input voltage, as well as in response to phase differences between a reference clock signal and a trigger signal.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: April 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Stefan Wlodzimierz Wiktor, Brian Thomas Lynch
  • Patent number: 9257956
    Abstract: A passive filter may include at least one elliptical filter unit and at least one asymmetric rejection filter unit coupled in series with the elliptical filter unit. The at least one asymmetric rejection filter unit may have a frequency response curve that includes a dip with different attenuations on either side, and an overshoot upon exiting the dip at the side with the lower attenuation.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: February 9, 2016
    Assignee: STMICROELECTRONICS SA
    Inventors: Jean-Christophe Ricard, Cedric Durand, Frederic Gianesello
  • Patent number: 9041440
    Abstract: A frequency tripler device is disclosed. The frequency tripler device includes a first graphene based field effect transistor (FET) of a first dopant type, having a gate, a drain, and a source, and a second graphene based FET of a second dopant type, having a gate, a drain, and a source, the gate of the first FET coupled to the gate of the second FET and coupled to an input signal having an alternating current (AC) signal of a first frequency, the combination of the first and second FETs generates an output signal with a dominant AC signal of a frequency of about three times the first frequency.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: May 26, 2015
    Assignee: Purdue Research Foundation
    Inventors: Joerg Appenzeller, Hong-yan Chen
  • Publication number: 20150130517
    Abstract: Frequency multipliers include a pair of transistors each connected to a common impedance through a respective collector impedance formed from a transmission line. Each transmission line has a length between about one quarter and about one eighth of a wavelength of an input signal frequency and is tuned to produce a large impedance at a collector of the respective transistor at the input signal frequency. The output frequency between the collector impedances and the common impedance is an even integer multiple of the input frequency.
    Type: Application
    Filed: January 2, 2015
    Publication date: May 14, 2015
    Inventors: Wooram Lee, ALBERTO VALDES GARCIA
  • Patent number: 8981822
    Abstract: Described is an apparatus comprising a plurality of logic units arranged in a ring, wherein an output terminal of each logic unit from the plurality of logic units is coupled to an input terminal of a next logic unit from the plurality of logic units, wherein the plurality of logic units includes a first multiple input logic unit having input nodes coupled to at least two output terminals of logic units from the plurality of logic units; and a plurality of latch units coupled to the output terminals of the plurality of logic units.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventor: Shenggao Li
  • Publication number: 20150070055
    Abstract: A received is disclosed that is capable of improving reception sensitivity while avoiding an increase in circuit scale. The receiver includes: a multi-phase local oscillation signal generating section that generates a plurality of local oscillation signals of different phases; a phase selection signal generating section that generates a phase selection signal used to select a baseband signal of a predetermined phase based on a detection result of a reception level of a high-frequency signal; and a frequency converter that frequency-converts the high-frequency signal based on the plurality of local oscillation signals, that generates a plurality of baseband signals of different phases, and that selects a baseband signal from among the plurality of baseband signals based on the phase selection signal.
    Type: Application
    Filed: December 25, 2013
    Publication date: March 12, 2015
    Inventors: Masahiro Kumagawa, Yoshifumi Hosokawa
  • Patent number: 8977519
    Abstract: A spectrum analyzer for measuring an RF signal over a selected frequency span configured to use multiple Intermediate Frequencies (IFs) for residual, spurious and image signal reduction. The spectrum analyzer has both a primary IF path and a secondary IF path configured to provide band pass filtering of the IF signals. A master clock synthesizer is configured to reduce residual noise by providing from a single Voltage Controlled Oscillator, a master clock signal and a Local Oscillator (LO) signal. The spectrum analyzer has a microcontroller configured to change the frequency of the master clock signal and the LO signal if the center frequency of the selected span is sufficiently close to a known spurious signal.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: March 10, 2015
    Assignee: Test Equipment Plus, Inc
    Inventor: Justin Crooks
  • Patent number: 8952732
    Abstract: A signal processor includes: a plurality of frequency converters which perform frequency conversion of input signals to output converted signals; and an output section which combines the converted signals output from the plurality of frequency converters and outputs a composite signal, wherein the plurality of frequency converters are formed in a one-chip semiconductor chip, and the plurality of frequency converters perform frequency conversion into converted signals in different frequency bands.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: February 10, 2015
    Assignee: Sony Corporation
    Inventor: Kenichi Kawasaki
  • Patent number: 8952733
    Abstract: A frequency multiplier circuit includes a first signal input terminal, a second signal input terminal, an output terminal, a power source terminal, a ground terminal, a main control circuit which is connected to the first signal input terminal, the second signal input terminal, the power source terminal and the ground terminal, a reference circuit which is connected to the power source terminal and the ground terminal, and a frequency synthesis circuit which is connected to the main control circuit, the reference circuit, the output terminal, the power source terminal and the ground terminal.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: February 10, 2015
    Assignee: IPGoal Microelectronics (Sichuan) Co., Ltd.
    Inventor: Fangping Fan
  • Patent number: 8941420
    Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: January 27, 2015
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Brian S. Leibowitz, Masum Hossain
  • Patent number: 8938204
    Abstract: The disclosed signal generator circuit has a four-phase signal generator circuit generating four-phase signals with a first frequency; an eight-phase signal generator circuit performing ½ frequency division of the four-phase signals to generate eight-phase signals with a second frequency; a first to a fourth harmonic rejection mixer circuits multiplying a first four-phase signal and a second four-phase signal of the four-phase signals by a first to a third eight-phase signals and a third to a fifth eight-phase signals of the eight-phase signals with mutually different combinations; a subtractor subtracting between outputs of the first and the fourth harmonic rejection mixer circuits to generate a first output signal with a third frequency; and an adder adding between outputs of the second and the third harmonic rejection mixer circuits to generate a second output signal with a third frequency whose phase is different from the first output signal by ?/2.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: January 20, 2015
    Assignee: Fujitsu Limited
    Inventor: Kazuaki Oishi
  • Patent number: 8933731
    Abstract: An adder circuit includes first through fourth two-bit adder modules, and first through third result mux blocks for receiving and adding first and second binary values to generate a final sum. A multiplier circuit that multiplies a multiplier and a multiplicand includes a multiplexer, an encoder connected to the multiplexer, a shifter connected to the encoder, and an accumulator connected to the encoder for receiving the multiplier and multiplicand and generating a multiplication product.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rohit Goyal, Amit Kumar Dey, Naman Gupta
  • Patent number: 8933732
    Abstract: Methods for increasing a signal frequency include generating two or more signals having a fundamental mode and one or more harmonics; phase shifting bifurcated components of the two or more signals in transmission lines; and combining the bifurcated components to create an output signal that cancels a fundamental mode, a second harmonic, and a third harmonic in the signals to produce a frequency-multiplied output signal.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Wooram Lee, Alberto Valdes Garcia
  • Patent number: 8917805
    Abstract: Frequency multipliers include a pair of transistors each connected to a common impedance through a respective collector impedance formed from a transmission line. Each transmission line has a length between about one quarter and about one eighth of a wavelength of an input signal frequency and is tuned to produce a large impedance at a collector of the respective transistor at the input signal frequency. The output frequency between the collector impedances and the common impedance is an even integer multiple of the input frequency.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wooram Lee, Alberto Valdes Garcia
  • Patent number: 8901973
    Abstract: A multi-band frequency multiplier configured to generate frequencies and multiplied frequencies in an integrated system. The multi-band frequency multiplier includes a multi-band multiplier core with a multiplier core differential amplifier configured to receive a multiplier input signal. A switchable load impedance connects to the multiplier core differential amplifier, and includes n multiplier sections. Each multiplier section includes a section impedance and a section switch. The multiplier core differential amplifier generates an output signal having a frequency substantially equal to k times the input frequency in a range of a selected one of n critical frequencies when a selected one of the section switches corresponding to the selected one of the n critical frequencies is triggered.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: December 2, 2014
    Assignee: Keysight Technologies, Inc.
    Inventors: Eric R. Ehlers, Bobby Yubo Wong
  • Patent number: 8896355
    Abstract: A variable-frequency input clock signal and a reference clock signal are compared during a frequency-compare interval to generate a value that indicates a ratio of their frequencies. The frequency-ratio value is then applied to configure a wide-range frequency-locking oscillator for operation with a narrowed input frequency range. Because the narrowed input frequency range is targeted to the input clock frequency, the wide-range oscillator is able to rapidly lock to a frequency multiple of the input clock frequency. Because the frequency-compare interval is also brief, an extremely fast-locking, clock-multiplying operation may be effected over a relatively wide range of input clock frequencies.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: November 25, 2014
    Assignee: Rambus Inc.
    Inventors: Yue Lu, Jared L. Zerbe
  • Patent number: 8890585
    Abstract: A frequency multiplier and associated method are provided, wherein the frequency multiplier includes a waveform generator and a slicer. The waveform generator generates a waveform in response to an input signal, and the slicer induces transitions in an output signal whenever the waveform crosses each of a plurality of reference levels, such that a frequency of the output signal is a multiple of a frequency of the input signal.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: November 18, 2014
    Assignee: MStar Semiconductor, Inc.
    Inventors: Jian-Yu Ding, Shih-Chieh Yen, Ming-Yu Hsieh, Yao-Chi Wang
  • Patent number: 8884664
    Abstract: An embodiment of a system for generating a low phase noise sine wave includes a variable signal source for generating a signal a series of octave dividing stages connected with the variable signal source, an input divider connected with the variable signal source, and a second series of octave dividing stages connected with an output of the pre-input frequency divider. Each octave dividing stage generating a successive octave of the generated signal using a frequency divider, a sine look up table, and a low pass filter.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 11, 2014
    Assignee: Anritsu Company
    Inventor: Donald Anthony Bradley
  • Patent number: 8878575
    Abstract: A noise reduction filter is inserted between the source and non-linear transmission line (NLTL) in a frequency multiplier to improve phase noise performance. The noise reduction filter is suitably coupled directly to the input of the NLTL. The noise reduction filter and the output BPF are suitably low complexity filters.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: November 4, 2014
    Assignee: Raytheon Company
    Inventors: Joel Charles Blumke, Ray Soloman Skaggs, Lawrence Wayne Tiffin, Christian Maldonado-Echevarria
  • Patent number: 8872553
    Abstract: A frequency multiplier includes: a multiphase signal generator configured to generate multiphase signals in response to a source signal; a pulse generator configured to generate a plurality of pulse signals in response to the multiphase signals; and a synthesizer configured to generate a frequency multiplication signal in response to edges of the pulse signals. Each of the plurality of pulse signals is generated in response to a corresponding multiphase signal, and the frequency multiplication signal is obtained by multiplying a frequency of the source signal.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: October 28, 2014
    Assignee: SK Hynix Inc.
    Inventor: Ji Wan Jung
  • Publication number: 20140312937
    Abstract: A multi-band frequency multiplier configured to generate frequencies and multiplied frequencies in an integrated system. The multi-band frequency multiplier includes a multi-band multiplier core with a multiplier core differential amplifier configured to receive a multiplier input signal. A switchable load impedance connects to the multiplier core differential amplifier, and includes n multiplier sections. Each multiplier section includes a section impedance and a section switch. The multiplier core differential amplifier generates an output signal having a frequency substantially equal to k times the input frequency in a range of a selected one of n critical frequencies when a selected one of the section switches corresponding to the selected one of the n critical frequencies is triggered.
    Type: Application
    Filed: April 19, 2013
    Publication date: October 23, 2014
    Applicant: Agilent Technologies, Inc.
    Inventors: Eric R. Ehlers, Bobby Yubo Wong
  • Publication number: 20140312938
    Abstract: A frequency multiplier includes: a multiphase signal generator configured to generate multiphase signals in response to a source signal; a pulse generator configured to generate a plurality of pulse signals in response to the multiphase signals; and a synthesizer configured to generate a frequency multiplication signal in response to edges of the pulse signals. Each of the plurality of pulse signals is generated in response to a corresponding multiphase signal, and the frequency multiplication signal is obtained by multiplying a frequency of the source signal.
    Type: Application
    Filed: August 20, 2013
    Publication date: October 23, 2014
    Applicant: SK hynix Inc.
    Inventor: Ji Wan JUNG
  • Publication number: 20140292381
    Abstract: A frequency tripler device is disclosed. The frequency tripler device includes a first graphene based field effect transistor (FET) of a first dopant type, having a gate, a drain, and a source, and a second graphene based FET of a second dopant type, having a gate, a drain, and a source, the gate of the first FET coupled to the gate of the second FET and coupled to an input signal having an alternating current (AC) signal of a first frequency, the combination of the first and second FETs generates an output signal with a dominant AC signal of a frequency of about three times the first frequency.
    Type: Application
    Filed: March 3, 2014
    Publication date: October 2, 2014
    Applicant: PURDUE RESEARCH FOUNDATION
    Inventors: Joerg Appenzeller, Hong-yan Chen
  • Patent number: 8841944
    Abstract: A symmetric frequency multiplier includes four non-linear devices configured to receive an input signal having a fundamental mode and to provide an output having one or more harmonics; and three collinear transmission lines, each having a length of about one quarter of an input wavelength, configured to receive the outputs of the non-linear devices and configured to combine bifurcated components of the signals from the non-linear devices into two frequency-multiplied output signals. Two of the signals from the non-linear devices are provided at respective ends of the collinear transmission lines and two of the signals from the non-linear devices are provided between transmission lines, such that each of the bifurcated components of a given signal passes through a different subset of the transmission lines.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wooram Lee, Alberto Valdes Garcia
  • Publication number: 20140266329
    Abstract: A symmetric frequency multiplier includes four non-linear devices configured to receive an input signal having a fundamental mode and to provide an output having one or more harmonics; and three collinear transmission lines, each having a length of about one quarter of an input wavelength, configured to receive the outputs of the non-linear devices and configured to combine bifurcated components of the signals from the non-linear devices into two frequency-multiplied output signals. Two of the signals from the non-linear devices are provided at respective ends of the collinear transmission lines and two of the signals from the non-linear devices are provided between transmission lines, such that each of the bifurcated components of a given signal passes through a different subset of the transmission lines.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 18, 2014
    Applicant: International Business Machines Corporation
    Inventors: Wooram Lee, Alberto Valdes Garcia
  • Publication number: 20140266331
    Abstract: A circuit includes an oscillation generation circuit, a distribution circuit, and a transceiver circuit. The oscillation generation circuit is configured to generate a first oscillation signal having a first frequency. The distribution circuit includes a voltage to current stage, a transmission portion and a current to voltage stage. The voltage to current stage is configured to receive the first oscillation signal, and convert the first oscillation signal into a current form. The transmission portion is configured to transmit the first oscillation signal in the current form. The current to voltage stage is configured to receive the first oscillation signal in the current form and generate a second oscillation signal having a sub-harmonic frequency of the first frequency, such as half of the first frequency. The transceiver circuit is configured to operate in a frequency band responsive to the second oscillation signal.
    Type: Application
    Filed: June 2, 2014
    Publication date: September 18, 2014
    Applicant: Marvell World Trade Ltd.
    Inventors: Himanshu ARORA, Paolo ROSSI, Jae Yong KIM