With Particular Tube Or Distributed Parameter Element Patents (Class 327/123)
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Patent number: 11012038Abstract: A plurality of transmission lines (3b,3c) are connected to a transistor (1) and have different characteristic impedances. A plurality of open stubs (4a,4b) are connected to the plurality of transmission lines (3b,3c) respectively. A length of each open stub (4a,4b) is shorter than a length of each transmission line (3b,3c).Type: GrantFiled: January 12, 2017Date of Patent: May 18, 2021Assignee: Mitsubishi Electric CorporationInventor: Takao Haruna
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Patent number: 9041440Abstract: A frequency tripler device is disclosed. The frequency tripler device includes a first graphene based field effect transistor (FET) of a first dopant type, having a gate, a drain, and a source, and a second graphene based FET of a second dopant type, having a gate, a drain, and a source, the gate of the first FET coupled to the gate of the second FET and coupled to an input signal having an alternating current (AC) signal of a first frequency, the combination of the first and second FETs generates an output signal with a dominant AC signal of a frequency of about three times the first frequency.Type: GrantFiled: March 3, 2014Date of Patent: May 26, 2015Assignee: Purdue Research FoundationInventors: Joerg Appenzeller, Hong-yan Chen
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Publication number: 20140166868Abstract: TeraHertz signal generation system based on traveling-wave oscillators providing extraction of orders of magnitude higher oscillation frequencies resulting in frequency multipliers and THz transceivers that can generate, transmit and sense THz frequency signals for sensing/imaging.Type: ApplicationFiled: December 17, 2012Publication date: June 19, 2014Inventors: Ahmet Tekin, Ahmed Emira, Suat Utku Ay
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Patent number: 8018290Abstract: An output terminal 6 is provided at the connecting point 5 between the collector terminal of a transistor 1 and an open-ended stub 4 by connecting the open-ended stub 4 to the collector terminal of the transistor 1, the open-ended stub 4 having a line length equal to a quarter of the wavelength of a signal of frequency 2N·F0 or 2N times the oscillation frequency F0. In addition, an output terminal 9 is provided at a connecting point 8 located at a distance equal to a quarter of the wavelength of a signal of oscillation frequency F0 from the end of an open-ended stub 7 by connecting the open-ended stub 7 to the base terminal of the transistor 1, the open-ended stub 7 having a line length longer than a quarter of the wavelength of the signal of oscillation frequency F0.Type: GrantFiled: October 15, 2007Date of Patent: September 13, 2011Assignee: Mitsubishi Electric CorporationInventors: Hiroyuki Mizutani, Kazuhiro Nishida, Masaomi Tsuru, Kenji Kawakami, Morishige Hieda, Moriyasu Miyazaki
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Patent number: 6998941Abstract: The invention can be used for telecommunications, measuring and other devices in order to produce stable superhigh frequency signals. An IMPATT diode (4) operating in the cascade break-down mode and having a sharp nonlinearity transforms an input signal in such a way that ultraharmonics which multiple in respect to the frequency of an input signal ?0 occur in a frequency spectrum. An output stage of a multiplier is used in order to separate an output n?0 frequency and to suppress adjacent frequencies. In order to tune the output stage to the n?0 frequency, a tuning plug (8) and short-circuiting pistons (13) are used. The tuning plug (8) is arranged above an upper electrod of the IMPATT diode (4) (inside the axis of the diode). The tuning plugs (13) make it possible to tune resonance capacitance to the n?0 frequency and remove energy towards the output part of a T-bend in which a wave guide pass-band filter (15) is disposed.Type: GrantFiled: March 26, 2002Date of Patent: February 14, 2006Inventors: Sergey Borisovich Maltsev, Daniil Olegovich Korneev
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Publication number: 20040222826Abstract: A data form converter allowing parallel-to-serial or serial-to-parallel conversion at various conversion ratios is disclosed. A frequency divider divides an input clock in frequency at a variable frequency division ratio to produce a single frequency-divided clock. A data shift circuit shifts serial input data according to the input clock to output n-bit parallel data, where n is determined depending on the variable frequency division ratio. A retiring section synchronizes the n-bit parallel data with the single frequency-divided clock to output parallel output data.Type: ApplicationFiled: May 10, 2004Publication date: November 11, 2004Applicants: NEC Corporation, NEC Electronics CorporationInventors: Masahiro Takeuchi, Takanori Saeki, Kenichi Tanaka
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Patent number: 6597231Abstract: The present invention provides a semiconductor switching circuit and a semiconductor device using the switching circuit that can maintain sufficient isolation characteristics even when dealing with high frequency signals. The semiconductor switching circuit includes a first semiconductor switching element connected between a first terminal and a second terminal, a second semiconductor switching element, one end of the second switching element being connected to one of the first and second terminals, and an open stub connected to the other end of the second switching element.Type: GrantFiled: July 26, 2001Date of Patent: July 22, 2003Assignee: Murata Manufacturing Co., Ltd.Inventor: Takahiro Tsutsumi
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Patent number: 6529051Abstract: A damping resistance 20 is connected between the drain D of an FET 10 and a first end T3 of an output transmission line 13, and a damping resistance 21 is connected between the drain D of an FET 11 and the first end T3. The source of the FET 10 and the gate of the FET 11 are connected to a ground plane on the back surface of a substrate through a via which has a parasitic inductance when a multiplied frequency exceeds 20 GHz. The gate of the FET 10 and the source of the FET 11 receive microwaves of the same frequency and phase through an input transmission line 12.Type: GrantFiled: February 27, 2001Date of Patent: March 4, 2003Assignee: Fujitsu Quantum Devices LimitedInventors: Tsuneo Tokumitsu, Osamu Baba
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Patent number: 6388546Abstract: This invention provides a multistage frequency multiplier having a plurality of frequency doublers. Each doubler incorporates a three-terminal transistor device and is connected to an adjacent doubler via an interstage network. The network comprises a transmission line having its electrical parameters selected to achieve conjugate impedance matching at the intermediate harmonic frequency generated by the corresponding doubler. This network also includes a quarter-wavelength open-ended stub for suppressing a main input frequency component received by the corresponding frequency doubler. A shunt resistor on the transistor gate is preferably used to stabilize the network. This interstage network simplifies overall circuit topology to reduce total circuit size, and provides increased drive power levels to permit broader bandwidth and stabilize required output level from a local oscillator.Type: GrantFiled: September 3, 1999Date of Patent: May 14, 2002Assignees: Her Majesty The Queen In Right of Canada as represented by The Minister of Industry through the Communications Research Centre, The Communications Research Laboratory of the Ministry of Posts and Telecommunications, JapanInventors: Masahiro Kikokawa, Malcolm G. Stubbs
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Frequency multiplier capable of taking out efficiently and stably harmonics higher than fourth order
Patent number: 6369675Abstract: One end of a first transmission line is connected to the collector of an HBT with the base connected to an output terminal of an input-side matching circuit and with the emitter grounded, and one end of an end-open stub for blocking the passage of the doubled wave is connected to the other end of the first transmission line. One end of a second transmission line is connected to the other end of the first transmission line, and one end of an end-open stub for blocking the passage of the fundamental wave is connected to the other end of the second transmission line. An input terminal of an output-side matching circuit is connected to the other end of the second transmission line.Type: GrantFiled: January 12, 2001Date of Patent: April 9, 2002Assignee: Sharp Kabushiki KaishaInventor: Atsushi Yamada -
Patent number: 6297716Abstract: A switched frequency multiplier receives pulses of pump energy as an input signal. The input signal is transferred to within a housing having a first cavity tuned to the frequency of the pump signal and a second cavity which is tuned to a harmonic of the input signal and is enclosed within the first cavity. An outlet port couples the second tuned cavity to a waveguide which includes a Q-switch that can be turned on and off. The interior of the housing has a planar grid of layers which includes a layer of nonlinear material and a frequency selective layer. The frequency selective layer is transparent to the input signal but reflective to the harmonic output signal thereby trapping energy in the second cavity. The multiplier operates by receiving a pump pulse and storing the energy while the Q-switch is closed. When the Q-switch is opened near the end of the pump pulse, the stored energy is suddenly released to produce a relatively high energy harmonic pulse having a shorter duration than the pump pulse.Type: GrantFiled: December 16, 1999Date of Patent: October 2, 2001Assignee: Lockheed Martin CorporationInventor: James Richard Wood
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Frequency multiplier capable of taking out efficiently and stably harmonics higher than fourth order
Patent number: 6198365Abstract: One end of a first transmission line is connected to the collector of an HBT with the base connected to an output terminal of an input-side matching circuit and with the emitter grounded, and one end of an end-open stub for blocking the passage of the doubled wave is connected to the other end of the first transmission line. One end of a second transmission line is connected to the other end of the first transmission line, and one end of an end-open stub for blocking the passage of the fundamental wave is connected to the other end of the second transmission line. An input terminal of an output-side matching circuit is connected to the other end of the second transmission line.Type: GrantFiled: November 16, 1999Date of Patent: March 6, 2001Assignee: Sharp Kabushiki KaishaInventor: Atsushi Yamada -
Patent number: 6066997Abstract: A frequency multiplier is constructed to input an input signal to a transistor through an input matching circuit and to output a multiplied output signal from the transistor through a reflecting type fundamental wave signal band suppressing circuit and an output matching circuit. A transmission line produces a standing wave and is disposed between the output terminal of the transistor and the input terminal of the reflecting type fundamental wave signal band suppressing circuit. Because the voltage acting on the output terminal of the transistor consequently increases, the transistor operates at a point at which the nonlinearity of its input-output characteristic is greater and the output power of the multiplied output signal increases.Type: GrantFiled: September 12, 1997Date of Patent: May 23, 2000Assignee: Denso CorporationInventors: Kazuoki Matsugatani, Manabu Sawada, Kunihiko Sasaki
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Patent number: 5886595Abstract: An odd order MESFET frequency multiplier which outputs a desired odd harmonic of a fundamental tone. The frequency multiplier includes a multiplier stage with a MESFET having a harmonic response dependent upon a plurality of bias conditions and the input RF power level. The MESFET includes a drain port coupled to an output matching network sized and configured for a predetermined load at a selected output frequency. The output matching network includes RF shorts for reflecting energy to the MESFET from a plurality of undesired even harmonics. Coupled to the output matching circuit is a bandpass filter sized and configured for the predetermined load. The bandpass filter includes RF shorts for reflecting energy to the MESFET from a plurality of undesired odd harmonics, wherein the reflected energy from the undesired even harmonics and the undesired odd harmonics are combined at the MESFET to provide additional energy at the desired odd harmonic.Type: GrantFiled: April 21, 1997Date of Patent: March 23, 1999Assignee: Raytheon CompanyInventor: Ofira M. Von Stein
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Patent number: 5821802Abstract: A transformer-coupled mixer circuit including dc voltage supply; and four transistors, arranged as a first transistor pair and a second transistor pair. Each transistor pair has a first transistor and a second transistor and each transistor has a base, a collector and an emitter. The emitter of the first transistor in each transistor pair is connected to the collector of the second transistor in that transistor pair, and the emitter of the second transistor in each transistor pair is connected to a current sink. The circuit also comprises a transformer, having a set of primary windings and first and second sets of secondary windings, the first set of secondary windings being connected in series with the emitter of the first transistor in the first transistor pair and the second set of secondary windings being connected in series with the emitter of the first transistor in the second transistor pair.Type: GrantFiled: April 18, 1997Date of Patent: October 13, 1998Assignee: Northern Telecom LimitedInventor: Gregory Weng Mun Yuen
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Patent number: 5731752Abstract: A microwave signal frequency multiplier is used to produce a harmonic signal derived from a microwave pump signal. In a selected embodiment, a Ka pump signal is converted to a W band microwave signal. The frequency signal multiplier includes a housing having a signal input port and a harmonic signal extraction port. The interior of the housing comprises a pump signal cavity which is tuned to the pump signal. Within the pump signal cavity, there is provided a non-linear material which converts the pump signal to a harmonic, preferably a third harmonic, of the pump signal. A frequency selective barrier within the pump signal cavity defines a harmonic signal cavity. An extraction port is coupled to the harmonic signal cavity for removing the harmonic signal from the multiplier. The frequency selective barrier is essentially transparent to the pump signal but is reflective to the harmonic signal.Type: GrantFiled: April 17, 1996Date of Patent: March 24, 1998Assignee: Loral Vought Systems CorporationInventor: James Richard Wood
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Patent number: 5392014Abstract: An input signal specified by an input frequency is divided by an out-of-phase type input hybrid coupler, into two divided signals with regard to the power of the input signal, where the divided signals have different phases. The input frequency of each of the divided signals is multiplied by a frequency multiplier connected with the input hybrid coupler, producing frequency multiplied signals each specified by the multiplied frequency. The frequency multiplied signals are composed by an out-of-phase type output hybrid coupler with regard to power, producing an output signal specified by the multiplied frequency. A phase shifter is provided between the input and the output hybrid coupler for varying the phase difference between the frequency multiplied signals, so that the frequency multiplied signals are composed in in-phase.Type: GrantFiled: March 1, 1993Date of Patent: February 21, 1995Assignee: Fujitsu LimitedInventors: Haruki Nishida, Yoshiaki Nakano, Shin Watanabe