Abstract: Techniques are disclosed related to determining delay in a radio frequency (RF) communications device configured to perform envelope tracking. The RF communications device may comprise a power amplifier and an envelope tracker. First and second input stimuli signals may be transmitted to each of the power amplifier and envelope tracker, respectively. The RF communications device may output, by the power amplifier, an output signal to a vector signal analyzer (VSA). The VSA may determine a first delay offset by cross-correlating the output signal with a reference signal, and the VSA may determine a second delay offset based on an amplitude distortion of the output signal. A relative delay between the first and second input stimuli signals may be determined based on a difference between the first and second delay offsets.

Abstract: An open loop envelope tracking system calibration technique and circuitry are proposed. A radio frequency power amplifier receives a modulated signal. An envelope tracker power converter generates a modulated power amplifier supply voltage for the radio frequency power amplifier based on a control signal derived from the modulated signal. A first output power and a second output power of the radio frequency power amplifier are measured when the control signal is respectively delayed by a first delay period and a second delay period. A sensitivity of the output power of the radio frequency power amplifier is near a maximum near the first delay period and the second delay period. The first delay period and/or the second delay period are adjusted until the first output power substantially equals the second output power. The first delay period and the second delay period are used to obtain a calibrated fine tuning delay offset.

Abstract: A fully integrated ramp generator circuit includes a first current generator that sources current to first capacitor through a first transistor that is gate controlled by the complement of a periodic signal. The ramping voltage stored on the first capacitor is buffered to an output node as a ramp output signal. A second transistor couples the output node to the first current generator and is gate controlled by the periodic signal. The periodic signal is generated at the output of a flip-flop that receives an input clock signal and reset signal. The reset signal is generated by a comparator circuit operable to compare the voltage on a second capacitor to a reference. The second capacitor is charged by a second current source and discharged by a third transistor that is gate controlled by the periodic signal.

Abstract: A method for generating a ramp comprises providing a voltage reference source, providing a summing amplifier, providing n switched capacitor elements coupled in parallel between the voltage reference source and the summing amplifier, and selectively activating a predetermined number of the switched capacitor elements to first store charge on each activated switched capacitor element and then to measure the sum of the charges on the activated capacitor switch elements in each of a fixed-integer number of time slots in a cyclical manner, the predetermined number being between 0 and n.

Abstract: High speed serial link techniques are provided. A system applying the high speed serial link technique comprises a relay unit and an amplifier. The relay unit receives a first pair of differential signals provided by a high speed transmitter of a first device, and provides the amplifier with at least one signal that is generated based on the first pair of differential signals. The amplifier amplifies and converts the signal provided by the relay unit to a second pair of differential signals to be received by a high speed receiver of a second device.

Abstract: Embodiments of the present disclosure relate to methods, systems and apparatus for implementing dithering in motor drive system for controlling operation of a multi-phase electric machine.

Abstract: An apparatus according to an embodiment of the present invention includes a conversion unit configured to generate electric charge, a first amplification unit configured to amplify a signal corresponding to an amount of the electric charge and output a first amplified signal, a second amplification unit configured to amplify the first amplified signal and output a second amplified signal, a current source shared by the first amplification unit and the second amplification unit, and a selection unit configured to bring the first amplification unit and the second amplification unit into an inactive state. The current source is shared by the first amplification unit and the second amplification unit. The number of current sources is therefore reduced. This leads to the reduction in power consumption.

Abstract: A timing controller includes a controller that controls an operation timing of a controlled unit, and a setting unit that associates a timing obtained by dividing a setting of the operation timing into a plurality of timings, each timing having an identification number, and sets the control unit so that an offset period based on the associated timing is added to the operation timing of the controlled unit.

Abstract: Provided are a converter circuit and a method of driving the same. The converter circuit includes: an input unit receiving a conversion target signal; a detection unit receiving a conversion target signal for each interval from the input unit, sampling the conversion target signal for each interval according to a plurality of timings to calculate an average value for each interval, and outputting a comparison unit input signal by using the average value for each interval; and a comparison unit comparing the comparison unit input signal with a predetermined reference signal to output a comparison result value.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves. Methods are provided for deskewing, equalizing, and boosting the differential signals in the embedded circuits that are mounted on a PCB.

Abstract: The invention describes an electric circuit (100), a method and a computer program for hot-swapping an electronic board in a telecommunication system, where the increase in current in the electric circuit is controlled by a microcontroller (130) switching a power transistor in a switching circuit (150) so as to gradually increase the capacitor voltage for the electronic board. The current level is measured either in the microcontroller (130) itself or in an external current sense circuit (140) and compared to a maximum current level.

Abstract: Embodiments for at least one method and apparatus of a wireless transceiver are disclosed. For one embodiment, the wireless transceiver includes a transmit chain, wherein the transmit chain includes a power amplifier. The wireless transceiver additionally includes a receiver chain that is tunable to receive wireless signals over at least one of multiple channels, wherein the multiple channels are predefined. Further, the wireless transceiver includes a voltage converter. The voltage converter provides a supply voltage to the power amplifier, and operates at a single switching frequency, wherein the single switching frequency and all harmonics of the single switching frequency fall outside of the multiple channels.

Abstract: An integrated circuit (IC) type voltage signal converter is provided for integrating with other ICs. The signal converter includes a first chopper circuit module, a second chopper circuit module, a full wave combining module, and a zero point detecting circuit module. Each of the circuit modules may be formed by an IC module. The first and second chopper circuit modules are composed of differential operational amplifiers for converting a high voltage signal into first and second low voltage half wave signals. The full wave combining module combines the first and second low voltage half wave signals to obtain a full wave signal. The zero point detecting circuit module converts the first and second low voltage half wave signals into a square wave having the same frequency of the high voltage signal.

Abstract: Receiver architectures and bias circuits for a data processor are provided. A receiver architecture includes a linear receiver having a first input node for a data (DQ) signal, a second input node for a reference voltage, and output nodes for a differential output signal. The linear receiver compares the DQ signal to the reference voltage, and generates the differential output signal in response to the comparison. A sense amplifier is coupled to the linear receiver. The sense amplifier has input nodes connected to the output nodes of the linear receiver, and an output node for a binary output signal having voltage characteristics compatible with the processor. The sense amplifier transforms the differential output signal into the binary output signal. The receiver architecture also includes a programming architecture coupled to the linear receiver to set operating characteristics of the linear receiver.

Abstract: A buffer circuit buffers incoming signals, from a local oscillator generator to a mixing circuit and has a push-pull circuit having two inputs, a first being coupled to a first incoming signal, and a second of the inputs being coupled to one of the buffered versions of the incoming signals, having a phase related to that of the first incoming signal. By coupling a second input to a buffered version rather than to the incoming signal, the load presented to the preceding circuit can be halved, while maintaining reduced power consumption. By using as a second input, a signal which is phase related to the first incoming signal, the normal operation of the push-pull circuit can be maintained. The incoming signals from the LO generator can be differential IQ signals and the buffered version of the further incoming signal be in phase with the first incoming signal.

Abstract: An interface circuit for a multi-differential embedded-clock channel for communicating data provides efficient utilization of the bandwidth of the channel. The interface circuit includes at least four first signals, at least four second signals, and a multi-differential amplifier. The multi-differential amplifier is coupled to the first and second signals. The multi-differential amplifier is adapted to generate the second signals by amplifying, for all combinations of two of the first signals, differential transitions between the two of the first signals. Each of a plurality of symbols of the data has a corresponding one of the differential transitions, and the differential transitions are serially communicated through the channel.

Abstract: Methods and apparatuses for detecting digital signals in high speed signaling systems. In at least one embodiment, at least one received input signal is combined with a plurality of predetermined reference signals according to a plurality of prior digital signal output states to generate a signal for detecting a present digital signal output state. In one aspect of the invention, a method for determining a digital signal state in a differential signaling system includes: comparing a first differential input signal to a second differential input signal; determining a prior digital signal output state; comparing the first differential input signal to one of a first reference voltage and a second reference voltage; comparing the second differential input signal to one of the first reference voltage and the second reference voltage; and determining a present digital signal output state from the prior digital signal output state and from all of the comparisons.

Abstract: Briefly, a transmitter that includes first and second fractional N synthesizers that may generate outphased modulated signals. First and second sigma-delta modulators may control the modulation of the first and second fractional N synthesizers.

Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: A PAM-4 data slicer includes first, second, and third comparators which provide first, second, and third thresholds, respectively. Each of the comparators has an offset. The first and third comparators have an offset generating arrangement at their outputs to provide the first and third comparator circuits with symmetrical offsets.

Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

Abstract: A method and an apparatus for the detection of the current distribution in at least one conductor (W1, W2) of an electric machine are specified, which indirectly permit, in a simple manner, the metrological determination of said distribution. The conductors or Roebel bars (W1, W2) are arranged in a slot (4) of a stator laminate stack (3) of the electric machine and each has a plurality of mutually electrically insulated and transposed conductor elements (W1nl, W1nr; W2nl, W2nr). A probe holder (6) which can be displaced radially with regard to the electric machine and contains, in recesses, 2 magnetic field probes (M1, M2) with a predeterminable center-to-center distance (d) is provided, adjacent to these conductors (W1, W2) in a probe channel (17) within the slot (4). The magnetic transverse field within the slot (4) is measured using said probes.