Abstract: Systems and apparatus may carry out analysis of battery physical phenomena, and characterize batteries based on phenomena occurring in particular time and/or frequency domains. These systems may be additionally responsible for charging and/or monitoring a rechargeable battery. Examples of battery physical phenomena include mass transport (e.g., diffusion and/or migration) in battery electrolytes, mass transport in battery electrodes, and reactions on battery electrodes.

Abstract: The present inventions, in one aspect, are directed to techniques and/or circuitry to applying a charge pulse to the terminals of the battery during a charging operation, measure a plurality of voltages of the battery which are in response to the first charge pulse, determine a charge pulse voltage (CPV) of the battery, wherein the charge pulse voltage is a peak voltage which is in response to the first charge pulse, determine whether the CPV of the battery is within a predetermined range or greater than a predetermined upper limit value and adapt one or more characteristics of a charge packet if the CPV is outside the predetermined range or is greater than a predetermined upper limit value.

Abstract: A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.

Abstract: A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the keeper circuit of the first latch and is cross-coupled with the gates of the keeper circuit of the first latch. The latch is hardened against single event upsets and an arbitrary number of successive SEUs attacking a single node, provided that the time between successive SEUs is larger than the recovery time of the latch. An alternate embodiment of the hardened latch includes a split buffer output. This embodiment is capable of reducing the propagation of erroneous transients. Another alternate embodiment of the hardened latch includes a Miller C buffer output. This embodiment is capable of reducing the propagation of erroneous transients below the level achievable in a hardened latch employing a split buffer output.

Abstract: A transmitting device generates a modulation signal depending on data to be transmitted. The transmitting device includes a transmission frequency generation device that is controlled depending on the signal in order to produce a transmission frequency corresponding to the modulation signal. A calibration device is provided for automatically calibrating the amplitude of the modulation signal during the operation of the transmitting device. This eliminates time-consuming and therefore costly adjustment steps during the production of the transmitting device.

Abstract: An unclocked, digital sequencer circuit having flexibly ordered leading and trailing edges on the output signals. The sequencer circuit of the invention includes a dual-input latch that detects only leading edges on a first input terminal and only trailing edges on a second input terminal. A delay line provides successively delayed input signals. Two delayed input signals are coupled to the first and second input terminals of each of two or more dual-input latches that provide a set of sequencer output signals. The sequence of the output signal edges depends on which delayed input signals are selected to drive each dual-input latch. In one embodiment, the selection of delayed input signals to drive the first and second input terminals of the dual-input latches is programmable. Thus, the sequence of the leading edges on the output signals is programmable, and the sequence of the trailing edges is independently programmable.

Abstract: The signal regeneration circuit recovers a digital signal from an input signal that is supplied via metallic isolation (galvanic separation). The circuit has two input terminals for the input signal and one output terminal for the recovered digital signal. A current direction sensor detects the current direction prevailing between the input terminals and outputs the signal in accordance with the last prevailing current direction. The circuit is advantageously used in connection with digital circuits that require potential isolation at their input terminals.