Specific Signal Discriminating (e.g., Comparing, Selecting, Etc.) Without Subsequent Control Patents (Class 327/1)
  • Patent number: 10145819
    Abstract: The present invention provides a method for a method for measuring the properties of liquid based on a quartz crystal microbalance sensor, which employs two measurements to obtain two frequency shifts of the QCM sensor induced by two different volume of the sample liquid. The present invention creatively established the relationship between the density and viscosity of sample liquid and the frequency shifts of QCM sensor. With present invention, the density and viscosity of sample liquid can be obtained through two frequency shifts. Comparing to the conventional liquid property measurement. The measuring procedure of present invention are more simple, and the measuring results are more accurate. Moreover, the present invention consumes less volume of sample liquid, and has the features such as online, real time and quantitative.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: December 4, 2018
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Feng Tan, Duyu Qiu, Peng Ye, Hao Zeng, Yong Zhao, Jun Jiang, Huiqing Pan, Lianping Guo, Shuhao Wu
  • Patent number: 10003332
    Abstract: A drive control device includes a MOS transistor, voltage measuring circuits, a correction circuit, and a control circuit. The voltage measuring circuits measure a drain-to-source voltage when a forward drain current flows through the MOS transistor and when a reverse drain current flows in the MOS transistor. The correction circuit sets a current setting voltage level when the reverse drain current flows, where the current setting voltage level is proportional to the voltage between the drain and the source when a predetermined reverse setting current flows in the MOS transistor. The control circuit controls ON/OFF of the MOS transistor in response to a control signal reflecting a measured value of the first voltage measuring circuit when the forward drain current flows through the MOS transistor and the current setting voltage level that is set by the correction circuit when the reverse drain current flows in the MOS transistor.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: June 19, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideki Kimura
  • Patent number: 9973178
    Abstract: In a clock frequency doubler, an input clock feeds into a digital programmable delay circuit, and an inverted input clock feeds into another digital programmable delay. The outputs of these digital programmable delay circuits are combined with the input clock and inverse clock through AND gates in order to generate clock pulses at both the rising and falling edge of the clock. These signals are combined using an OR gate to provide an output clock signal with a frequency that is double the frequency of the input clock signal. The values of the control bits for the digital programmable delay circuit are determined in a time-to-digital conversion (TDC) circuit that includes a Successive Approximation Register (SAR). For every cycle of the clock, the SAR circuit successively sets the programmable delay control bits and compares the delay circuit output with the input clock to determine the value of the control bits.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: May 15, 2018
    Assignee: Nuvoton Technology Corporation
    Inventor: Peter J. Holzmann
  • Patent number: 9947388
    Abstract: Described is an apparatus which comprises: a bit-line (BL) read port; a first local bit-line (LBL) coupled to the BL read port; a second LBL; and one or more clipper devices coupled to the first and second LBLs. The apparatus allows for low swing bit-line to be used for large signal memory arrays. The low swing operation enables reduction in switching dynamic capacitance. The apparatus also describes a split input NAND/NOR gate for bit-line keeper control which achieves lower VMIN, higher noise tolerance, and improved keeper aging mitigation. Described is also an apparatus for low swing write operation which can be enabled at high voltage without degrading the low voltage operation.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkarni, Iqbal R. Rajwani, Eric K. Donkoh
  • Patent number: 9843414
    Abstract: For low complexity error correction, a decoder modifies each reliability metric of an input data stream with a random perturbation value. The reliability metric comprises a weighted sum of a channel measurement for the input data stream and parity check results for the input data stream. In addition, the decoder may generate an output data stream as a function of the reliability metrics.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: December 12, 2017
    Assignee: Utah State University
    Inventors: Chris Winstead, Gopalakrishnan Sundararajan, Emmanuel Boutillon
  • Patent number: 9781022
    Abstract: Presented is a system for monitoring the integrity of a communication bus.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: October 3, 2017
    Assignee: Sital Technology Ltd.
    Inventor: Ofer Hofman
  • Patent number: 9722608
    Abstract: Various systems may benefit from interfaces for handling multiple types of inputs. For example, a device with a trigger input from an external device may benefit from an isolated logic level trigger that is capable of addressing multiple types and values of voltage. An apparatus can include an input configured to receive an external trigger input signal having a trigger input voltage. The apparatus can also include circuitry configured to automatically adjust the trigger input voltage to a value configured to be compatible with a provided attached system. A working range of the trigger input voltage can exceed a compatible working range of the provided attached system.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: August 1, 2017
    Assignee: Mercury Systems Inc.
    Inventor: Robert V. Lazaravich
  • Patent number: 9698728
    Abstract: Several circuits and methods for transferring an input data signal in a digital isolator are disclosed. In an embodiment, the digital isolator includes an isolation element, input circuit, and output circuit. The isolation element includes at least one input node and at least one output node, the input circuit is electronically coupled to the input node and generates modulated differential data signals based on modulating the input data signal on a carrier signal. The input circuit operates using a first supply voltage with respect to a first ground. The output circuit is electronically coupled to the output node to receive the modulated differential data signals, operates using a second supply voltage with respect to a second ground and includes a frequency-shift keying demodulator configured to generate a demodulated data signal in response to detection of presence of the carrier signal. The output circuit further generates an output data signal.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: July 4, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anant Shankar Kamath, Sreeram N S
  • Patent number: 9577816
    Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: February 21, 2017
    Assignee: Rambus Inc.
    Inventors: Masum Hossain, Brian Leibowitz, Jihong Ren
  • Patent number: 9437092
    Abstract: Various apparatus and methods for smoke detection are disclosed. In one embodiment, a method of training a classifier for a smoke detector comprises inputting sensor data from a plurality of tests into a processor. The sensor data is processed to generate derived signal data corresponding to the test data for respective tests. The derived signal data is assigned into categories comprising at least one fire group and at least one non-fire group. Linear discriminant analysis (LDA) training is performed by the processor. The derived signal data and the assigned categories for the derived signal data are inputs to the LDA training. The output of the LDA training is stored in a computer readable medium, such as in a smoke detector that uses LDA to determine, based on the training, whether present conditions indicate the existence of a fire.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: September 6, 2016
    Assignee: UT-Battelle, LLC
    Inventors: Robert J. Bruce Warmack, Dennis A. Wolf, Steven Shane Frank
  • Patent number: 8811502
    Abstract: Systems, methods and/or mobile devices are provided that enable a level of privacy/security in wireless communications to be increased responsive to a content of the wireless communications, biometric data and/or a position from which the wireless communications takes place. A plurality of communications modes is used by the system infrastructure and the plurality of mobile devices communicating therewith to increase privacy and undetectability of transmitted signals. The increased level of privacy and undetectability of signals is provided via pseudo-randomly generated signaling alphabets that are used by the mobile devices and by the system infrastructure to provide the communications. This represents a level of encryption/scrambling that is over and above the conventional encryption and/or scrambling at the bit level. Accordingly, systems, methods and/or devices providing a concatenated level of encryption/scrambling are provided.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: August 19, 2014
    Assignee: EICES Research, Inc.
    Inventor: Peter D. Karabinis
  • Patent number: 8718152
    Abstract: There is provided a two-wire transmitter which is connected to an external circuit by two transmission lines and which outputs a certain current signal to the external circuit using the external circuit as a power source. The two-wire transmitter includes: a sensor configured to convert a physical quantity into a first electrical signal and output the first electrical signal; a signal processing circuit configured to perform certain processing on the first electrical signal and output a second electrical signal; a constant current circuit configured to determine the certain current signal to be output to the external circuit, based on the second electrical signal; a reference voltage output unit configured to output a reference voltage based on the second electrical signal; and a shunt regulator circuit configured to determine a circuit voltage of the two-wire transmitter based on the reference voltage.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: May 6, 2014
    Assignee: Yokogawa Electric Corporation
    Inventors: Youichi Iwano, Ikuhiko Ishikawa, Ryou Hagiwara, Kazuyuki Endo
  • Publication number: 20140118027
    Abstract: An apparatus for processing signals, arranged on an integrated circuit, comprises at least one analog input port that receives an input signal from outside of the integrated circuit, and a detector that detects an operation state of the apparatus based on the input signal. The detector provides at least one digital control/enable signal, which is dependent on the operation state of the apparatus, to another apparatus arranged on the integrated circuit.
    Type: Application
    Filed: October 30, 2013
    Publication date: May 1, 2014
    Applicant: Renesas Mobile Corporation
    Inventors: Ari Juhani VILANDER, Jouni Kristian KAUKOVUORI
  • Publication number: 20140049290
    Abstract: There is disclosed an integrated circuit comprising a management unit for managing the occurrence of predetermined events in the integrated circuit. The management unit comprises: a processing unit adapted to determine the occurrence of a predetermined event in the integrated circuit; a data storage unit adapted to store information regarding the determined event occurrence; an output interface adapted to output a signal based on the stored information regarding the determined event occurrence; and an output generating unit adapted to analyse the stored information and to generate a signal to be output by the output interface based on results of the analysis.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 20, 2014
    Applicant: NXP B.V.
    Inventors: Rinze Ida Mechtildis Peter Meijer, Ghiath Al-kadi
  • Patent number: 8630358
    Abstract: A system-on-chip integrated circuit 2 includes a packet transmitter 28 for generating data packets to be sent via a communication circuit 34 to a packet receiver 30 containing a buffer circuit 32. A transmitter counter 36 stores a transmitter count value counting data packets sent. A receiver counter 38 stores a receiver count value tracking data packets emptied from the buffer circuit 32. A comparison circuitry 40 is used to compare the transmitter count value and the receiver count value to determine whether or not there is storage space available within the buffer circuit 30 to receive transmission of further data packets. The packet transmitter 28 operates in a transmitter clock domain that is asynchronous from a receiver clock domain in which the packet receiver operates. One of the count values is passed across this asynchronous clock boundary in order that the comparison may be performed and flow control exercised.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: January 14, 2014
    Assignee: ARM Limited
    Inventors: Partha Prasun Maji, Steven Richard Mellor
  • Publication number: 20130342239
    Abstract: A shifter with invalid signal filtering mechanism, comprising: a first shifting stage, for receiving and capturing an input signal in a first clock cycle; and a second shifting stage, after the first shifting stage, for receiving the input signal from the first shifting stage, and for receiving a validity signal indicating whether the input signal is valid or invalid, before a second clock cycle next to the first clock cycle occurs; wherein the second shifting stage captures the input signal transmitted from the first shifting stage if the validity signal indicates that the input signal is valid, where the second shifting stage does not capture the input signal transmitted from the first shifting stage if the validity signal indicates that the input signal is invalid.
    Type: Application
    Filed: June 24, 2012
    Publication date: December 26, 2013
    Inventor: Kallol Mazumder
  • Publication number: 20130328594
    Abstract: A divider for providing an output signal having an output frequency by dividing a reference frequency of a reference signal by a divider value is disclosed. The divider includes at least a first divider element configured to provide a first divider output signal having a first divider output signal frequency which is half of the reference frequency and a last divider element configured to provide a last divider output signal having a last divider output signal frequency which half of the preceding divider output signal frequency. Furthermore, the divider comprises an output signal provider for providing the output signal.
    Type: Application
    Filed: June 11, 2012
    Publication date: December 12, 2013
    Applicant: Intel Mobile Communications GmbH
    Inventor: Oliver Hauck
  • Patent number: 8531187
    Abstract: Provided is a correction circuit for generating an output signal emphasizing a predetermined signal component of a supplied input signal, including: a first detection section that detects a waveform of the input signal; an amplifying section that amplifies the waveform detected by the first detection section; a correction signal generating section that generates a correction signal by extracting an alternate current component from the waveform amplified by the amplifying section; and an output signal generating section that superimposes the correction signal on the waveform of the input signal, thereby generating the output signal.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: September 10, 2013
    Assignee: Advantest Corporation
    Inventors: Yuji Kuwana, Naoki Matsumoto
  • Publication number: 20130076397
    Abstract: A circuit configuration for a data processing system for predicting a coordinate for at least one operation to be carried out is provided, the prediction being connected to at least one input signal and being a function of a predefined first time value and at least one predefined first value which represents another physical variable. Upon each change of the at least one input signal, a second time value is calculated in each case from the first value, and to subtract the first time value from the second time value to form a third time value, and/or to calculate a second value from the first time value, and to subtract the first value from the second value to form a third value, in order to determine from the third time value and/or the third value a state in which the at least one operation is to be carried out.
    Type: Application
    Filed: March 16, 2011
    Publication date: March 28, 2013
    Inventors: Eberhard Boehl, Andreas Hempel, Dieter Thoss, Ruben Bartholomae, Stephen Schmitt, Andreas Merker
  • Patent number: 8401093
    Abstract: A method for producing a set of inbound pulse patterns and detection vectors for lengths longer than 4 cycles in an AC waveform. These are used for generating inbound messages in a two-way automatic communication system (TWACS). The method uses Hadamard matrices adapted to generate a set of detection vectors by permuting rows of a matrix and removing certain columns of the matrix to meet system design requirements. The method can be extended to any length and modified to accommodate multiple pulses per half-cycle to support higher data rates.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: March 19, 2013
    Assignee: Aclara Power-Line Systems, Inc.
    Inventor: Quentin Spencer
  • Publication number: 20130049809
    Abstract: A micro electro-mechanical system (MEMS) circuit includes a MEMS differential capacitor, a read-out circuit, a control circuit, and a compensation circuit. The MEMS differential capacitor includes a first capacitor and a second capacitor. The read-out circuit is coupled to the MEMS differential capacitor for reading a difference between the first capacitor and the second capacitor in a zero-G condition, and generating an output signal according to the difference. The control circuit is coupled to the read-out circuit for receiving the output signal and generating a control signal. The compensation circuit is coupled to the control circuit for compensating the MEMS differential capacitor according to the control signal.
    Type: Application
    Filed: November 8, 2011
    Publication date: February 28, 2013
    Inventor: Chia-Tai Wu
  • Publication number: 20130015885
    Abstract: Systems and methods are provided for reading an associated state of a qubit. A first soliton is injected along a first Josephson transmission line coupled to the qubit. A velocity of the first soliton is selected according to a physical length of the qubit and a characteristic frequency of the qubit. A second soliton is injected at the selected velocity along a second Josephson transmission line that is not coupled to the qubit. A delay associated with the first soliton is determined relative to the second soliton.
    Type: Application
    Filed: July 11, 2011
    Publication date: January 17, 2013
    Inventors: OFER NAAMAN, Jae I. Park, Aaron A. Pesetski
  • Patent number: 8340223
    Abstract: A receiver includes: an amplifier that amplifies a received broadband signal up to a predetermined level; a first switch that switches an output signal from the amplifier; a signal generator that generates a signal for controlling a switching operation of the first switch; an integration capacitor that integrates an output signal from the first switch; a comparator that compares an output voltage from the integration capacitor with a predetermined voltage; and a reset circuit that discharges electrical charges accumulated in the integration capacitor based on a comparison result from the comparator.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: December 25, 2012
    Assignee: NEC Corporation
    Inventor: Akio Tanaka
  • Patent number: 8254437
    Abstract: A transmitting apparatus, receiving apparatus and communication system are disclosed, and great improvement in an S/N ratio, preventing an actual throughput from decreasing, and preventing the number of circuits for synchronizing spread spectrum signals from increasing can be expected at the receiving apparatus side. The transmitting apparatus includes a pulse generating circuit, pulse repetition cycle determining circuit, peak power determining circuit, and modulator. The pulse generating circuit generates pulse strings, pulse repetition cycle determining circuit determines, based on a clock signal, a pulse repetition cycle of the pulse string generated by the pulse generating circuit. The peak power determining circuit determines a pulse peak power of the pulse string. The modulator modulates the pulse string with transmission data, and then generates a transmission signal.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: August 28, 2012
    Assignee: Panasonic Corporation
    Inventors: Suguru Fujita, Masahiro Mimura, Kazuaki Takahashi, Yoshinori Kunieda, Noriyuki Ueki
  • Publication number: 20120200317
    Abstract: A control system is disclosed for monitoring and controlling an industrial water system comprising (a) obtaining a priori knowledge about the correlation between water and treatment chemistry and equipment health; (b) pre-defining a set of operating regions of more than one feed-water or system water variable and at least one chemical treatment variable, where, based on (a) above, corrosion, scaling and fouling are inhibited; (c) adjusting the at least one chemical treatment variable according to the more than one feed water or system water variable, such that based on (a), corrosion, scaling and fouling are inhibited.
    Type: Application
    Filed: August 10, 2011
    Publication date: August 9, 2012
    Inventors: John RICHARDSON, Ron Woods
  • Patent number: 8238477
    Abstract: In an embodiment, set forth by way of example and not limitation, a data slicer includes a signal input node, a comparator having a first input of a first polarity, a second input of a second polarity which is the opposite of the first polarity, and an output coupled to a data out node, the first input of the comparator being coupled to the signal input node, and a multi-mode threshold generator including a first threshold generator and second threshold generator, whereby the first threshold generator is selected firstly and the second threshold generator is selected secondly.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: August 7, 2012
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Andrew Zocher, Luiz Antonio Razera, Jr.
  • Publication number: 20120198204
    Abstract: A fast masked summing comparator apparatus includes a comparator unit configured to compare a masked first number to a masked sum of a second number and a third number to determine whether the masked sum is equivalent to the masked first number without performing a summation portion of an addition operation between the second number and the third number. The comparator unit may concurrently mask both the sum and the first number using the same mask value.
    Type: Application
    Filed: August 22, 2011
    Publication date: August 2, 2012
    Inventor: Chetan C. Kamdar
  • Patent number: 8209142
    Abstract: A device for triggering a recording of a measured signal dependent upon at least one triggering event identifiable in a occurrence distribution of parameter pairs from two mutually-dependent parameters of the measured signal includes a discriminator for the identification of triggering events in each case with one frequency (NofTreffer) determined for the respective parameter pair and, in a first embodiment, disposed outside, and in a second embodiment, disposed inside, an upper and lower threshold value (UpperNofTreffer, LowerNofTreffer) associated with the respective parameter pair and for marking each occurring triggering event with the assistance of an activated first trigger marker (TrigMerk1) associated with the respective parameter pair. A memory is used for buffering at least the upper and lower threshold value (UpperNofTreffer, LowerNofTreffer) for every parameter pair.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: June 26, 2012
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Kurt Schmidt
  • Publication number: 20120019285
    Abstract: Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal.
    Type: Application
    Filed: July 21, 2010
    Publication date: January 26, 2012
    Applicant: Intel Corporation
    Inventors: Praveen Mosalikanti, Harishankar Sridharan, Jacob Schneider, Pushkar Gorur, Nasser A. Kurd
  • Patent number: 8073061
    Abstract: There is provided a radio communication device capable of suppressing increase of power consumption of a relay station device. In this device, a channel information extraction unit (31) extracts channel information (channel information in the mobile station device of the signal transmitted from the base station device) from the reception signal from a base station device; a sub carrier selection unit (32) selects a sub carrier of low received quality according to the channel information; a relay data extraction unit (33) extracts data to be relay-transmitted according to the selection result in the sub carrier selection unit (32); and a sub carrier allocation unit (35) allocates data to be relay-transmitted to the sub carrier for relay transmission.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: December 6, 2011
    Assignee: Panasonic Corporation
    Inventors: Ayako Horiuchi, Akihiko Nishio
  • Patent number: 8064722
    Abstract: A method and system of analyzing signal-vector data from first order sensors including providing a training data set, adjusting the training data set using a background adjustment technique, normalizing and transforming the training data set into wavelet coefficients, using an automated analysis of variance feature selection technique and a pattern recognition technique to classify the training data set. The method and system may also include performing these operations on an unknown sample data set collected under unknown conditions and comparing the unknown sample data set to the classification model to provide an identity of the unknown conditions associated with the unknown sample data set. The present invention is also directed to a computer system for analyzing signal-vector data according to this method and a sensing system that includes a sensor and a microprocessor on which is stored a classification model for real-time sensing of unknown sample data sets.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: November 22, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Susan L. Rose-Pehrsson, Mark H. Hammond, Kevin J. Johnson
  • Patent number: 8040813
    Abstract: An apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. The signal-handling element includes an isolating circuit coupled to the first conductor, a second conductor operable to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. The signal-handling circuit is operable to perform a signal-handling function in response to the output of the isolating circuit. By virtue of the isolating circuit, the signal-handling circuit and the first circuit are isolated from the second conductor and the signal-handling circuit. Preferably, the achieved isolation permits a communication signal included in the first signal to be conducted within a communication apparatus with less capacitance, and producing less return loss of that signal.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Karl D. Selander, Michael A. Sorna, Daniel W. Storaska
  • Patent number: 8040958
    Abstract: A method for measuring correlation between frequency response functions. A first frequency response function and a second frequency response function are acquired. The amplitude of the first and second frequency response functions are tabulated at a plurality of corresponding, predetermined frequencies. Amplitude and shape correlations between the first and second frequency response functions are then computed. The computed amplitude and shape correlations provide an indication of the degree of correspondence between the first and second frequency response functions, and can be used to compute a frequency response index that is an objective measure of the overall correspondence between the first and second frequency response functions.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: October 18, 2011
    Assignee: Honda Motor Co., Ltd
    Inventors: Jared S. Cox, Charles Gagliano
  • Patent number: 8023605
    Abstract: A multiphase delay unit causes different delay times to a reference clock to generate a multiphase clock with different phases. A multiphase sampling unit samples the input signal using the multiphase clock, and outputs multiphase sampling data. A phase selecting unit detects a phase relation of the multiphase clock using the multiphase sampling data, and selects output data from the multiphase sampling data based on a result of detecting the phase relation.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: September 20, 2011
    Assignee: Ricoh Company, Ltd.
    Inventors: Nobunari Tsukamoto, Hidetoshi Ema
  • Patent number: 7999576
    Abstract: The present invention discloses a sense amplifier control circuit which controls the sense amplifier. A sense amplifier control circuit comprises a voltage comparing unit outputting delay control signals having a value corresponding to each of divided voltages obtained by dividing a potential of a power supply voltage and a pull-up control signal generating unit outputting an overdrive control signal and a pull-up control signal by an active signal and changing an enable pulse width of the overdrive control signal in response to the delay control signals, whereby it is possible to reduce current consumption caused by unnecessary overdrive operation and prevent a potential drop of the power supply voltage and thus provide operational stability of the semiconductor memory device by providing the overdrive control signal of which the enable pulse width is controlled in response to the potential of the power supply voltage.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: August 16, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Soo Chi
  • Patent number: 7978111
    Abstract: A time-to-digital converter (TDC) can have a resolution that is finer than the propagation delay of an inverter. In one example, a fractional-delay element circuit receives a TDC input signal and generates therefrom a second signal that is a time-shifted facsimile of a first signal. The first signal is supplied to a first delay line timestamp circuit (DLTC) and the second signal is supplied to a second DLTC. The first DLTC generates a first timestamp indicative of a time between an edge of a reference input signal to the TDC and an edge of the first signal. The second DLTC generates a second timestamp indicative of a time between the edge of the reference input signal and an edge of the second signal. The first and second timestamps are combined and together constitute a high-resolution overall TDC timestamp that has a finer resolution than either the first or second timestamps.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: July 12, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Bo Sun, Zixiang Yang
  • Publication number: 20110158031
    Abstract: In a signal calibration scheme, a desired phase relationship is maintained between a set of signals. For example, in some aspects the desired phase of a clock tree generated from a high speed reference clock signal may be maintained by detecting phase differences between a low speed reference clock signal and low speed clock signals associated with different phases of the clock tree. In some aspects, the desired phase of a clock tree may be maintained by detecting framing offsets that occur through the use of the clock tree.
    Type: Application
    Filed: August 27, 2009
    Publication date: June 30, 2011
    Inventors: Frederick A. Ware, Reza Navid, John W. Poulton
  • Publication number: 20110032001
    Abstract: According to one embodiment, a temperature detection circuit is provided which requires only a small number of additional components, thus minimizing an increase in costs and which offers an insulating property and high responsiveness. A temperature detection circuit outputs a first PWM signal corresponding to a temperature of a first temperature sensor from a photointerrupter as a signal insulated from the first temperature sensor. A temperature detection circuit outputs a second PWM signal corresponding to a temperature of a second temperature sensor from a photointerrupter as a signal insulated from the second temperature sensor. A controlling arithmetic apparatus calculates a higher one of the temperatures detected by the first and second temperature sensors based on the PWM signals output from the photointerrupter.
    Type: Application
    Filed: October 18, 2010
    Publication date: February 10, 2011
    Inventors: Ryuta HASEGAWA, Ryuichi Morikawa, Nobumitsu Tada, Masami Hirata
  • Patent number: 7885342
    Abstract: In one embodiment, a method includes receiving, from a decoder connected to a wireless receiver for communication with a remote apparatus, first error data that indicates a current error rate that corresponds to a first inbound data packet received from the remote apparatus. Based in part on the first error data, it is determined whether the remote apparatus should increase a current signal to noise ratio. If so, then a first outbound data packet is sent to an encoder connected to a wireless transmitter. The first outbound data packet includes first link conditioning request data that indicates a current signal to noise ratio for one or more data packets received from the remote apparatus based at least in part on the first error data. The remote apparatus increases signal to noise ratio of transmissions in response to receiving the outbound data packet.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: February 8, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: Alain Brainos, David Buster, Christopher James Lefelhocz
  • Patent number: 7882473
    Abstract: Mechanisms for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is provided that does not have this asynchronous behavior logic but instead correlates to the simplest synchronous model that is usually used for non-asynchronous functional verification tasks. Sequential equivalence checking is performed to verify that the two models are input/output equivalent. In order to address non-uniform arrival times of bus strands, logic is provided for identifying bus strands that have transitioning bits, determining a representative delay for these strands, comparing the representative delays for all of the bus strands to determine the maximum delay for the entire bus, and applying this maximum delay to one of the models.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jason R. Baumgartner, Yee Ja, Hari Mony, Viresh Paruthi, Barinjato Ramanandray
  • Publication number: 20100321037
    Abstract: A configurable semiconductor includes N terminals adapted to be connected to at least one of T external impedances. N is an integer greater than zero and T is an integer greater than one. The T external impedances have impedance values within predetermined tolerances. A measurement circuit measures an impedance value of at least one of the T external impedances. A control circuit compares the measured impedance value to T ranges and selects a value of a device characteristic based on comparison. The value of the device characteristic selected by the control circuit is independent of the predetermined tolerances of the T external impedances.
    Type: Application
    Filed: August 25, 2010
    Publication date: December 23, 2010
    Inventor: Sehat Sutardja
  • Publication number: 20100308867
    Abstract: A semiconductor device includes a first CPU, a second CPU having a configuration that is the same as or comparable to a configuration of the first CPU, and a comparator that compares an output of the first CPU with an output of the second CPU. The second CPU is made so as to have a lower operating margin than the first CPU. By supplying a same signal to the first CPU and the second CPU and then detecting a mismatch between the outputs of the first CPU and the second CPU as a result of comparison, the abnormality is predicted. The semiconductor device includes a reset control circuit that resets the device when the result of comparison by the comparator indicates an error.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 9, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Atsushi TAKAHASHI, Hiroyuki Kll
  • Publication number: 20100201558
    Abstract: This disclosure relates to analog to digital conversion using irregular sampling.
    Type: Application
    Filed: April 16, 2010
    Publication date: August 12, 2010
    Applicant: Infineon Technologies AG
    Inventors: Andreas Wiesbauer, Lajos Gazsi
  • Publication number: 20100182048
    Abstract: A circuit includes a load; a first differential pair coupled to the load and responsive to input data; a second differential pair coupled to the load and responsive to the input data; a third differential pair coupled to the first differential pair and the second differential pair and responsive to a first control signal and a second control signal; a bias circuit configured to pull a node coupled to both the first differential pair and the second differential pair to a predetermined state; and a current source coupled to the third differential pair and the bias circuit.
    Type: Application
    Filed: January 16, 2009
    Publication date: July 22, 2010
    Applicant: Tektronix, Inc.
    Inventors: John F. STOOPS, Daniel G. KNIERIM
  • Patent number: 7741917
    Abstract: According to an embodiment of a time to digital converter, the time difference between a signal of interest and a reference signal is measured by operating a digitally controlled oscillator at a first frequency during a first portion of the reference signal period and changing the operating frequency from the first frequency to a second frequency during the reference signal period as a function of the time difference between the signal of interest and the reference signal. The time to digital converter continuously counts how many signal transitions occur at an output of the digitally controlled oscillator during the reference signal period. The time difference between the signal of interest and the reference signal is estimated based on the number of signal transitions counted during the reference signal period.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: June 22, 2010
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Staffan Ek
  • Patent number: 7720132
    Abstract: A new method for transmitter-receiver design that enhances the desired signal output from the receiver by whitening the total interference and noise input to the receiver and maximizing the output Signal to Interference plus Noise power Ratio (SINR) is presented. As a result of the whitening process, the receiver “sees” a desired signal in white noise, and the receiver structure is then optimized to maximize the receiver output at the desired decision making instant. Furthermore the new design scheme proposed here can be used for transmit signal energy and bandwidth tradeoff. As a result, transmit signal energy can be used to tradeoff for “premium” signal bandwidth without sacrificing the system performance level in terms of the output Signal to Interference plus Noise power Ratio (SINR).
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: May 18, 2010
    Assignee: C&P Technologies, Inc.
    Inventors: Unnikrishna Sreedharan Pillai, Ke Yong Li
  • Publication number: 20100117882
    Abstract: A semiconductor device includes a first switching device including a first electrode coupled with a first node, a second electrode coupled with a second node, and a first control electrode controlling connection between the first and second electrodes; a second switching device including a third electrode coupled with the second node, a fourth electrode coupled with the second node, and a second control electrode controlling the connection between the third electrode and the fourth electrode; and a first control circuit controlling a substrate voltage of the second switching device.
    Type: Application
    Filed: November 3, 2009
    Publication date: May 13, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Sanroku TSUKAMOTO
  • Patent number: 7711057
    Abstract: A new method for transmitter-receiver design that enhances the desired signal output from the receiver while minimizing the total interference and noise output from the receiver at the desired decision making instant is presented. Further the new design scheme proposed here can be used for transmit signal energy and bandwidth tradeoff. As a result, transmit signal energy can be used to tradeoff for the “premium” signal bandwidth without sacrificing the system performance level in terms of the output Signal to Interference plus Noise power Ratio (SINR). The two designs—the one before and the one after the tradeoff—will result in two different transmitter-receiver pairs that have the same performance level. In many applications such as in telecommunications, since the available bandwidth is at premium, such a tradeoff will result in releasing otherwise unavailable bandwidth at the expense of additional signal energy.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: May 4, 2010
    Assignee: C & P Technologies, Inc.
    Inventor: Unnikrishna Sreedharan Pillai
  • Publication number: 20100079170
    Abstract: An apparatus and method for the analysis of a periodic signal. One embodiment provides signal values. Signs are assigned to the signal values. The signed signal values are summed to a first sum. At least one signal property is determined on the basis of the first sum.
    Type: Application
    Filed: September 29, 2008
    Publication date: April 1, 2010
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Heinz Mattes, Jaafar Mejri, Stephane Kirmser, Frank Demmerle
  • Publication number: 20100039311
    Abstract: A system and method for generating alert signals in a detection system is described. The system compares data extracted from signals received via receive antenna beams with stored scenarios and determines whether to generate an alert signal based upon the results of the compare operation. The comparison of data extracted from received signals with stored scenarios can be accomplished by using one or more latches to process the extracted data from the received signals. In one embodiment, raw detections are pre-processed to generate so-called field of view (FOV) products. The FOV products are then provided to a tracker. In another embodiment, rather than pre-process the raw detections, the raw detections are instead provided directly to a tracker which processes the raw detections to provide products including, but not limited to, relative velocity and other parameters.
    Type: Application
    Filed: October 31, 2007
    Publication date: February 18, 2010
    Inventors: Walter G. Woodington, Wilson J. Wimmer