With Feedforward Patents (Class 327/154)
  • Patent number: 10326432
    Abstract: A method and system of providing harmonic frequency multiplication are provided. An input signal having a frequency f, is received by a programmable timing circuit. A signal that is in phase with the input signal, is provided at the first output of the programmable timing circuit. A time delayed version of the input signal, having the frequency f, is provided at the second output of the programmable timing circuit. A signal having the frequency f, is provided at the output of a first buffer. A duty cycled controlled signal having the frequency f, is provided at the output of the second buffer. A frequency nf, where n is a positive integer, is provided at the output of the multiplier. A higher-order frequency multiplied signal based on the frequencies f and nf, is provided at the output of a mixer.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wooram Lee, Bodhisatwa Sadhu, Alberto Valdes Garcia
  • Patent number: 10075153
    Abstract: A low-power synchronizer circuit, a data processing circuit that incorporates the synchronizer circuit, and a synchronization method are provided. The synchronizer circuit includes a delay circuit for receiving and delaying an asynchronous input signal, a first flip-flop having an input terminal connected to an output terminal of the delay circuit, a clock terminal for receiving the asynchronous input signal, and a reset terminal for receiving the asynchronous input signal, a synchronizer connected to an output terminal of the first flip-flop, and a clock-gating circuit for receiving a clock signal and determining whether to supply the clock signal to the synchronizer in response to one of a first output value of the delay circuit and a second output value of the first flip-flop and a third output value of the synchronizer.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: September 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taek Kyun Shin, Jin Pyo Park, Soong Hyun Shin, Jung Hun Heo
  • Patent number: 10003617
    Abstract: An application synchronization method for use in a terminal is provided. The application synchronization method includes acquiring an alarm registration request of a first repetitive synchronization operation, acquiring a next execution time of a second repetitive synchronization operation associated with a same application as an application of the first repetitive synchronization operation, adjusting, if a difference between an alarm time of the alarm registration request of the first repetitive synchronization operation and the next execution time of the second repetitive synchronization operation is less than or equal to a threshold value, the alarm time of the alarm registration request of the first repetitive synchronization operation according to the next execution time of the second repetitive synchronization operation, and registering the adjusted alarm time.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: June 19, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngki Hong, Killyeon Kim, Yongseok Park
  • Patent number: 9584141
    Abstract: A circuit and a method are disclosed herein. The circuit includes a digitally controlled oscillator and a detector. The digitally controlled oscillator is configured to generate an oscillator signal according to an oscillator tuning word. The detector is configured to output one of a first control word and a second control word that is derived from the first control word as the oscillator tuning word.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: February 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Wei Kuo, Chewn-Pu Jou, Huan-Neng Chen, Kuang-Kai Yen, Lan-Chou Cho, Robert Bogdan Staszewski, Tsung-Hsiung Lee
  • Patent number: 9501088
    Abstract: The present invention discloses a clock generator comprising: an oscillator operable to generate a reference clock; a multi-phase clock generating circuit operable to generate a plurality of output clocks of the same frequency but different phases according to the reference clock and stop or start outputting the output clocks according to a power control signal; a sequential clock gating circuit operable to sequentially stop or start outputting a plurality of gated clocks according to a gate control signal and maintain an output cycle number relation between the gated clocks even though the multi-phase clock generating circuit stops and then starts outputting the output clocks; and a clock operation control circuit operable to provide the power control signal and the gate control signal.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: November 22, 2016
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chih-Jung Chiang, Shun-Te Tseng, Kai-Yin Liu, Jian-Ru Lin
  • Publication number: 20150145566
    Abstract: A hybrid analog/digital control approach for a digitally controlled oscillator augments a digital control path with an analog control path that acts to center the digital control path control signal within its range. The digital control path controls a first group of varactors within an oscillator tank circuit using a digital filter and a delta sigma modulator, which generates a dithered control signal for at least one of the first group of varactors. The analog control path controls a second group of varactors in the tank circuit but actively tunes only one varactor at a time. The analog control path performs relatively low bandwidth centering of the digital control signal resulting in negligible impact on PLL bandwidth, stability, and noise performance. Instead, the digital control path dominates in setting the PLL dynamic and noise behavior, and has reduced range requirements due to the centering action.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 28, 2015
    Inventor: Michael H. Perrott
  • Patent number: 9025712
    Abstract: A clock frequency adjusting system is disclosed. The clock frequency adjusting system includes a sensing clock generating unit, a frequency-dividing unit and a controller. The frequency-dividing unit makes frequency of the sensing clock signal be divided by a frequency-dividing modulus and then outputs a clock calibration signal. The controller includes a period counter and a frequency adjusting unit. The period counter samples the clock calibration signal through the external clock signal so as to acquire a second count value. The frequency adjusting unit calculates a frequency difference data between the clock calibration signal and the predetermined clock signal according to the first count value and the second count value, and determines a number of adjustment according to the frequency difference data and a step adjusting frequency so as to output a clock adjusting signal to the sensing clock unit to adjust frequency of the sensing clock signal.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: May 5, 2015
    Assignee: Pixart Imaging Inc.
    Inventor: Kevin Len-Li Lim
  • Publication number: 20150097602
    Abstract: A system includes a first phase-locked loop (PLL) circuit, a slew rate limiter and a second PLL. The first PLL is configured to receive an input signal, generate a first output identifying a frequency associated with the input signal, and generate a second output identifying phase information associated with the input signal. The slew rate limiter is configured to receive the first output from the first PLL, determine whether the frequency of the first output is changing at greater than a predetermined rate, and generate a first signal indicating whether the frequency is changing at greater than the predetermined rate. The second PLL is configured to receive the first signal from the slew rate limiter, receive the second output from the first PLL, and generate an output signal identifying an angle or phase information based on the first signal and the second output.
    Type: Application
    Filed: September 15, 2014
    Publication date: April 9, 2015
    Inventor: Justin Walraven
  • Publication number: 20140312942
    Abstract: In some examples, a circuit is described. The circuit may include a voltage-controlled oscillator that may be configured to generate an output signal. The circuit may also include a control signal generation unit that may be configured to generate a control signal based on the output signal. The control signal generation unit may also be configured to provide the control signal to the voltage-controlled oscillator. The voltage-controlled oscillator and the control signal generation unit may be part of a phase-locked loop (PLL) included in the circuit. The circuit may also include a feed-forward network. The feed-forward network may be configured to provide a portion of the control signal to the voltage-controlled oscillator. The voltage-controlled oscillator may generate the output signal based on the control signal from the control signal generation unit and the portion of the control signal from the feed-forward network.
    Type: Application
    Filed: April 22, 2013
    Publication date: October 23, 2014
    Applicant: WASHINGTON STATE UNIVERSITY
    Inventors: Deukhyoun Heo, Pawan Agarwal
  • Publication number: 20140084974
    Abstract: A phase locked loop having a normal mode and a burn-in mode. The logic portion is coupled to a logic power supply terminal and includes a clock receiver coupled to a phase frequency detector. The analog portion has a charge pump coupled to the phase frequency detector and to an analog power supply terminal. The analog portion also has a voltage controlled oscillator coupled to the charge pump at an analog node and to the analog power supply terminal. The phase locked loop has a node control circuit that is coupled to the analog node during the burn-in mode that controls a voltage at the analog node sufficiently below a voltage at the analog power supply terminal to avoid over-stressing the charge pump and the voltage controlled oscillator during the burn-in mode.
    Type: Application
    Filed: September 26, 2012
    Publication date: March 27, 2014
    Inventors: XINGHAI TANG, Gayathri A. Bhagavatheeswaran, Hector Sanchez
  • Patent number: 8638172
    Abstract: A local oscillator of an embodiment includes a digitally-controlled oscillator, a phase data generator, a subtractor, a loop filter, a multiplier, and a coefficient calculator. The digitally-controlled oscillator variably controls an oscillation frequency of an oscillation signal by using a first oscillator control value. The oscillation frequency is equal to a product of the first oscillator control value multiplied by an amount of change in the oscillation frequency per unit first oscillator control value. Set frequency data is calculated by dividing a set frequency by a reference frequency of a reference signal. The multiplier outputs the first oscillator control value obtained by multiplying a normalized control value from the loop filter by a first coefficient. The coefficient calculator divides, by the set frequency data, the first oscillator control value which makes the oscillation frequency roughly equal to the set frequency, and sets the quotient as a new first coefficient in the multiplier.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: January 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Suzuki, Hiroyuki Kobayashi, Jun Deguchi
  • Patent number: 8471619
    Abstract: A circuit comprises a frequency divider coupled to receive an oscillating signal generated by an oscillator and a division ratio and configured to divide the oscillating signal by the division ratio into a clock signal; a temperature compensation circuit configured to measure a temperature of the oscillator and generate a division ratio to be provided to the frequency divider and a first value on the basis of the measured temperature; and a control system configured to control connection between a calibration element and the oscillator based on the first value and the oscillating signal of the oscillator.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: June 25, 2013
    Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd.
    Inventor: Henry Ge
  • Patent number: 8427219
    Abstract: The present invention is directed to a clock generator and a method of generating a clock signal. A digital control oscillator (DCO) generates a clock signal. A first frequency calibration unit extracts a periodic signal and determines a frequency error quantity between the extracted periodic signal and a derived clock signal. A second frequency calibration unit generates a coarse tuning signal when an absolute value of the frequency error quantity is greater than a first predetermined threshold, and generates a fine tuning signal when the absolute value of the frequency error quantity is less than a second predetermined threshold.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: April 23, 2013
    Assignee: Skymedi Corporation
    Inventors: Ching-Cheng Wu, Chih-Yu Chuang
  • Patent number: 8392744
    Abstract: Apparatus, systems, and methods are disclosed that operate to adjust power received by a clock distribution network at least partially based on operating conditions of an integrated circuit. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: March 5, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Feng Lin
  • Patent number: 8258877
    Abstract: Systems, methods, and apparatus are described that provide for low phase-noise, spectrally-pure, and low-jitter signals from electrical oscillators. An aspect of the present disclosure includes utilization of an open-loop feed-forward phase-noise cancellation scheme to cancel phase noise, or jitter, of an electrical oscillator. Phase noise can be measured and then subtracted, with the phase noise measurement and subtraction being performed at a speed faster than phase noise variations of the oscillator. Another aspect of the present disclosure includes use of a feedback scheme for phase noise reduction. A feedback scheme can be used alone or in conjunction with a feed-forward scheme. Related phase-noise cancellation and/or reduction methods are described. Notch filter and RF amplifier circuits are also described.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: September 4, 2012
    Assignee: University of Southern California
    Inventors: Ankush Goel, Alireza Imani, Hossein Hashemi
  • Patent number: 8237482
    Abstract: A circuit comprises a frequency divider coupled to receive an oscillating signal generated by an oscillator and a division ratio and configured to divide the oscillating signal by the division ratio into a clock signal; a temperature compensation circuit configured to measure a temperature of the oscillator and generate a division ratio to be provided to the frequency divider and a first value on the basis of the measured temperature; and a control system configured to control connection between a calibration element and the oscillator based on the first value and the oscillating signal of the oscillator.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: August 7, 2012
    Assignee: STMicroelectronics (Shenzen) R&D Co. Ltd.
    Inventor: Henry Ge
  • Patent number: 8222921
    Abstract: Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 17, 2012
    Assignee: Altera Corporation
    Inventors: David Lewis, David Cashman
  • Patent number: 8166438
    Abstract: A system includes an input device, an output device, a printed circuit board, and a semiconductor device. The semiconductor device includes a semiconductor die. The semiconductor die includes a clock distribution network that distributes a primary clock signal. The clock distribution network includes a low RC local clock distribution structure. The low RC local clock distribution structure includes a conductor, a first clock signal incident on the conductor, a local gain buffer pair that receives the first clock signal and outputs a second clock signal corresponding to the first clock signal, and a shorting bar that shorts the second clock signal to a plurality of conductors.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: April 24, 2012
    Assignee: Oracle America, Inc.
    Inventor: Robert P. Masleid
  • Patent number: 8154327
    Abstract: A phase adjusting apparatus includes a comparison code generating section, a calculating section, and a delay section. The comparison code generating section individually generates a first comparison code having a phase of a head code advanced and a second comparison code having the phase of the head code delayed, the head code being included in serial transfer data. The calculating section acquires a direction of adjustment of a phase of the serial transfer data using a comparison result of the head code and the first comparison code and a comparison result of the head code and the second comparison code. The delay section adjusts a delay amount of the serial transfer data based on the direction of adjustment of the phase.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: April 10, 2012
    Assignee: Nikon Corporation
    Inventor: Daiki Ito
  • Publication number: 20120049908
    Abstract: To calculate a control signal for the duty cycle of a switched mode power supply (SMPS), a voltage feed forward compensator is integrated into a feedback unit. A control unit has an adder with a first input to receive a signal dependent upon an output voltage.
    Type: Application
    Filed: February 26, 2010
    Publication date: March 1, 2012
    Inventors: Magnus Karlsson, Fredrik Wahledow
  • Patent number: 8045610
    Abstract: A decision feedback equalizer has a feedback filter and K feed forward filter branches. Each of the K feed forward filter branches receives an input signal from a corresponding one of a plurality of channels associated with a corresponding one of a plurality of antennas, where K>1. Each of the K feed forward filter branches provides an output. An instantaneous SNR level ?k is determined for each of the K feed forward filter branches. The instantaneous SNR level ?k for each of the K feed forward filter branches is compared to an upper threshold TH and to a lower threshold TL. The outputs from the K feed forward filter branches are selectively added dependent upon the comparing of the instantaneous SNR level ?k for each of the K feed forward filter branches to the upper threshold TH and to the lower threshold TL.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: October 25, 2011
    Assignee: Zenith Electronics LLC
    Inventor: Huahui Wang
  • Patent number: 8032778
    Abstract: Apparatus, systems, and methods are disclosed that operate to adjust power received by a clock distribution network at least partially based on operating conditions of an integrated circuit. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: October 4, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Feng Lin
  • Patent number: 8014881
    Abstract: In a lithographic apparatus, a feedforward transfer function of a control system is determined by: a) iteratively learning a feedforward output signal of the control system by iterative learning control for a given setpoint signal; b) determining a relation between the learned feedforward output signal and the setpoint signal; and c) applying the relation as the feedforward transfer function of the control system. A learned feedforward, which has been learned for one or more specific setpoint signals only, can be adapted to provide a setpoint signal dependent feedforward output signal. The learned feedforward can be made more robust against setpoint variations.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: September 6, 2011
    Assignee: ASML Netherlands B.V.
    Inventors: Mark Constant Johannes Baggen, Petrus Marinus Christianus Maria Van Den Biggelaar, Yin Tim Tso, Marcel François Heertjes, Ramidin Izair Kamidi, Dennis Andreas Petrus Hubertina Houben, Constant Paul Marie Jozef Baggen, Marinus Jacobus Gerardus Van De Molengraft
  • Patent number: 7987382
    Abstract: One inventive aspect relates to a digital sub-circuit suitable for embedding in an at least partially digital circuit for minimizing the influence of another digital sub-circuit on the at least partially digital circuit, the other digital sub-circuit being part of the at least partially digital circuit. The influence of the other digital sub-circuit may, for example, be the introduction of ground bounce by switching of the other digital sub-circuit. Another inventive aspect relates to an at least partially digital circuit comprising such a digital sub-circuit for minimizing the influence of another digital sub-circuit to the at least partially digital circuit and to a method for reducing the influence of another digital sub-circuit to an at least partially digital circuit.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: July 26, 2011
    Assignee: IMEC
    Inventor: Mustafa Badaroglu
  • Patent number: 7958469
    Abstract: A design structure for a hybrid phase locked loop (PLL) circuit that obtains stabilized dynamic response and independent adjustment of damping factor and loop bandwidth is provided. The hybrid PLL circuit of the illustrative embodiments includes the resistance/capacitance (RC) filter elements of a conventional RC PLL and the feed-forward path from the output of the phase frequency detector to the voltage controlled oscillator (VCO). The hybrid PLL essentially enhances the performance of the conventional feed-forward PLL by providing the RC filter whose components can be weighted to provide a dynamic response that is significantly less sensitive to parameter variation and which allows loop bandwidth optimization without sacrificing damping.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: June 7, 2011
    Assignee: International Business Machines Corporation
    Inventors: David W. Boerstler, Eskinder Hailu, Jieming Qi
  • Patent number: 7944264
    Abstract: A variable delay circuit includes: a first delay section that changes a first drive capability or a first capacity load, receives the reference signals, and generates a first delayed signal by giving a first delay to the reference signal; a second delay section that changes a second drive capability or a second capacity load of the second delay section, receives the reference signal, and generates a second delayed signal by giving a second delay to the reference signal; a first capacity load setting section that sets at least one of the first capacity load and the second capacity load; a first phase comparing section that compares a first phase of the first delayed signal with a second phase of the second delayed signal; and a drive capability setting section that controls the first drive capability and the second drive capability.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: May 17, 2011
    Assignee: Fujitsu Limited
    Inventors: Ryuichi Nishiyama, Naoya Shibayama
  • Patent number: 7868655
    Abstract: Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: January 11, 2011
    Assignee: Altera Corporation
    Inventors: David Lewis, David Cashman
  • Publication number: 20100194454
    Abstract: A phase adjusting apparatus includes a comparison code generating section, a calculating section, and a delay section. The comparison code generating section individually generates a first comparison code having a phase of a head code advanced and a second comparison code having the phase of the head code delayed, the head code being included in serial transfer data. The calculating section acquires a direction of adjustment of a phase of the serial transfer data using a comparison result of the head code and the first comparison code and a comparison result of the head code and the second comparison code. The delay section adjusts a delay amount of the serial transfer data based on the direction of adjustment of the phase.
    Type: Application
    Filed: December 30, 2009
    Publication date: August 5, 2010
    Applicant: NIKON CORPORATION
    Inventor: Daiki Ito
  • Patent number: 7714631
    Abstract: There are provided, in a clock generator for generating a plurality of output clock signals, an apparatus and method for synchronizing the clock generator to an input reference clock in the presence of a jittery input clock provided to the clock generator from a PLL. The clock generator and the PLL each have a divider with the same ratio. The apparatus includes a synchronizer (205) and a state machine (210). The synchronizer receives the input reference clock and the jittery input clock, and generates there from a synchronized input clock signal with respect to the jittery input clock. The state machine receives the synchronized input clock signal and the jittery input clock, synchronizes with the synchronized input clock signal using the jittery input clock, and abstains from a re-synchronizing operation when the jittery input clock has a jitter of up to a pre-defined maximum number of clock widths.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: May 11, 2010
    Assignee: Thomson Licensing
    Inventor: Gabriel Alfred Edde
  • Patent number: 7716001
    Abstract: A tunable delay line is calibrated to maintain the delay of the delay line at a desired value or within a desired range of values. In some aspects a signal is passed through a delay line multiple times so that the cumulative delay of the signal through the delay line (e.g., as indicated by a count) may be calculated over a period of time. The count is compared with an expected count and, based on this comparison, the delay of the delay line is adjusted as necessary. In some aspects the signal may comprise a digital signal. In some aspects a delay through a delay line may be calculated based on analysis of amplitude changes in a signal caused by a phase shift imparted on the signal by the delay line. In some aspects a delay line is incorporated into a transmitted reference system to generate and/or process transmitted reference signals.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: May 11, 2010
    Assignee: QUALCOMM Incorporated
    Inventors: Chong U. Lee, David Jonathan Julian, Amal Ekbal
  • Publication number: 20090295438
    Abstract: An apparatus and method for timing calibration of write and read-back data exchanges between respective dies of an external memory/external device has a master arbiter or, alternatively, a test mux between a system bus master interface and an external memory controller for driving the external memory/external device, a calibration circuit under control of the master arbiter via a test bus master interface to provide stepped-through time delays for test data exchanges between the dies, and the calibration circuit obtains pass/fail data indicating pass or fail of the varied time delays for the test data exchanges. A processor system at the system bus master interface selects calibration values corresponding to pass data, and applies the calibration values to the respective dies for timing of write and read-back data exchanges between the dies.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 3, 2009
    Inventors: Ravi Kishore Jammula, Andrew Wang, Mark Thierbach
  • Patent number: 7605624
    Abstract: A delay locked loop (DLL) circuit is disclosed. The DLL circuit includes a first delay locked loop (DLL) configured to receive a plurality of first clock signals, delay each of the first clock signals by a predetermined period of time in response to a first control signal, and generate a plurality of first internal clock signals and a second delay locked loop (DLL) configured to receive the first internal clock signals, delay the first internal clock signals by a predetermined period of time in response to a second control signal, and generate a plurality of second internal clock signals.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: October 20, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kwang Jin Na
  • Patent number: 7583103
    Abstract: Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: September 1, 2009
    Assignee: Altera Corporation
    Inventors: David Lewis, David Cashman
  • Patent number: 7561652
    Abstract: For EMI reduction the current modulation profile is preferably used for frequencies over 1 GHz while the frequency deviation is increased at least to ±2.5 MHz and the modulation frequency is increased to at least 150 kHz, preferably about 260 kHz. In an alternative embodiment, the modification frequency is 1 MHz or greater so that a segmented spectrum is achieved. For clocks having basic frequency below 1 GHz, but having strong harmonics higher than 1 GHz, modulation of the foregoing is combined with the slower modulation currently used. EMI reduction is realized both at the lower and the higher harmonics.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: July 14, 2009
    Inventors: Paul Kevin Hall, Keith Bryan Hardin, Robert Allan Menke, Robert Aaron Oglesbee
  • Patent number: 7528638
    Abstract: Clock signal distribution systems with reduced parasitic loading effects are provided. A reference clock is frequency-divided to produce a lower frequency clock signal. A delay-locked loop (DLL) circuit locks to the lower frequency clock signal, and outputs a corresponding lower frequency clock signal for distribution over a long trace. Power consumption caused by parasitic capacitance of the trace is thereby reduced. Parasitic effects associated with clock jitter are also reduced. A frequency multiplying phase-locked loop (PLL) circuit locks to the lower frequency clock signal, and outputs at least one clock signal having a higher frequency than the lower frequency signal.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: May 5, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Seong-hoon Lee, Feng Lin
  • Publication number: 20090007047
    Abstract: A design structure for a hybrid phase locked loop (PLL) circuit that obtains stabilized dynamic response and independent adjustment of damping factor and loop bandwidth is provided. The hybrid PLL circuit of the illustrative embodiments includes the resistance/capacitance (RC) filter elements of a conventional RC PLL and the feed-forward path from the output of the phase frequency detector to the voltage controlled oscillator (VCO). The hybrid PLL essentially enhances the performance of the conventional feed-forward PLL by providing the RC filter whose components can be weighted to provide a dynamic response that is significantly less sensitive to parameter variation and which allows loop bandwidth optimization without sacrificing damping.
    Type: Application
    Filed: May 29, 2008
    Publication date: January 1, 2009
    Applicant: International Business Machines Corporation
    Inventors: David W. Boerstler, Eskinder Hailu, Jieming Qi
  • Patent number: 7319728
    Abstract: A delay locked loop includes a delay line for delaying an input signal generated from an external signal. A delay controller controls the delay line to keep the external and internal signals synchronized. The delay locked loop also includes cycle control circuitry for controlling the cycle time of the signal entering the delay and the cycle time of the signal exiting the delay line.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: January 15, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Debra M. Bell, Paul A. Silvestri
  • Patent number: 7279944
    Abstract: A clock signal generator and method thereof are provided for a system to generate an output signal. The apparatus comprises: a delay circuit for generating a delayed clock with a first time, a delay module for generating delayed signal(s), and a decision circuit for comparing the delayed signal(s) with the delayed clock to obtain the relative relation between the delay time and the first time and controlling a delay time of an input signal according to the relative relation to generate the output signal.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: October 9, 2007
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chao-Hsin Lu
  • Patent number: 7162000
    Abstract: A delay locked loop circuit (200) in which multiple outputs are produced. A single delay line (24) is shared among multiple tap selection circuits (256A, 265B, 265C). Fixed phase shifts (412) can be introduced between multiple outputs. A modulating signal can be used in the tap selection processing to produce digital amplitude, frequency and/or phase modulation.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: January 9, 2007
    Assignee: Motorola, Inc.
    Inventors: Robert E. Stengel, Joseph P. Heck, David E. Bockelman
  • Patent number: 7069359
    Abstract: An apparatus includes a first circuit and a second circuit. The first circuit receives indications of first data that is associated with a first data set and second data that is associated with a second data set. The second circuit is coupled to the first circuit to cause the first circuit to in a first mode, communicate indications of the first data to an output terminal in synchronization with a first phase of a clock signal and communicate indications of the second data to the output terminal in synchronization with a second phase of the clock signal. In a second mode, the second circuit causes the first circuit to communicate the indications of the first data to the output terminal in synchronization with the first phase and prevent communication of the second data during the second phase.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: June 27, 2006
    Assignee: Intel Corporation
    Inventor: Steve Nishimoto
  • Patent number: 6989696
    Abstract: A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: January 24, 2006
    Assignee: International Business Machines Corporation
    Inventors: Rolf Hilgendorf, Jens Kuenzer, Cédric Lichtenau, Thomas Pflueger, Mathew I. Ringler, Gerard M. Salem, Peter A. Sandon, Dana J. Thygesen, Ulrich Weiss
  • Patent number: 6930522
    Abstract: A first circuit is to generate a data signal containing data. A second circuit is to utilize said data, where the first and second circuits are commonly clocked by a latch signal, further a circuit has a first level sensitive latch to latch the data signal from the first circuit upon receiving by way of a delay circuit the latch signal, and a second level sensitive latch to latch an output signal of the first level sensitive latch to the second circuit upon receiving the latch signal. Other embodiments are also described and claimed.
    Type: Grant
    Filed: January 6, 2004
    Date of Patent: August 16, 2005
    Assignee: Intel Corporation
    Inventor: Stephen S. Chang
  • Patent number: 6891412
    Abstract: An RC equivalent filter is provided in which the resistor is replaced by a voltage source (40) and a capacative divider. With suitable control the voltage occurring across a capacitor (44) in the divider can reproduce that which would occur across at the output of the original RC filter, but with much lower noise.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: May 10, 2005
    Assignee: Analog Devices, Inc.
    Inventors: Christopher Geraint Jones, Christophe Claude Beghein
  • Patent number: 6861882
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: March 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Patent number: 6839092
    Abstract: In accordance with an embodiment of the present invention a microprocessor in the horizontal phased lock loop reads the horizontal timing with respect to the sync input and provides an increment inch to the horizontal discrete time oscillator to make corrections in its timing to maintain lock to the sync input. The horizontal discrete time oscillator output is used to produce a pixel clock which drives the color discrete time oscillator in a color phased locked loop. A microprocessor reads a phase error between the color burst input and the color local oscillator frequency and writes an increment incsc to the color discrete time oscillator to maintain lock to the color burst. The horizontal phase locked loop adjusts inch that varies about nominal increment (nom_inch) by ?h. The feed forward error correction for the adjustment to the color discrete time oscillator is the nomimal increment (nom_incsc) and a feed forwarded scaled version of ?h.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: January 4, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Karl Renner
  • Patent number: 6839301
    Abstract: Delay-locked loops, signal locking methods and devices and system incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively couples to an external clock signal and to an internal test signal. The phase detector adjusts a delay line based upon the phase differences of a feedback signal and the external clock signal. The timer circuit switches the test signal into the forward delay path and measures the time of traversal of the test signal around the forward delay path and the feedback delay path and generates a time constant for configuring the phase detector's update period. The phase detector is thereafter able to stabilize at an improved rate.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: January 4, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Feng Lin, J. Brian Johnson
  • Patent number: 6792060
    Abstract: The invention relates to a processing device for digital data which is capable of processing data which have been sampled with a sampling clock which may have any value whatsoever with respect to the basic clock of the device. To achieve this, the device is provided with means for generating from its basic clock an operational clock which is a function of the sampling clock of the data to be processed. This operational clock has a constant integer number of active periods during one cycle of the sampling clock. Application: Digital communication systems, especially demodulation.
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: September 14, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Eric Dujardin, Olivier Gay-Bellile
  • Patent number: 6781426
    Abstract: A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: August 24, 2004
    Assignee: The Regents of the University of California
    Inventor: Vitali V. Souchkov
  • Patent number: 6782353
    Abstract: The present invention provides a measuring device which extracts, from an inputted data signal, a clock signal in which there is little internal occurrence of absence or phase fluctuations, and correctly carries out measurement of an error ratio or jitter or wander accompanying transmission of the data signal by using the clock signal. A band-pass filter extracts, from the inputted data signal, a signal component having a same frequency as that of a clock signal to be regenerated. A binarizing circuit binarizes the extracted signal component at a predetermined threshold value, and outputs it as a regenerated clock signal. At this time, the binarizing circuit is configured such that, when there is a same code continuing period in the data signal, the binarizing circuit binarizes the signal outputted during the period by relaxation vibration at an interior of the band-pass filter, so as to compensate for absence of the clock signal during the period.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: August 24, 2004
    Assignee: Anritsu Corporation
    Inventor: Seiya Suzuki
  • Patent number: 6762630
    Abstract: An integrated circuit has a synchronous circuit and an asynchronous circuit. A clock-controlled input register circuit and an output register circuit for storing data are each connected to the synchronous circuit and the asynchronous circuit. Data are transferred from the synchronous circuit into the input register circuit, from where they are transferred into the asynchronous circuit and processed in the asynchronous circuit. Processed data are transferred into the output register circuit. A sequence controller generates a respective control clock signal for the register circuits in a manner dependent on the data processing duration of the asynchronous circuit. This enables a high data throughput between the synchronous circuit and the asynchronous circuit independently of a clock frequency of the synchronous circuit.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: July 13, 2004
    Assignee: Infineon Technologies AG
    Inventors: Heiko Fibranz, Eckehard Plaettner