With Delay Means Patents (Class 327/161)
  • Patent number: 10387606
    Abstract: A computer implemented method for validating a clock tree includes estimating a first number of a multitude of first buffers disposed in the clock tree path, and selecting a first scaling coefficient in accordance with the first number. The computer implemented method further includes scaling a first delay associated with the multitude of first buffers in accordance with the selected first scaling coefficient, and generating a second multitude of second buffers disposed in the clock tree path defined by a second number greater than the first number.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: August 20, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Chunyang Feng, Jianquan Zheng
  • Patent number: 10347307
    Abstract: A data interface circuit includes a first latch corresponding to a first data signal, and suitable for outputting first data based on toggling of a data strobe signal; a second latch corresponding to a second data signal, and suitable for outputting second data based on toggling of the data strobe signal; and a skew control circuit suitable for delaying the first data signal by a predetermined time, applying the delayed first data signal to the first latch, controlling the delayed first data signal based on a result of comparing the first data signal and the second data signal, and applying the controlled delayed first data signal to the second latch.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 9, 2019
    Assignee: SK hynix Inc.
    Inventor: Jae-Heung Kim
  • Patent number: 10331193
    Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: June 25, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
  • Patent number: 10284952
    Abstract: An audio processing apparatus and a control method thereof are provided. The method includes receiving an audio signal including audio data corresponding to each of a plurality of channels, generating a strobe signal for the audio data corresponding to each of the plurality of channels, converting a clock for the strobe signal corresponding to each of the plurality of channels to a master clock having preset multiple speeds, and outputting the audio signal based on the master clock. The simplification of the system configuration is accomplished by synchronizing an input and an output of the audio signal using hardware.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: May 7, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-hyung Lee, Dae-hyeon Lee, Chang-yong Heo
  • Patent number: 10218342
    Abstract: Apparatuses and methods for correcting a duty cycle of a clock signal are described. An example apparatus includes: a duty cycle corrector (DCC) that receives an input clock signal and a control signal and produces an output clock signal responsive, at least in part, to the input clock signal and the control signal; a circuit that divides a frequency of the input clock signal by a positive even integer and generates an intermediate clock signal; and a phase detector that generates the control signal responsive, at least in part, to a difference in phase between the output clock signal and the intermediate clock signal.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: February 26, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Katsuhiro Kitagawa
  • Patent number: 10063365
    Abstract: Methods, systems, and apparatus for inserting a re-timer signal between a transmitter and a receiver, including receiving, from the transmitter, an input data signal having encoded words, where each encoded word of the encoded words has a word length of a predetermined number of bits; generating, by a re-timer and based on the input data signal, a regenerated clock signal and an output data signal; determining, based on the regenerated clock signal, a timing difference between the input data signal and the output data signal of the re-timer; and applying, by the re-timer and based on the timing difference between the input data signal and the output data signal, a delay to the input data signal to generate a delayed output data signal, such that a timing difference between the input data signal and the delayed output data signal corresponds to N word lengths.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: August 28, 2018
    Assignee: Keyssa Systems, Inc.
    Inventors: Jerome Jean Ribo, Bruno Tourette
  • Patent number: 10038433
    Abstract: A device for correcting a multi-phase clock signal includes a first duty ratio adjusting circuit (DRAC) to adjust a duty ratio of a first clock signal; a variable delay line (VDL) delaying a second clock signal; a second DRAC adjusting a duty ratio of the VDL output; first and second differential clock generating circuits (DFCGs) generating differential signals from first and second DRAC outputs, respectively; an edge combining circuit combining edges of outputs from the DFCGs; a duty ratio detecting circuit (DRDC) detecting a duty ratio of a first DRAC output or a first DFCG output in a first mode and of an edge combining circuit output in a second mode; a first control circuit controlling the first and second DRACs using a DRDC output in the first mode; and a second control circuit controlling the VDL using the DRDC output in the second mode.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: July 31, 2018
    Assignees: SK HYNIX INC., KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Jeong Cho, Soowon Kim, Jinhoon Hyun, Chanhui Jeong, Daehan Kwon
  • Patent number: 10038371
    Abstract: The invention concerns a device (3) for synchronizing at least two DC/DC converters. It is characterized in that it comprises receiving means (21A, 21B, 23A, 23B) for receiving a switching signal generated by each of the converters; means (25) for detecting a transition type of the received switching signals; means (27) for generating a synchronization signal when a transition is detected; and means (27, S1, S2) for supplying the synchronization signal to one of the converters, said means (27, S1, S2) being configured to supply the synchronization signal to a different converter and in an order of succession each time a transition is detected.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: July 31, 2018
    Assignee: TECHNOBOOST
    Inventors: Bernard Boucly, Eric Lecrux
  • Patent number: 9990973
    Abstract: A method and apparatus for using neighboring sampling points in a memory subsystem calibration is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller coupled thereto. A calibration unit in the memory controller is configured to perform calibrations of a data strobe signal and a reference voltage to determine eye openings for signals conveyed between the memory and the memory controller. Performing the calibration includes determining a number of different calibration points and computing initial scores for each of the calibration points. The method further includes calculating adjusted scores for each calibration point. For a given calibration point, the adjusted score includes weighted values of one or more calibration points that are adjacent thereto. The method further includes selecting a calibration point having the highest adjusted score as the calibrated value.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: June 5, 2018
    Assignee: Apple Inc.
    Inventors: Robert E. Jeter, Rakesh L. Notani, Fabien S. Faure
  • Patent number: 9971711
    Abstract: Selected portions of an uncore fabric of a system-on-a-chip (SoC) or other embedded system are divided into two independent pipelines. Each pipeline operates independently of the other pipeline, and each accesses only one-half of the system memory, such as even or odd addresses in an interleaved memory. However, the two pipelines are tightly coupled to maintain coherency of the fabric. Coupling may be accomplished, for example, by a shared clock that is one-half of the base clock cycle for the fabric. Each incoming address may be processed by a deterministic hash, assigned to one of the pipelines, processed through memory, and then passed to a credit return.
    Type: Grant
    Filed: December 25, 2014
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Ramadass Nagarajan, Michael T. Klinglesmith, Joydeep Ray
  • Patent number: 9966953
    Abstract: A low clock power data-gated flip-flop is provided. The data-gated flip-flop includes an exclusive OR component including a first exclusive OR input, a second exclusive OR input, and a first exclusive OR output. The first exclusive OR input is configured to receive a data input to the data-gated flip-flop. The data-gated flip-flop includes a first latch including a first latch data input and a first latch reset input, the first exclusive OR output being coupled to the first latch data input and the first latch reset input. The data-gated flip-flop includes a second latch having a data output, the data output coupled to the second exclusive OR input.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: May 8, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Qi Ye, Animesh Datta, Bo Pang
  • Patent number: 9904644
    Abstract: A system for managing internal-computer system communications including a processor, an SPI controller, an interconnector, and an SPI cluster containing multiple SPI interfaces, with the SPI interfaces being connected to one or more devices in the computer system or environment. The SPI cluster includes SPI interfaces that can convert communications to/from a plurality of device's formats to serialized digital formats suitable for ingest and actuation for the SPI controllers. The interconnector may use a differentially, optically, galvanometrically, inductively coupled driven wire and to enable communications between the SPI cluster constituents and the SPI controller. The SPI controller manages communications to the SPI interfaces that act as coordinated intermediates for device control and communications, thus insulating the computer system's processor from the increased workload of managing all internal system communications.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: February 27, 2018
    Assignee: Goodrich Corporation
    Inventors: Erik V. Rencs, Jennifer S. Richardson, Scott W. Ramsey
  • Patent number: 9823301
    Abstract: A method is presented for characterizing a digital circuit for determining an optimum operating point of the digital circuit. The digital circuit includes sequential elements; conducting data paths; a clock tree; a time fault sensor receiving as input a data signal and configured to detect during a detection window a transition of the data signal; and a system for setting first and second operating parameters of the circuit. The method includes a) activating a conducting data path leading to the sequential element coupled to the sensor; b) determining, for a given value of the first parameter, a first value of the second parameter from which the sensor detects a transition of the data signal during the detection window, the values of the first and second parameters defining an operating point of the circuit; and c) correcting the operating point.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: November 21, 2017
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventor: Ivan Miro Panades
  • Patent number: 9786353
    Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Mozhgan Mansuri, Aaron Martin, James A. McCall
  • Patent number: 9746877
    Abstract: A method for detecting and correcting an error in a circuit is provided. The circuit is configured to receive an input signal and clock the input signal with a rising and falling timing signal. The method includes detecting late arrival signal transition of the input signal, at an intermediate point of a path, the path being one through which the input signal transits. The method further includes predicting an error in the input signal in response to detecting the late arrival signal transition at the intermediate point of the path. In addition, the method includes correcting the error in the input signal by manipulating the timing signal and/or a supply voltage.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: August 29, 2017
    Assignee: Agency for Science, Technology and Research
    Inventors: Jun Zhou, Xin Liu
  • Patent number: 9729131
    Abstract: Apparatuses and methods for correcting a duty cycle of a clock signal are described. An example apparatus includes: a duty cycle corrector (DCC) that receives an input clock signal and a control signal and produces an output clock signal responsive, at least in part, to the input clock signal and the control signal; a circuit that divides a frequency of the input clock signal by a positive even integer and generates an intermediate clock signal; and a phase detector that generates the control signal responsive, at least in part, to a difference in phase between the output clock signal and the intermediate clock signal.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: August 8, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Katsuhiro Kitagawa
  • Patent number: 9621040
    Abstract: A PWM signal generator includes a delay circuit unit, which includes a plurality of delay elements connected in series, an output terminal of the delay element in a final stage among the plurality of delay elements and an input terminal of the delay element in an initial stage among the plurality of delay elements being connected to each other; a selector, which selects any one of output signals of the plurality of delay elements based on a digital value; a PWM signal output unit, which outputs a PWM signal based on the output signal selected by the selector; a delay-amount detector, which detects an amount of delay of a signal due to the delay circuit unit; and a digital value generator, which generates the digital value by correcting predetermined data based on the amount of delay detected by the delay-amount detector.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: April 11, 2017
    Assignee: Sanken Electric Co., LTD.
    Inventors: Kazuhiro Mima, Hiroki Yukiyama, Takanaga Yamazaki
  • Patent number: 9564885
    Abstract: Duty cycle error vectors that indicate both the magnitude and direction of the duty cycle error relative to a desired duty cycle are generated within a duty cycle measurement circuit, enabling threshold-based determination of whether duty cycle adjustment is necessary, refraining from power-consuming adjustment and follow-up measurement in those cases where the duty cycle is within a target range. When duty cycle adjustment is deemed necessary, the magnitude of the duty cycle error indicated by the duty cycle error vector may be applied to effect proportional rather than incremental duty cycle adjustment, quickly returning the clock duty cycle to a target range.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: February 7, 2017
    Assignee: Rambus Inc.
    Inventors: Pak Shing Chau, Wayne S. Richardson, Jun Kim
  • Patent number: 9515686
    Abstract: A transmitting circuit includes a plurality of transmitters, an operation clock generator, and a clock divider. Each of the transmitters outputs data serially. The operation clock generator generates an operation clock signal. The clock divider divides the operation clock signal to generate a symbol clock signal. The plurality of transmitters receives the operation clock signal and the symbol clock signal in common. A clock signal provided to one transmitter is equally synchronized with a clock signal provided to other transmitter(s).
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: December 6, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Ha Kim, Sanghune Park, Hwaseok Oh
  • Patent number: 9503348
    Abstract: An operating method of a control point includes setting a Maximum time for waits (MX) value for device discovery. The method also includes transmitting a message that includes the set MX value to at least one device connected with the control point. The method further includes receiving a response message in response to a Method for Search Request (M-SEARCH) message from the at least one device.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: November 22, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-Seob Kang, Seong-Il Hahm, Woo-Jin Park, Hun-Je Yeon
  • Patent number: 9494649
    Abstract: An integrated circuit (IC) measures uncertainties in a first signal. The IC comprises a programmable delay circuit to introduce a programmable delay to the first signal to generate a first delayed signal. The IC further comprises a digital delay line (DDL) comprising a first delay chain of delay elements having input to receive the first delayed signal. The DDL further comprises a set of storage elements, each storage element having an input coupled to an output of a corresponding delay element of the first delay chain, and an output to provide a corresponding bit of a digital reading. The DDL additionally comprises a decoder to generate a digital signature from the digital reading and a controller to iteratively adjust the programmed delay of the programmable delay circuit to search for a failure in a resulting digital signature.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: November 15, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Arun S. Iyer, Prashanth Vallur, Shraddha Padiyar, Amit Govil
  • Patent number: 9484895
    Abstract: A duty cycle tuner measures high and low periods of a signal, calculates an actual duty cycle, generates duty control signals based on the actual duty cycle and a desired duty cycle, and adjusts the duty cycle responsive to the duty control signals. The high and low periods are measured using high-speed counters to provide a high count for the high period and a low count for the low period. The actual duty cycle value is then computed from the high and low counts, and compared to the desired duty cycle value to generate increment and decrement signals which may be positive or zero, to increase, decrease or maintain the actual duty cycle. In this manner, even if the high and low counts are subject to variations due to process, temperature or power supply voltage, their ratio is independent of such variations, so the tuner is immune to those effects.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: November 1, 2016
    Assignee: International Business Machines Corporation
    Inventor: Takeo Yasuda
  • Patent number: 9459689
    Abstract: In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventors: Tapan A. Ganpule, Inder M. Sodhi, Yair Talker, Inbar Falkov, Tanveer R. Khondker
  • Patent number: 9436213
    Abstract: Provided is a clock data recovery circuit including a phase-frequency detector configured to detect a frequency and phase of a reference clock signal and control a frequency and phase of an internal clock signal based on the detected frequency, a frequency detector configured to detect a frequency of a data signal and, based on the detected frequency of the data signal, adjust the frequency of the internal clock signal; and a phase detector configured to detect a phase of the data signal based on the detected frequency of the data signal and adjust the phase of the internal clock signal. Accordingly, a timing controller that includes the clock data recovery circuit is capable of establishing data communication at high speeds when the system is powered on/off to reduce power consumption. Also, the timing controller does not need to include an additional external clock generation device, and is capable of achieving frequency synchronization using a non-precision clock signal generated in the timing controller.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: September 6, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Du-Ho Kim, Jong-Shin Shin
  • Patent number: 9404966
    Abstract: A performance characteristic monitoring circuitry includes a first delay circuitry providing a first delay path, where transmission of a data value over that first delay path incurs a first delay that varies in dependence on the performance characteristic. Reference delay circuitry is also included to provide a reference delay path, where transmission of the data value over the reference delay path incurs a reference delay. The reference delay circuitry includes components configured to provide a capacitive loading on the reference delay path in order to produce a self-compensating effect on the reference delay that causes the reference delay to be less sensitive than the first delay to variation in the performance characteristic. Comparison circuitry is then used to generate the output signal of the monitoring circuitry in dependence on a comparison of the first delay and the reference delay.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: August 2, 2016
    Assignee: ARM Limited
    Inventors: Sandeep Dwivedi, Betina Hold
  • Patent number: 9366718
    Abstract: A multi-die chip assembly is described, the multi-die chip assembly including at least one detection apparatus which detects manipulations of the multi-die chip assembly, the detection apparatus including a distributed circuit including a circuit whose elements are distributed among those dies which include the elements of a local reference circuit, the distributed circuit including a free running clock, at least one local reference circuit disposed in at least one die of the multi-die chip assembly, each of the local reference circuits including a free running clock, and at least one non-volatile memory, in which is stored during manufacture of the multi-die chip assembly, an allowed range of a result of a function having at least two arguments for each reference circuit a value of the frequency of the local reference circuit as manufactured, and a value of the frequency of the distributed circuit as manufactured, at least one element of the plurality of memories being disposed in each die including the elem
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: June 14, 2016
    Assignee: Cisco Technology Inc.
    Inventors: Chaim D. Shen-Orr, Lior Amarilio, Uri Bear
  • Patent number: 9356769
    Abstract: Certain aspects of the present invention provide methods and apparatus for synchronizing frequency-divided oscillating signals associated with multiple radio frequency (RF) paths to be in-phase. For certain aspects, a reset pulse is input to synchronization logic for a particular RF path, and this logic retimes the reset pulse to a local synthesizer clock in this RF path. The retimed reset pulse drives the reset input of a local frequency divider for this RF path and is also appropriately delayed, buffered, and then daisy-chained to the synchronization logic in the next RF path to be repeated therein. By appropriately resetting the local frequency dividers using the synchronization logic in this manner, the frequency-divided oscillating signals for the RF paths are synchronized to operate in-phase with one another.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: May 31, 2016
    Assignee: Qualcomm Incorporated
    Inventor: David Ta-Hsiang Lin
  • Patent number: 9330741
    Abstract: A semiconductor device including a data aligner that aligns input data in response to internal strobe signals obtained by dividing a data strobe signal to generate a first alignment data and a second alignment data. The semiconductor device may also include a phase sensor that generates a control clock signal in response to a clock signal and senses phases of the internal strobe signals with the control clock signal to generate a selection signal, and a data selector that selectively outputs the first and second alignment data as a first selection alignment data and a second selection alignment data in response to the selection signal.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: May 3, 2016
    Assignee: SK HYNIX INC.
    Inventor: Keun Soo Song
  • Patent number: 9203449
    Abstract: A delay quantity estimation apparatus comprises a first correlation value arithmetic unit to calculate a first correlation value as a correlation value between a first input signal and a feedback signal delayed with a first delay value; a second correlation value arithmetic unit to calculate a second correlation value as a correlation value between the first input signal and a feedback signal delayed with a second delay value; and a delay quantity estimation unit to estimate a delay quantity of the feedback signal with respect to the input signal on the basis of the first difference value as a difference between the first correlation value and the second correlation value, wherein the second delay value is a value given by adding a certain value to the first delay value.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 1, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Satoshi Matsubara, Hideharu Shako, Mitsuharu Hamano, Kazuo Nagatani
  • Patent number: 9077375
    Abstract: Some embodiments relate to a transmitting arrangement that includes a digital to time converter (DTC) with a reference generator and a modulation generator coupled to first and second input terminals thereof. A feedback path, which includes a phase and/or frequency measurement block and a phase and/or frequency correction block, is coupled between an output terminal of the DTC converter and the second input terminal of the DTC. The feedback path can help determine a phase or frequency correction word that can be applied to a modulation control word provided by the modulation generator to tune or correct the modulation control word before it reaches the DTC. In this way, the transmitting arrangement facilitates extremely accurate phase alignment and helping achieve extremely accurate signal transmission.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: July 7, 2015
    Assignee: Intel Mobile Communications GmbH
    Inventor: Markus Scholz
  • Patent number: 9030242
    Abstract: A data output timing control circuit for a semiconductor apparatus includes a phase adjustment unit. The phase adjustment unit is configured to shift a phase of a read command as large as a code value of the delay control code in sequential synchronization with a plurality of delayed clocks obtained by delaying the external clock as large as predetermined delay amounts, respectively, delay the shifted read command as large as the variable delay amount, and output the result of delay as an output enable flag signal.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: May 12, 2015
    Assignee: SK Hynix Inc.
    Inventor: Kyung Hoon Kim
  • Patent number: 9013216
    Abstract: Disclosed is a digital phase-locked-loop including: a time-to-digital converter (TDC) configured to output a digital bit based on an input clock and a reference clock, in which the TDC includes: a first arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a first average offset and output a first logic value; a second arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a second average offset and output a second logic value; and a signal processor configured to output the digital bit based on the first and second logic values.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: April 21, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyun Ho Boo, Byung Hun Min, Duong Quoc Hoang, Cheon Soo Kim, Hyun Kyu Yu
  • Patent number: 9013215
    Abstract: A signal processing apparatus includes: a signal conversion circuit, for performing a signal conversion operation on a reception signal to generate a first output signal according to a first clock signal, and performing the signal conversion operation on the reception signal according to a second clock signal to generate a second output signal; an amplitude adjustment circuit, coupled to the signal conversion circuit, for calculating an amplitude value of the reception signal according to the first output signal, and accordingly adjusting an amplitude of the reception signal; and a phase adjustment circuit, for adjusting a phase of the second clock signal according to the second output signal.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: April 21, 2015
    Assignee: MStar Semiconductor, Inc.
    Inventors: Chien-Sheng Chen, Shih-Chieh Yen, Chien-Shan Chiang, Ying-Chieh Chiang
  • Publication number: 20150102846
    Abstract: A controller sets a selector register of programmable delay signal logic is to a value equal to a required number of clock cycles of delay for signals output from an integrated circuit to an external memory. The controller controls a selection of additional logic along the output path to perform on the delayed signal within a clock cycle without any latency added to the output path by delay signal logic outputting the delayed signal. The controller waits required number of clock cycles after setting the selector register before using the delayed signal output by the delay signal logic onto an output path.
    Type: Application
    Filed: December 23, 2014
    Publication date: April 16, 2015
    Inventors: HUU N. DINH, ROBERT S. HORTON, BILL N. ON
  • Publication number: 20150103964
    Abstract: The CDR circuit 100 includes first to second data delaying cells ID1, ID2. The CDR circuit 100 includes first to fourth oscillation delaying cells IC1, IC2, IC3, IC4. The CDR circuit 100 outputs a second data signal d2 at a data output terminal TDout as a recovery data signal Dout. The CDR circuit 100 outputs an oscillation clock signal a0 at a clock output terminal TRCK as a recovery clock signal RCK.
    Type: Application
    Filed: August 21, 2014
    Publication date: April 16, 2015
    Inventors: Junji Wadatsumi, Shouhei Kousai, Daisuke Miyashita
  • Patent number: 9000817
    Abstract: Apparatuses and methods related to altering the timing of command signals for executing commands is disclosed. One such method includes calculating a forward path delay of a clock circuit in terms of a number of clock cycles of an output clock signal provided by the clock circuit and adding a number of additional clock cycles of delay to a forward path delay of a signal path. The forward path delay of the clock circuit is representative of the forward path delay of the signal path and the number of additional clock cycles is based at least in part on the number of clock cycles of forward path delay.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: April 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jongtae Kwak, Kallol Mazumder
  • Patent number: 8994424
    Abstract: A logic unit is configured with least one multiplexor distributed along a delay path of a logic unit, wherein each at least one multiplexor is configured to receive two inputs and output one of the two inputs, wherein each at least one multiplexor is configured to select one of the two inputs to control a particular programmable number of clock cycles of delay added to a signal from 1 to N clock cycles. The logic unit is configured with at least two latches distributed along the delay path of the logic unit, wherein each at least one latch is configured to add a clock cycle of delay, wherein a terminating latch from among the at least two latches is configured to output the signal delayed by the particular programmable number of clock cycles.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Huu N. Dinh, Robert S. Horton, Bill N. On
  • Patent number: 8988955
    Abstract: Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply sensitivities of delays of a forward clock path and of a feedback clock path. Another example method includes providing an output clock signal in phase with an input clock signal and compensating for delay error between delays used in providing at least some of the delay of the output clock signal relative to the input clock signal by providing delays having power supply sensitivities resulting in a combined power supply sensitivity that is inverse to the delay error.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: March 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Yantao Ma, Tyler Gomm
  • Patent number: 8983012
    Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: March 17, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Gregory Lee Christison
  • Patent number: 8963646
    Abstract: The delay line degradation protection architecture as build-in ring oscillation apparatus includes a two gates logical circuit, a buffer, a clock input buffer and a delay lock loop circuit. The two gates logical circuit receives a clock enable signal, specific mode signal, and delayed clock output signal. The two gates logical circuit performs a logical operating on the clock enable signal, the specific mode signal and the delayed clock output signal for generating a mode selecting signal. The buffer generates a feedback signal according to the mode selecting signal and a control signal. The clock input buffer decides whether to transport the input clock signal to an output end of the clock input buffer or not according to the feedback signal. The delay lock loop circuit generates the delayed clock output signal. A frequency of the feedback signal is adjusted according to the control signal.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: February 24, 2015
    Assignee: Nanya Technology Corporation
    Inventor: Yantao Ma
  • Patent number: 8957736
    Abstract: The oscillation method uses an oscillation circuit in which a plurality of MOSFETs are annularly connected. The method comprises the steps of: forming GND of the circuit, which is separated from GND of a driving electric source of the MOSFETs, in a part of a first connection line which connects the MOSFET with the adjacent MOSFET; connecting a probe with a second connection line which connects another MOSFET with the adjacent MOSFET, an odd number of the MOSFETs being connected between the GND and the second connection line; and generating an oscillation waveform between the probe and the GND.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: February 17, 2015
    Inventor: Akira Takizawa
  • Patent number: 8957714
    Abstract: A master measure circuit is disclosed that may select from various nodes on a delay path carrying a signal. The master measure circuit measures the delay for propagation of the signal from one selected node to another selected node and controls an adjustable delay circuit in the delay path accordingly.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 17, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Vaishnav Srinivas, Jan Christian Diffenderfer, Philip Michael Clovis, David Ian West
  • Patent number: 8952737
    Abstract: A method for calibrating a delay locked loop (“DLL”) having a plurality of delay segments, comprises: determining segment delay values for the delay segments; calculating a full-cycle delay value for an input signal to the DLL; adjusting one or more of the segment delay values as a function of the full-cycle delay value to generate one or more adjusted delay values; and calculating weights for the delay segments as a function of the segment delay values, the full-cycle delay, and the one or more adjusted delay values, wherein the weights are used to calibrate the DLL.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: February 10, 2015
    Assignee: Kool Chip, Inc.
    Inventors: Kishore Mishra, Purna C. Mohanty, Venkata N. S. N. Rao
  • Patent number: 8947124
    Abstract: An integrated circuit device comprising first circuitry including first logic devices and a clock tree for distributing a clock signal to the first logic devices and second circuitry comprising second logic devices, a first clock gater and a second clock gater. The first and second clock gaters comprise a programmable delay circuit.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: February 3, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Deepesh John, Teja Singh, Sundar Rangarajan
  • Patent number: 8947141
    Abstract: A differential amplifier may be configured to have a duty cycle and/or gain that is adjustable, such as by adjusting the switch points of circuitry in the differential amplifier. The differential amplifier may alternatively or additionally have a hysteresis function by, for example, using a signal feedback from the output of the amplifier to adjust the switch points of circuitry in the differential amplifier. The differential amplifier may be used for a variety of purposes, such as in an input buffer or delay line, either of which may be used, for example, in a clock generator circuit.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Willey
  • Patent number: 8947140
    Abstract: Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: February 3, 2015
    Assignee: Uniquify, Inc.
    Inventors: Venkat Iyer, Prashant Joshi, Jung Lee
  • Patent number: 8941422
    Abstract: Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: January 27, 2015
    Assignee: Uniquify, Inc.
    Inventors: Venkat Iyer, Prashant Joshi, Jung Lee
  • Patent number: 8941425
    Abstract: Provided is a semiconductor device for compensating for an internal skew without training with an external device. The semiconductor device includes a signal generating unit configured to generate and output a reference signal, a first receiving unit configured to receive the reference signal and output a first output signal, a second receiving unit configured to receive the reference signal and output a second output signal, a delay unit configured to delay the first output signal by a certain time and output a delayed signal, a sampling unit configured to sample the second output signal based on the delayed signal and output sampling data, and a skew controlling unit configured to control the delaying unit based on the sampling data.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: January 27, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Bin Song, Tae-Pyeong Kim, Cheon-Oh Lee
  • Patent number: 8941423
    Abstract: Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: January 27, 2015
    Assignee: Uniquify, Incorporated
    Inventors: Venkat Iyer, Prashant Joshi, Jung Lee
  • Publication number: 20150015314
    Abstract: A method and a system are provided for synchronizing a signal. A keep out window is defined relative to a second clock signal and an edge detection signal is generated that indicates if an edge of a first clock signal is within the keep out window. The edge detection signal may be filtered. An input signal is received in a domain corresponding to the first clock signal and a delayed input signal is generated. Based on the edge detection signal or the filtered edge detection signal, either the input signal or the delayed input signal is selected, to produce an output signal in a domain corresponding to the second clock signal.
    Type: Application
    Filed: July 15, 2013
    Publication date: January 15, 2015
    Inventor: William J. Dally