Abstract: An apparatus for processing a signal and method thereof are disclosed. The present invention includes receiving coding mode information indicating a speech coding scheme or an audio coding scheme, linear prediction coding degree information indicating a linear prediction coding degree, and the signal including at least one of a speech signal and an audio signal; decoding the signal according to the speech coding scheme or the audio coding scheme based on the coding mode information; decoding linear prediction coding coefficients of the signal based on the linear prediction coding degree information; and generating an output signal by applying the decoded linear prediction coding coefficients to the decoded signal. In this case, the linear prediction coding degree information is determined based on a variation of a value of an LPC residual generated from performing the linear prediction coding on the signal.

Abstract: A method and apparatus for mitigating offsets in an interpolator are disclosed. In the method and apparatus, a first number of clock cycles of a first clock signal observed over a first clock cycle of a second clock signal is determined and then stored. Also a second number of clock cycles of the first clock signal observed over a second clock cycle of the second clock signal subsequent to the first clock cycle is determined and stored. The first number of clock cycles and the second number of clock cycles are compared to determine whether they are different from each other. If they are different from each other, a reset signal is asserted under control of the second clock signal to reset at least one of a derivator stage and an integrator stage of an interpolator.

Abstract: A multi-stage passive capture adapter (PCA) circuit is configured to sense and recover digital signals present on a high-speed serial bus for capture and analysis in external test equipment. A first stage of the PCA circuit includes a differentiator that functions as a high impedance probe that contacts the serial bus to capture an original input signal waveform of the high-speed digital signals. The signal waveform is fed to a dual-slope comparator/driver that includes a plurality of high-speed comparators and drivers. The second stage includes a differential receiver/shaper that converts logic levels of differential receiver outputs to input signals that set and reset a signal restorer whose output signals are fed to a driver of a driver/shaper. The output of the driver is then fed to a shaper network configured to substantially match an output signal of driver/shaper to the input signal waveform sensed from the high-speed serial bus.

Abstract: A multi-stage passive capture adapter (PCA) circuit is configured to sense and recover digital signals present on a high-speed serial bus for capture and analysis in external test equipment. A first stage of the PCA circuit includes a differentiator that functions as a high impedance probe that contacts the serial bus to capture an original input signal waveform of the high-speed digital signals. The signal waveform is fed to a dual-slope comparator/driver that includes a plurality of high-speed comparators and drivers. The second stage includes a differential receiver/shaper that converts logic levels of differential receiver outputs to input signals that set and reset a signal restorer whose output signals are fed to a driver of a driver/shaper. The output of the driver is then fed to a shaper network configured to substantially match an output signal of driver/shaper to the input signal waveform sensed from the high-speed serial bus.

Abstract: There is provided a modulation profile generator and spread spectrum clock generator including the modulation profile generator. The modulation profile generator includes an input signal generator that generates an input signal; a function calculator that outputs a function calculation result in the form of a square root graph by using the input signal as an input of a function; and a profile generator that generates a non-linear modulation profile based on the function calculation result. As a result, it is possible to effectively reduce electromagnetic interference.

Abstract: Some embodiments of the invention relate to a DC offset correction circuit comprising a feedback loop having a DAC controlled by a reconfigurable ADC, which determines (e.g., tracks) the mean value of a modulated input signal. The circuit operates according to two phase process. In a first “pre-modulation” tracking phase, an input signal is tracked by the ADC, which is configured to output the input signal's mean value as a digital code equivalent to the input mean value. The output of the ADC is provided to a DAC, which provides an analog representation of the mean value to an adder that subtracts the mean value from the modulated input signal to generate a bipolar adjusted input signal. In a second “modulation” phase, the estimated mean value is held constant, so that the bipolar adjusted input signal may be provided to an activated modulation circuit for improved system performance.

Abstract: Circuits, demultiplexers, and methods are disclosed. A circuit includes a reference clock input to receive clock pulses at a reference clock speed. An internal divided clock input receives a divided clock signal from a clock divider that is driven by the clock pulses. The clock divider generates the divided clock signal at a second clock speed that is a fraction of the reference clock speed. An external divided clock input receives an external divided clock signal. The external divided clock signal is driven by the clock pulses and operates at the second clock speed. A clock transition synchronization circuit suppresses application of one or more of the clock pulses to the clock divider when the divided clock signal transitions between clock states out of synchronization with the external divided clock signal.

Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal ?(0) to ?(2i?1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal ?(0) to j(2i?1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal ?(0) to ?(2i?1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

Abstract: A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent.

Abstract: The circuit arrangement (1) comprises an input (2) for the connection of an oscillator (3) and an amplifier circuit (20) having a first input (21) that is coupled to the input (1) of the circuit arrangement (1), having a second input (22) and an output (23) that is connected to an output (4) of the circuit arrangement (1). A clock signal (Vout) with a duty cycle (?) can be accessed at the output (4) of the circuit arrangement (1). The circuit arrangement (1) furthermore incorporates a low-pass filter (40), the input of which is connected to the output (23) of the amplifier circuit (20), and an integrator circuit (50) the input of which is connected to the low-pass filter (40) and the output of which is connected to the second input (22) of the amplifier circuit (20) for the delivery of an adjustable threshold value (Vth) for controlling the duty cycle (?).

Abstract: A method for identifying a drifted dose integrator in an implantation system and an implantation system are provided. The implantation system includes a first dose integrator and a second dose integrator. The first dose integrator includes a first input configured to receive a first current generated from charges carried by implanted ions in a wafer, and a first output configured to output a first accumulated dosage value. The second dose integrator includes a second dose integrator including a second input configured to receive a second current generated from the charges carried by the implanted ions in the wafer, and a second output configured to output a second accumulated dosage value. The implantation system further includes a processing unit comparing the first accumulated dosage value and the second accumulated dosage value to detect a drift in one of the first and the second dose integrators.

Abstract: A system and method for preventing push-out theft includes a network of electronic devices that are collectively operable in either a “safe restart” mode” or in an “operational” mode. The network is installed in a shopping area and prevents shopping cart removal from the area when in the “operational” mode. It does this by initially issuing egress permits to every shopping cart. The network then selectively removes egress permits when a shopping cart enters a selected section of the shopping area. Another egress permit is issued when the shopping cart successfully passes a cashier location. Otherwise, a sentry beacon will disable a shopping cart with no egress permit, before it can leave the shopping area. The network defaults to a permit issuing mode whenever a component of the system becomes inoperable.

Abstract: A noise shaping quantizer having a first noise shaping quantization unit for applying a first noise shaping operation on an input signal.

Abstract: Replica output buffers, having the same input/output characteristic as that of an output buffer, respond to the rise of a TEST signal generated by a test pulse generating circuit and causes an output signal to rise at a through rate according to voltage of an SL_SET signal, and causes an output signal to fall at a through rate according to voltage of a CNT signal. A phase comparing circuit makes a comparison between phases of the signals output from the replica output buffers, and outputs an UP signal or Down signal with a length corresponding to a phase difference to a delay control circuit. The delay control circuit changes the voltage of the CNT signal according to the UP signal and the DOWN signal, and adjusts a through rate at which a signal output from the output buffer falls.

Abstract: A device for converting a current pulse signal into a voltage pulse signal through a conversion from a current to a voltage includes a converting unit converting the current pulse signal into a first voltage signal, a voltage reducing unit generating a second voltage signal by reducing a magnitude of the first voltage signal, a delay unit generating a third voltage signal by delaying the second voltage signal, and a comparison unit generating the voltage pulse signal by comparing the first voltage signal with the third voltage signal.

Abstract: A pulse generating circuit for use in a semiconductor memory device is triggered by a transition of an input logic signal, to provide an output pulse having a predetermined pulse width or period. Feedback from the output pulse is used to isolate the input signal once the output pulse has begun, so as to prevent premature truncation of the output pulse if the input signal changes state during the output pulse period. This pulse generator is particularly advantageous in high-speed semiconductor memory integrated circuits where the input pulse may be relatively brief.

Abstract: There is disclosed a rectangular filter which has a simple configuration and is capable of producing an improved rectangular wave. An input step wave is differentiated by a differentiator circuit and amplified by a first amplifier. The output from the amplifier is inverted by an inverting amplifier having a gain of -1. The output from the first amplifier is integrated by an integrator circuit having a time constant equal to the time constant of the differentiator circuit. The output from the inverting amplifier and the output from the integrator circuit are summed up by an adding circuit. The input signal is faithfully reproduced at the output of the adding circuit. After a given time passes since the input signal has been applied, the capacitor of the integrator circuit is shorted out. In this way, a rectangular wave is obtained. There is also disclosed a filter amplifier comprising this rectangular filter and a gated integrator for integrating the output from the rectangular filter for a predetermined time.

Abstract: A noise shaper includes an incomplete integrator which conducts an addition of a present data and a last sampled data stored and a positive coefficient smaller than 1, a complete integrator which conducts an addition of a storage data before one sample delay and a present data, a three-value quantizing circuit which outputs 0, +1 or -1 signal as an output signal, and a feedback circuit which feeds-back the output signal from the three-value quantizing circuit to the incomplete integrator and the complete integrator. The noise shaper may further include a delay-data supply selection circuit which supplies the last sampled data stored and the positive coefficient to the incomplete integrator only when the output signal supplied from the three-value quantizing circuit through the feed-back circuit is zero. The output signal from the noise shaper can be made zero without deteriorating signal to noise (S/N) ratio when no input signal is inputted to the noise shaper.

Abstract: Binary current signals are differentiated to produce pulses indicative of the front and rear edges. The pulses are amplified and utilized in a latch to regenerate binary voltage signals which are amplified replicas of the input signals. Because of the input differentiator the sensitivity of the circuit remains high while the latched output makes the circuit burst mode ready.