Abstract: A storage device includes a nonvolatile memory device and a controller that accesses the nonvolatile memory device based on a request of an external host device, receives a first clock signal from the external host device, generates a second clock signal through frequency multiplication of the first clock signal, and communicates with the external host device based on the second clock signal. The controller requests the external host device to adjust a multiplication ratio for the frequency multiplication of the first clock signal.

Abstract: A display device may include a display panel including a gate line, a data line, and a pixel electrically connected to the gate line and the data line, where display panel displays an image based on input image data, a gate driver which outputs a gate signal to the gate line, a data driver which outputs a data voltage to the data line, and a power supply voltage generator which provides a driving voltage to the display panel, the gate driver and the data driver. The power supply voltage generator generates a gate clock signal based on an on-clock signal and an off-clock signal and changes a count value of the on-clock signal or the off-clock signal when the gate clock signal is an abnormal signal.

Abstract: Example embodiments relate to radar transceivers. One embodiment includes a radar transceiver. The radar transceiver includes a chirp generator for generating a chirp having an initial frequency and a final frequency. The radar transceiver also includes a controllable variable gain amplifier having an input connected to an output of the chirp generator. Further, the radar transceiver includes a control unit connected to a control input on the chirp generator and to a control input on the controllable variable gain amplifier. The control unit is adapted to output a first control signal to the chirp generator such that the chirp generator starts generating the chirp. The control unit is also adapted to output a second control signal to the controllable variable gain amplifier such that the controllable variable gain amplifier starts increasing an amplification in the controllable variable gain amplifier from a first amplification level to a second amplification level.

Abstract: Apparatus and associated methods relate to detection of an overcurrent condition by determining if a voltage across a current-sense resistor exceeds a predetermined voltage threshold. The voltage at each side of the current-sense resistor is sensed indirectly, through a diode network. The diode networks through which the voltages on each side of the current-sense resistor are biased differently from one another. Such differently-biased diode networks translate the voltages at each side of the current-sense resistor by different amounts, the biasing of these diode networks is such that a voltage difference between the second terminals of the first and second diode networks is of a first polarity during normal current conditions, and the voltage difference between the second terminals of the first and second diode networks is of a second polarity during overcurrent conditions.

Abstract: A LED driving apparatus with differential signal interfaces is introduced, including: N-stages LED drivers, wherein the first stage LED driver receives a first data packet differential signal and a first clock differential signal and outputs a second data packet differential signal and a second clock differential signal, the Mth stage LED driver receives a Mth data packet differential signal and a Mth clock differential signal and outputs a (M+1)th data packet differential signal and a (M+1)th clock differential signal.

Abstract: A semiconductor device includes two-terminal memory devices characterized by a range of program voltages and a first capacitance, wherein the two-terminal memory devices are coupled in parallel between ground and a first common node, a first capacitor having a second capacitance, coupled between ground and a second common node, a voltage source configured to provide an input voltage lower than the range of program voltages, a first operational amplifier including an inverting input, a non-inverting input, and an output, wherein the non-inverting input is coupled to the first voltage source, wherein the inverting input is coupled to a third common node, and wherein the output is coupled to a fourth common node, a first resistance device coupled between the third common node and the fourth common node, and wherein the first common node is coupled to the second common node and the third common node.

Abstract: A client computing system (CCS) receives a download including (i) an image representative of a vehicle component, (ii) symbol data associated with a first symbol, (iii) a set of one or more selectable identifiers, and (iv) supplemental information associated with the vehicle component. Each selectable identifier can indicate a respective portion of the supplemental information. After receiving the download, the CCS displays the image and the first symbol without displaying the set and the supplemental information. While the image and the first symbol are displayed without the set, the CCS receives a first input corresponding to selection of the first symbol. The CCS then responsively displays the set. While the set is displayed, the CCS receives a second input corresponding to selection of a first selectable identifier from the set. The CCS then responsively displays the respective portion of the supplemental information indicated by the first selectable identifier.

Abstract: The present invention provides a signal detection circuit, wherein the signal detection circuit includes a sampling circuit and a determination circuit. In the operations of the signal detection circuit, the sampling circuit uses a plurality of clock signals to sample an input signal to generate a sampling result, wherein the plurality of clock signals have different phases, and frequencies of the plurality of clock signals are lower than a frequency of the input signal. The determination circuit refers to the sampling result to determine if the input signal comprises valid data, so as to determine if the input signal comes from outside a chip, wherein the chip includes the signal detection circuit.

Abstract: An integrated circuit includes: a phase-shifted data signal generation circuit configured to generate a plurality of phase-shifted data signals from an input data signal based on at least one phase-shifted clock signal; a synchronization circuit configured to generate a plurality of synchronization data signals by applying the at least one phase-shifted clock signal to the plurality of phase-shifted data signals provided by the phase-shifted data signal generation circuit; and a control signal generation circuit configured to perform logic operations on the plurality of synchronization data signals to generate a phase control signal for controlling a phase of the at least one phase-shifted clock signal, and generate a frequency control signal for controlling a frequency of the at least one phase-shifted clock signal.

Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

Abstract: A differential data transmitter with pre-emphasis comprises a main driver coupled to receive an input data stream and to produce a main differential output stream which varies with the input stream, circuitry which provides a delayed and inverted version of the input stream, and a first pre-emphasis driver coupled to the output of the circuitry and arranged to produce a pre-emphasis differential output stream which varies with the delayed and inverted input stream. The pre-emphasis differential output stream is coupled to the main differential output stream to produce differential data transmitter output signals. The main and pre-emphasis drivers operate in parallel, with the pre-emphasis driver boosting the output signals when consecutive bits in the input stream change state, and attenuating the output signals when consecutive bits in the input stream do not change state.

Abstract: A transceiver system compensates for baseline wandering in an analog signal in the analog stage before sampling the analog signal and processing the analog signal in the digital stage. The transceiver system includes an analog to digital converter that samples the analog signal after baseline wandering compensation, a digital equalizer to condition the digital samples, and the slicer to determine transmitted symbols from the digital samples. The transceiver system includes a subtraction block that determines the difference between an input and an output of the slicer, a digital to analog converter that converts a difference between the input and the output of the slicer, a low pass filter that filters out high frequency components of the difference between the input and the output of the slicer thereby to extract out the baseline wandering, and a signal summation circuit that subtracts the baseline wandering from the analog signal.

Abstract: A GOA driving circuit includes a plurality of cascaded GOA units and outputs a gate driving signal to an Nth-stage horizontal scanning line of a display region by an Nth-stage GOA unit. The Nth-stage GOA unit includes a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down sustaining unit, a download unit, and a bootstrap capacitor unit. The pull-up unit, the pull-down unit, the pull-down sustaining unit, and the bootstrap capacitor unit are respectively electrically connected with a first node and an Nth-stage horizontal scanning line. The pull-up control unit and the download unit are electrically connected with the first node. N is a positive integer. The Nth-stage GOA unit further includes a forced pull-down unit, which is used to force the first node to low level when clock signals are disappeared. A LCD device is also provided.

Abstract: A device for generating a duty cycle includes a converter, a corrector, and a control circuit. The converter is configured to generate a first output signal having a duty cycle to an output terminal according to an input signal. The corrector is coupled to the output terminal, and is configured to adjust the duty cycle of the first output signal according to a control signal. The converter is coupled in parallel with the corrector and between a first power source and a second power source. The control circuit is coupled to the output terminal, and is configured to generate the control signal according to the first output signal and a reference signal.

Abstract: A signal receiver circuit may include: a receiver suitable for generating a received signal based on comparison of an input signal with a reference voltage during a normal operation and based on comparison of the input signal with a target voltage during a training operation; a compensator suitable for applying a weight to the received signal to compensate for the input signal; and a weight adjuster suitable for adjusting the weight based on a level of the received signal during the training operation, wherein during the training operation, the input signal toggles between first and second levels, and the receiver is enabled when the input signal is at the first level.

Abstract: A read-out method of an image sensing device includes: firstly counting a reset signal of a pixel signal based on a first analog gain during a first period of a unit row period; storing a result of the first counting as a previous counting result; secondly counting the reset signal based on a second analog gain; thirdly counting a data signal of the pixel signal based on the second analog gain during a second period following the first period in the unit row period; storing a first counting signal corresponding to results of the second counting and the third counting; fourthly counting the data signal based on the first analog gain during a third period following the second period in the unit row period; and storing a second counting signal corresponding to the previous counting result and a result of the fourth counting.

Abstract: This disclosure provides a display system, which comprises: a mainframe; a control module comprising an image processing unit and an image compositing unit, communicating with the mainframe through a first channel and a second channel, and generating an image signal; and a display panel showing pictures according to the image signal; wherein the mainframe provides the image processing unit with image data, parameter data and control signals through both the first and second channels when the first channel works, and the image processing unit processes the image data and the parameter data and generates a first data signal to be the image signal; wherein the mainframe provides the image compositing unit with response data through the second channel when the first channel fails, and the image compositing unit combines the response data and a pre-determined background into a second data signal to be the image signal.

Abstract: An apparatus can include a test power supplier comprising a power supply to sense resistance between electrodes of a touch sensor, and a comparison unit configured to compare the sensed resistance between the electrodes with an allowable threshold to output a comparison result.

Abstract: An method of driving an AMOLED is provided, including: dividing grayscale values of each pixel of each frame into N portions, so as to obtain N PWM driving signals of an organic light emitting diode; dividing the driving time of each frame of the organic light emitting diode into N sub-driving times, wherein one of the sub-driving times of each frame corresponds to one of the PWM driving signals; and transmitting all of the PWM driving signals of each frame to the organic light emitting diode at the corresponding sub-driving time, so as to drive and display an image.

Abstract: A clock detector a first delay circuit delaying an input clock by a first delay time and outputting the delayed input clock as a delayed clock signal, an edge detection circuit receiving the input clock and the delayed clock signal to generate an output signal including pulses which are created in synchronization with edges of the input clock, a delay/inversion circuit delaying the output signal of the edge detection circuit by a second delay time and inverting the delayed output signal to output the inverted signal as an output signal, a first flip-flop receiving the input clock to generate a first output signal, a second flip-flop receiving the first output signal to generate a second output signal, and a clock detection signal generation circuit receiving the first and second output signals to generate a clock detection signal.

Abstract: A delay cell includes first through fifth inversion circuits. The first inversion circuit inverts an input signal, and an output electrode of the first inversion circuit is coupled to a first node. The second inversion circuit is turned on in response to a control signal, and inverts the input signal when turned on. An output electrode of the second inversion circuit is coupled to the first node. The third inversion circuit inverts a signal at the first node, and an output electrode of the third inversion circuit is coupled to a second node. The fourth inversion circuit is turned on in response to the control signal, and inverts the signal at the first node when turned on. An output electrode of the fourth inversion circuit is coupled to the second node. The fifth inversion circuit inverts a signal at the second node to generate an output signal.

Abstract: A CDR control circuit detects a phase shift of input data that is taken in with a phase-adjusted clock, and generates phase control data that controls the phase of the clock based on the detected phase shift, the CDR control circuit includes a change detection circuit that detects an over-change in the phase shift; and a selection circuit that outputs the phase shift before the change, which is the phase shift before the time of detection of the over-change, as the phase shift for a predetermined period of time at the time of detection of the over-change, wherein during the predetermined period of time, the phase control data is generated based on the phase shift before change.

Abstract: Disclosed is a display device and a method of driving the display device. The display device includes a display panel, a scan driving unit, and a timing control unit. The display panel displays an image. The scan driving unit supplies a scan signal to the display panel. The timing control unit controls the scan driving unit. The scan driving unit includes a correction circuit unit that detects whether a clock signal output by the timing control unit is normal or abnormal, and corrects the detected abnormality.

Abstract: An apparatus includes analog or mixed-signal circuitry that operates in response to a first signal, and digital circuitry that operates in response to a second signal. The apparatus further includes a signal retiming circuit. The signal retiming circuit retimes an output signal of a digital signal source to reduce interference between the digital circuitry and the analog or mixed-signal circuitry by retiming edges of the output signal of the digital signal source to fall on cycle boundaries of the first signal.

Abstract: A transmitter including a noise signal generator and a summing element is provided. The noise signal generator is configured to receive multiple noise settings and output multiple noise signals corresponding to the multiple noise settings. The summing element is configured to receive a transmit data signal and the multiple noise signals, sum one or more of the multiple noise signals with the transmit data signal, and output to a transmit driver configured to generate one of a single-ended and a differential signal based on the sum of the one or more of the multiple noise signals with the transmit data signal.

Abstract: This disclosure generally provides a system, active input device, and method for generating an amplified square wave signal based on an input signal. The method comprises generating a pulse signal based on the input signal, and driving a switching signal based on the pulse signal to control a first switch. A pulse width of the pulse signal is adaptively controlled using a control signal generated based on the amplified square wave signal. An output terminal of the first switch is coupled with a second switch, and the switching signal controls current entering into the second switch. The method further comprises driving the input signal to control a third switch coupled with the second switch. The amplified square wave signal is generated at the second output terminal based on the switching signal and on the input signal.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a first information handling resource communicatively coupled to the processor, and a second information handling resource communicatively coupled to the processor and the first information handling resource. The first information handling resource and the second information handling resource may be configured to, in concert determine an optimum delay between opposite polarity signals for differential signals communicated from the first information handling resource to the second information handling resource via a path comprising a differential pair and transmit data from the first information handling resource to the second information handling resource via the path by inserting a delay into one of the opposite polarity signals equal to the optimum delay.

Abstract: A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.

Abstract: A phase detector and retimer circuit that includes a retimer circuit, a phase shift circuit coupled to the retimer circuit, and an error signal generation circuit coupled to the retimer circuit and the phase shift circuit. The retimer circuit is configured to receive a data signal and generate a first retimed data signal based on a first phase of a clock signal and a second retimed data signal based on a second phase of the clock signal. The phase shift circuit is configured to receive the data signal and phase shift the data signal to generate first, second, third, and fourth phase shifted data signals. The error signal generation circuit is configured to generate a first error signal and a second error signal based on the first and second retimed data signals and the first, second, third, and fourth phase shifted data signals.

Abstract: A semiconductor apparatus include a signal level switching decision unit and a transmitter unit. The signal level switching decision unit generates a switching control signal according to off-current of transistors included therein. The transmitter unit outputs a transmitter input signal as a transmitter output signal in response to a switching control signal.

Abstract: Embodiments described herein include an input device that drives an equalization signal onto an electrode that may be capacitively coupled to a sensor electrode used for capacitive sensing. The equalization signal may include a plurality of pulses that are synchronized to be out of phase with a capacitive sensing signal driven on the sensor electrode. For example, as the capacitive sensing signal transitions from a low voltage to a high voltage, the equalization signal transitions from a high voltage to a low voltage. Doing so increases the voltage difference between the electrodes and increases the slew rate of the capacitive sensing signal. In further embodiments, where the input device includes a display device, the equalization signal may be driven onto display electrodes that are used when updating a display.

Abstract: An apparatus includes a first circuit of a first type that couples an output node to a first power supply node in response to a first value of a control signal. The apparatus includes a second circuit of a second type to couple the output node to the first power supply node in response to a first value of a first signal having a first voltage swing. The apparatus includes a third circuit of the second type to couple the output node to a second power supply node in response to a second value of the first signal. The apparatus includes a control circuit that generates the control signal based on the first signal and an output signal on the output node. The first, second, and third circuits generate an output signal on the output node. The output signal has a second voltage swing less than the first voltage swing.

Abstract: Aspects of the present invention include a power supply system comprising a plurality of power supplies. Each of the power supplies can include an oscillator system configured to generate a clock signal at a clock node. Each of the power supplies can include an error amplifier configured to generate an error voltage at an error amplifier output node. Each of the power supplies can also include a pulse-width modulation (PWM) generator configured to generate a PWM switching signal based on an error voltage and the clock signal. Each of the power supplies can further include a power stage configured to generate an output voltage based on the PWM switching signal.

Abstract: A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits.

Abstract: A voltage converting apparatus and a sub-harmonic detector are disclosed. The sub-harmonic detector includes a pulse eliminating circuit, a counter, and a comparator. The pulse eliminating circuit receives a pulse width modulation (PWM) signal and a reference PWM signal having a same period. The PWM signal and reference PWM signal has a plurality of pulses and reference pulses respectively. The pulse eliminating circuit eliminates at least one part of the pulses which overlap with the reference pulses for generating a processed signal. The counter counts the processed signal and the PWM signal during a time period to obtain first and second counting values. The comparator compares the first and second counting values for detecting whether a sub-harmonic condition happens or not in the PWM signal.

Abstract: A redriver chip is inserted between a transmitter chip and a receiver chip and re-drives differential signals from the transmitter chip to the receiver chip. The redriver chip has switched output termination that switches to a high value to detect far-end termination at the receiver chip, and to a low value for signaling. An output detector detects when the receiver chip has termination to ground and enables switched input termination to provide termination to ground on the lines back to the transmitter chip so that the far-end termination on the receiver chip is mirrored back to the transmitter chip, hiding the redriver chip. An input signal detector detects when the transmitter chip begins signaling and enables an equalizer, limiter, pre-driver, and output stage to re-drive the signals to the receiver chip. The input signal detector also causes the switched output termination to switch to the low value termination for signaling.

Abstract: A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.

Abstract: A pulse restoration circuit includes: a voltage restorator configured to include an OP amplifier and input an input voltage to an input terminal of the OP amplifier; a rising time restorator configured to be connected to the other input terminal of the OP amplifier; and a falling time restorator configured to be connected to an output terminal of the OP amplifier, whereby it is possible to improve a reduction in performance of the medical image electronics transmitting an analog signal via the cable and a PET detector of a PET-MRI convergence system among the medical image electronics by correcting a distortion phenomenon of an output signal depending on a cable length into the original signal using the pulse restoration circuit.

Abstract: An embodiment of the invention includes a receiver with reduced error terms and incoming jitter tracking that improves jitter tolerance. An embodiment provides these benefits based on a voltage integrator that recovers data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. An embodiment provides these benefits based on a time integrator that recovers, using digital logic, data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. Other embodiments are described herein.

Abstract: A communication device includes: a converting part converting a data signal from a non-return-to-zero signal to a return-to-zero signal; a trigger flip-flop inverting an output signal every time the return-to-zero signal changes in one cycle; a first filter outputting a positive pulse and a negative pulse alternately, which indicate existence and absence of the pulse corresponding to a value of the data signal, by removing a low frequency component of an output signal of the trigger flip-flop.

Abstract: A signal transmission/reception system includes a transmission line, a signal transmission circuit configured to generate a transfer signal and transfer the transfer signal through the transmission line, wherein a logic value of the transfer signal is changed whenever a pulse signal is input to the signal transmission circuit, and a signal reception circuit configured to receive the transfer signal through the transmission line and generate a restoration signal using the transfer signal and a delayed transfer signal obtained by delaying the transfer signal.

Abstract: A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include a digital control circuit configured to control the clock and data recovery circuit. The digital control circuit and the clock and data recovery circuit may be formed on a single substrate.

Abstract: In one example embodiment, a programmable capacitor array is provided for low distortion and minimizing linearity degradation of an input (Vin) by utilizing control circuitry to switch on and off an array of MOSFET switches. The control circuitry turns on a MOSFET to load a capacitance on Vin and turns off the MOSFET to remove the capacitance from Vin in response to a Din control signal. When the intention is to load Vin with the capacitance, the MOSFET is left on continuously. When the intention is to remove or unload the capacitance from Vin, the MOSFET is primarily turned off, however, the MOSFET is still periodically turned on with appropriate voltage levels in response to a clock signal for periods of time when the loading of the capacitance on Vin is tolerable to the system, thereby ensuring minimal linearity degradation of Vin due to the programmable capacitor array system.

Abstract: The present specification provides a method, apparatus and system for sensing a signal with automatic adjustments for changing signal levels. A novel fractional peak discriminator circuit is provided which can be incorporated into a system for measuring periodic signals from moving elements. The circuit can be used regardless of whether the periodic signals are detected using optics, magnetic detector or other methods.

Abstract: An apparatus comprising an RF circuit, a converter circuit, an amplifier, and a delay circuit. The RF circuit may be configured to generate (i) an output signal and (ii) a first intermediate signal, in response to (i) an input signal and (ii) a control signal. The converter circuit may be configured to generate a second intermediate signal in response to the first intermediate signal. The amplifier may be configured to generate a third intermediate signal in response to the second intermediate signal. The delay circuit may be configured to generate the control signal in response to the third intermediate signal. The RF circuit may generate the output signal having a flattened response by providing pulse shaping in response to the control signal.

Abstract: Clock signal timing cells, clock signal timing circuits, clock circuits, memory devices, systems, and method for altering the timing of a clock signal are disclosed. An example method for altering the timing of an output signal provided responsive to an input clock signal includes adjusting a transition of an edge of the output signal from one voltage level to another based at least in part on a bias signal. An example clock signal timing cell includes an inverter and a bias controlled inverter coupled in parallel to the inverter. The bias controlled circuit is configured to provide an output signal wherein a transition of a clock edge of the output signal between first and second voltage levels is based at least in part on a bias signal.

Abstract: Apparatuses and methods are disclosed, including an apparatus that includes a differential driver with charge injection pre-emphasis. One such apparatus includes a pre-emphasis circuit and an output stage circuit. The pre-emphasis circuit is configured to receive differential serial signals, and buffer the differential serial signals to provide buffered differential serial signals. The output stage circuit is configured to receive the buffered differential serial signals and drive the buffered differential serial signals onto differential communication paths. The pre-emphasis circuit is configured to selectively inject charge onto the differential communication paths to assist with a signal transition on at least one of the differential communication paths. Additional embodiments are disclosed.

Abstract: A system can include a phase detector configured to generate a phase error signal indicating a phase error of an input signal compared to an output signal and a first filter coupled to the phase detector and configured to generate a first control signal derived from the phase error signal. The system can include a pattern error detector configured to generate a pattern error signal specifying a pattern error of the input signal compared to the output signal and a second filter coupled to the pattern error detector and configured to generate a second control signal derived from the pattern error signal. The system further can include a controlled oscillator coupled to the first filter and the second filter, wherein the controlled oscillator is configured to generate the output signal responsive to the first control signal, the second control signal, and a center frequency signal.

Abstract: The described embodiments provide a configurable clock circuit. The clock circuit includes a control and enable circuit and a clock distribution circuit. During operation, when a signal on an enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a clock mode, the control and enable circuit generates an enable signal on a control output to enable a signal on a clock input to propagate through the clock distribution circuit to the clock output. Alternatively, when a signal on the enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a pulse mode, the control and enable circuit generates a pulsed control signal on the control output to control a length of a pulse generated from the clock input on a clock output by the clock distribution circuit.

Abstract: A system for generating a gated clock signal includes an AND gate and a clock gating cell. The AND gate receives a reset signal and an input clock signal and generates a clock signal that is provided to a clock input terminal of the clock gating cell. The clock gating cell generates a gated clock signal based on an input signal and the clock signal. Gating the clock input to a latch allows a means for conserving power.