Abstract: An apparatus and method for measuring the duty cycle of a clock signal, the apparatus having a first multi-tap delay module, a second multi-tap delay module, and a multi-element detecting module, the input terminal of the first multi-tap delay module and the input terminal of the second multi-tap delay module coupled to an input node IN, the first multi-tap delay module receiving the clock signal and then providing it a first constant incremental delay at each tap, the second multi-tap delay module receiving the same clock signal CLK and then providing it a second constant incremental delay at each tap, and the multi-element detecting module determining the ratio of the number of outputs of the multi-element detecting module in which the sampled clock level is high with respect to the total number of steps covering one complete clock cycle.

Abstract: The joint (36) comprises a tubular body (37) having two connecting zones (38, 39) each connected by an end to a tubular element (40) of a fluid transport line, giving continuity to passage of fluid. The tubular body is made of a mixture of an electrically-conductive material such as PVC, with carbon black to give it electrical conductivity. The joint has an internal surface (41) which is destined to come into contact with the transported fluid, and an external surface which is destined to have a grounded galvanic contact. The joint is inserted in the discharge fluid drainage line of a dialyzer filter, in an apparatus for intensive treatment of acute renal insufficiency, for eliminating ECG artefacts due to functioning of peristaltic pumps in the apparatus.

Abstract: A circuit for receiving an input signal having a first frequency and generating an output signal having a second frequency. The circuit comprises a forward branch for receiving the input signal and generating the output signal and a return branch for generating a feedback signal from the output signal. The forward branch comprises a frequency detector for receiving the input signal and the feedback signal and outputting a value based on a ratio of a frequency of the feedback signal to the first frequency; a word length reduction block for receiving a fractional component of a first division factor and generating a modulated output; an adder for forming a sum of an integer component of the first division factor and the modulated output of the word length reduction block; a subtracting element for subtracting the output value of the frequency detector from the sum; and an oscillator controlled by an output from the subtracting element.

Abstract: A system for quantizing an analog signal comprises an input terminal for receiving an input signal, an inverted input terminal for receiving an inverted input signal, a clock terminal for receiving a clock signal, and an inverted clock terminal for receiving an inverted clock signal. A first negative-resistance device has a first terminal coupled to the clock terminal and a second terminal coupled to the clock terminal coupled to the input terminal. A second negative-resistance device has a third terminal coupled to the clock terminal and a fourth terminal coupled to the inverted input terminal. A third negative-resistance device has a fifth terminal coupled to the input terminal and a sixth terminal coupled to the inverted clock terminal. A fourth negative-resistance device has a seventh terminal coupled to the inverted input terminal and an eighth terminal coupled to the inverted clock terminal. An output terminal for producing an output signal is connected to the input terminal.

Abstract: A phase-locking system is provided that includes a bridge, a light source and an optical pulse injector. The bridge includes a plurality of negative differential resistance devices for storing an input signal. The light source is capable of producing an optical pulse. The optical pulse injector receives the optical pulse and transmits an optical signal to trigger the bridge in response to receiving the optical pulse.

Abstract: A high frequency clock signal generator (10) is disclosed. The clock signal generator includes a power supply (12, 14), a first resonant tunneling diode (18) coupled to a first terminal of the power supply and an output node (22), and a second resonant tunneling diode (20) coupled to the output node (22) and a second terminal of the power supply. A signal source is coupled to the output node (22) and periodically switches the first and second resonant tunneling diodes (18, 20) between a first state and a second state. The signal source comprises an oscillating signal generator (26) and a transmission line (28) coupled to the output node (22) of the clock signal generator. The oscillating signal generator (26) produces an oscillating input signal, which is reflected by the transmission line (28). The resonant tunneling diode configuration provides rapid voltage swings at the output, thus allowing the generation of a high frequency clock signal of 25 GHz or more.

Abstract: A method and structure for wave-shaping of digital waveforms of integrated circuit processes that do not have area efficient dielectric capacitors is disclosed. The dielectric capacitors of the prior art are replaced with a first, linearizing diode and a second diode of a wave-shaping circuit, each diode having a junction capacitance that varies with voltage applied across the diode. The first, linearizing diode is supplied with a constant current from a constant current source. A current inversely proportional to the junction capacitance of the first, linearizing diode is produced at a node defined as the connection between the constant current source and the first linearizing diode. The current at the node is supplied to the second diode to produce an output voltage of the wave-shaping circuit that is linear with respect to time.