Abstract: A switch controller is provided that uses one or more capacitors to generate a slow turn on/slow turn off switch control signals to suppress audible switching noise in an audio switch. In some embodiments, an analog inverter and a capacitor are used to generate the switch control signals, while in other embodiments two capacitors are used to generate the switch control signals. To conserve power between switching states, routing logic is provided that ties the switch control signals to respective voltage rails and disables selected portions of the switch controller.

Abstract: The present invention relates to a quadrature divider which may be used in a phase locked loop or frequency synthesizer or with a single side band mixer. According to a preferred embodiment the divider takes a quadrature input and has a quadrature output. The divider has four analog mixers 1, 2, 3 and 4. The first two mixers 1, 2 take the in-phase quadrature input, while the second mixers 3, 4 take the quadrature-phase quadrature input. The outputs and feedback loops of the mixers are properly arranged such that the in-phase and quadrature-phase outputs of the divider have a determinisitic phase sequence relationship based on the phase sequence relationship of the corresponding quadrature inputs. Third order harmonics may be minimized or reduced by addition or subtraction of the mixer outputs. As the divider is able to take a quadrature input, there is no need for a dummy divider in the phase locked loop, thus saving space and power.

Abstract: A method for calculating coordinate values of a measuring machine is provided. The method includes receiving signals in three dimensions from a raster ruler signal generator, identifying a direction of each signal and multiply a frequency of each signal. The method further includes counting each of multiplied signals in each dimension, sending the counted data to the MCU. The method further includes adding the counted data of each of the multiplied signals in each dimension to obtain an accumulated number in each dimension and calculating coordinate values of the measuring machine according to the accumulated number in each dimension and a proportionality factor of the raster ruler signal generator.

Abstract: A method for determining a time interval between leading edges of two adjacent cyclic input pulses of a series of cyclic input pulses. A sample of the cyclic input pulses is taken at each of a series of sampling times to produce sampling hits, each sampling hit being an indication of a presence of a cyclic input pulse, recording a count number at each of the sampling hits, determining initial sampling hits from the detected sampling hits, determining a minimum sampling interval between initial sampling hits, and determining a count number located at a back end of the minimum sampling interval, count numbers of the minimum sampling interval being used to determine a time interval between lead edges of two adjacent cyclic input pulses.

Abstract: A phase detector is adapted to receive first and second signals and generate third and fourth signals representative of the difference between the phases of the first and second signals. The phase detector assert the third signal in response to the assertion of the first signal and unasserts the third signal in response to the assertion of the second signal. The phase detector asserts the fourth signal in response to the assertion of the third signal and unasserts the fourth signal in response to unassertion of the first signal. The phase detector may include combinatorial logic gates, thereby to generate the third and fourth signals in response to logic levels of the first and second signals. The phase detector may include sequential logic gates, thereby to generate the third and fourth signals in response to transitions of the first and second signals.

Abstract: Bidirectional power conversion systems provide the ability to change power attributes to and from a component. Current bidirectional power conversion systems use a unidirectional power converter for each direction. The integration of the two normally independent power converters results in a bidirectional power converter with nearly half the size, weight, volume, cost and complexity. Described are embodiments of bidirectional power conversion systems that allow power transfer between two or more components without requiring the use of separate unidirectional power converters.

Abstract: A phase difference detector adapted to generating a signal indicative of a phase difference between a first signal and a second signal, comprising: a first bistable element clocked by the first signal and having a first output signal, and a second bistable element clocked by the second signal and having a second output signal; means for determining the variation of the signal indicative of the phase difference, responsive to the first and second output signals, and a reset circuit having a first and a second inputs respectively connected to the first and second output signals and adapted to determine the resetting of the first and second bistable elements in response to the attainment of a respective prescribed state by the first and the second output signals. The first and second inputs of the reset circuit are substantially symmetrical to each other from the point of view of an input impedance associated to each of them.

Abstract: A phase detector customized for Clock Synthesis Unit (CSU) is disclosed. The phase detector improves jitter performance by providing minimal activity on VCO control lines and pushing ripple frequency to one octave higher, while maintaining wide linear characteristic. Moreover, it provides a frequency-scalable circuit that unlike a conventional phase-and-frequency detector (PFD), does not rely on asynchronous elements.

Abstract: A frequency synthesizer for dual-band high frequency RF application. The frequency synthesizer first uses a frequency-locked loop circuit (“FLL”) to achieve self-calibration and frequency-locking, and then uses a phase-locked loop circuit (“PLL”) to achieve phase-locking. During the FLL, the PLL is de-activated by control signals from the digital control and state machine of the FLL. The varactor of the VCO is initially connected to a fixed voltage, thus isolating the varactor from the PLL. The FLL adjusts the VCO's capacitor array by varying the five binary control bits from the state machine and digital control, until frequency-locking and self-calibration is achieved. Then, those five binary weighting control bits are also fixed for the VCO. The PLL is then activated to perform a fine-tuning and phase-locking loop, where the varactor of the VCO is controlled by the signal from the charge pump and the low-pass filter.

Abstract: A time discrete PLL-tuning system comprises a phase detector and a voltage controlled oscillator (VCO) for tuning the frequency (fVCO) thereof to a frequency equal to N/M times a reference frequency (fREF), with M a factor indicating the number of frequency steps in which a transmitter/receiver channel distance is divided and N the number of frequency steps in which the oscillator frequency is divided. The sampling frequency of the phase detector is substantial equal to the reference frequency (fREF).

Abstract: A method and apparatus for detecting a sinusoidal signal samples a received signal. An error signal generator receives at its inputs a previous sample of the received signal and a current sample of the received signal and generates an error signal based on these previous and current samples. A comparison circuit compares the generated error signal for the current sample to an error threshold value and generates a threshold comparison signal with a first value that indicates the generated error signal is below the error threshold value for a second value that indicates a generated error signal is above the error threshold value. A determination circuit then determines whether the received signal is a sinusoidal signal based on a threshold comparison signal generated for a plurality of samples. The determination circuit includes a counter that maintains a count of the number of threshold comparison signals having the first value within a sampling period.

Abstract: Spurious energy suppression for a data communication system is achieved without using a large order noise suppression filter, by means of a post-mixer tracking filter that contains a current-controlled MOSFET-implemented resistance for a transconductance-capacitance filter and an associated transconductance tuning stage. The MOSFET-implemented resistance is controlled by the same control current that establishes the output frequency. As a result, the cut-off frequency of the tracking filter is linearly proportional to the carrier and independent of absolute processing parameters and temperature.

Abstract: In a circuit (10), a first N-FET (N1) and a second N-FET (N2) are coupled serially between a node (15) and ground (93). The circuit (10) accommodates a first excursion (85) of a first signal (IN) at the gates of the first N-FET (N1) which is higher than the maximum allowable drain-source voltage for N-FETs. The voltage of a second signal (OUT) between the node (15) and ground (93) is distributed across the first and the second N-FETs (N1, N2). The gate voltage of the second N-FET (N2) is not constant, but controlled by a control circuit (20) receiving signals the first signal (IN) and, optionally, the second signal (OUT). With the variation of the gate voltage for the second N-FET (N2), the size of both transistors (N1, N2) can be reduced and the fall time (T.sub.F) of the second signal (OUT) can be reduced.

Abstract: A noise cancellation system which balances the photocurrents derived by a measurement signal and a reference signal of a sensor. The invention has application in any measurement device which detects a small signal in combination with high noise content and further utilizes a reference signal.

Abstract: A high speed ratio CMOS logic structure includes a static PMOS pullup transistor connected to an output node, and a plurality of NMOS pulldown transistors, connected in parallel, to the output node and which collectively define a pulldown circuit. The pullup transistor is biased using a reference voltage to define a static pullup strength for the logic structure. The pulldown strength of the pulldown circuit is also fixed. The combination of the pullup transistor, and the pulldown transistors define an N input NOR gate. The logic structure, however, further includes a feedback logic circuit, formed by a pair of inverters connected in series coupled to the output node to sense a current logic state of the output node. The feedback logic circuit generates an enable signal that is provided to a second, dynamic PMOS transistor connected in parallel with the static pullup PMOS transistor.