Abstract: An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.

Abstract: An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.

Abstract: A channel correction method, used for performing channel correction on radio frequency apparatuses in a network area, is provided. The radio frequency apparatuses are divided into at least one radio frequency apparatus group. A correction resource location is set for each radio frequency apparatus in the radio frequency apparatus group. These resource locations may be stored in a form of configuration information in base stations where the radio frequency apparatuses are located, so that the base station controls each of these radio frequency apparatuses to send a correction signal in a respective correction resource location based on the configuration information, and to implement, by using these correction signals, channel correction for the radio frequency apparatuses in the radio frequency apparatus group. The method can implement joint channel correction for a plurality of radio frequency apparatuses and improve correction efficiency.

Abstract: An ADC that includes a processing unit configured to receive from first sampling latches N first PWM pulse start counter values and N first PWM pulse end counter value, receive from second sampling latches, N second PWM pulse start counter values and N second PWM pulse end counter value; (c) select a counter that is coupled to a selected sampling latch; (d) calculate an estimated difference between first and second input analog signals based on at least readings of the selected latch. The readings of the selected counter include a first PWM pulse start counter value latched by the selected latch, a first PWM pulse end counter value latched by the selected latch, a second PWM pulse start counter value latched by the selected latch, and a second PWM pulse end counter value latched by the selected latch; and (e) output a digital output signal indicative of the estimated difference.

Abstract: A DC-DC converter includes a first half-bridge circuit, a second half-bridge circuit, at least one transformer having at least one primary winding and at least one secondary winding, wherein the first and second half-bridge circuits are designed to generate an AC voltage at the at least one primary winding, and a rectifier circuit having an output terminal. The output terminal includes a first output terminal pole and a second output terminal pole. The rectifier circuit includes at least one rectifier element. The rectifier circuit is designed to rectify a voltage present at the at least one secondary winding and to output it at the output terminal. The rectifier circuit includes a polarity reversal protection transistor, the collector-emitter path of which or the drain-source path of which is looped in between a terminal of the at least one rectifier element and the first or the second output terminal pole of the output terminal.

Abstract: The apparatus is a wake-up circuit including a first comparator coupled to an input signal and configured to compare the input signal to a first comparison value. The wake-up circuit includes a second comparator coupled to the input signal and configured to compare the input signal to a second comparison value. The wake-up circuit further includes an exclusive OR gate. A first input of the exclusive OR gate is coupled to an output of the first comparator. A second input of the exclusive OR gate is coupled to an output of the second comparator. The wake-up circuit also includes a tunable charge pump coupled to an output of the exclusive OR gate and configured to convert a signal from the exclusive OR gate to a DC value to wake up a circuit being monitored.

Abstract: A circuit for generating an output signal having a second pulse duty factor from an input signal having a first pulse duty factor includes a first capacitor and a second capacitor which are each connected to a charge source for periodically charging the capacitors. A voltage across the charged first capacitor is defined as a reference voltage, and the pulse duty factor of the output signal is defined by the charging period of the second capacitor required for reaching the reference voltage.

Abstract: A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.

Abstract: A circuit for use with PWM signal having first pulse and a second pulse, wherein the first pulse has a period and a first duty cycle, and the second pulse has the period and a second duty cycle. The period has clock information therein, the first duty cycle has first data information therein, and the second duty cycle has second data information therein. The circuit includes a first integrating component and a second integrating component. The first integrating component can generate a first voltage corresponding to the first duty cycle and a second voltage corresponding to the first duty cycle. The second integrating component can generate a third voltage corresponding to the second duty cycle and a fourth voltage corresponding to the second duty cycle.

Abstract: One embodiment includes a power regulator system. The system includes a switch control stage configured to generate at least one activation signal based on a pulse-width modulation (PWM) signal and to control a respective at least one switch to generate an output voltage. The system also includes a feedback stage configured to generate the PWM signal based on a ramp signal and a feedback voltage that is based on the output voltage. The system further includes a ramp generator stage configured to adaptively generate the ramp signal based on the output voltage and based on the at least one activation signal.

Abstract: The address transition detecting circuit includes two identical address transition detecting signal generating module, an inverter and a signal combining module. Both of the two address transition detecting signal generating modules have a unilateral delay circuit for generating an output pulse at the rising edge of the address signal and an output pulse at the falling edge of the address signal. The address transition detecting signal generating module can control the width of the two output pulses by controlling the delay times of the corresponding unilateral delay circuit. The signal combining module outputs the ATD signal having pulses at both the rising edge and falling edge of the address signal. The present application uses two unilateral delay circuits to control the width of the ATD signal at the rising edge and the falling edge of the address signal, thereby significantly preventing the width of the ATD signal from influence of the burr on the address line.

Abstract: A pulse stretching circuit having a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal, and a pulse adjustment circuit, connected to the pulse delay circuit, receiving the input pulse signal and the delay pulse signal and for outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal. The pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, keeps a state in which the output pulse signal is displaced with the leading edge thus caused longer than a total time of times for both pulse widths of the input pulse signal and the delay pulse signal, and causes a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal.

Abstract: A system for decreasing output power required to produce an output signal based on persistence of perception characteristics. The system includes a circuit configured to receive a perception signal at an input. The circuit is also configured to output a portion of the input perception signal when the circuit is receiving power output a zero amplitude signal when the circuit is not receiving power. The system also includes a switch configured to provide power to the circuit for a first interval of time and cut power to the circuit for a second interval of time contiguous to the first interval of time.

Abstract: A sensor device includes a detector portion, plural metal terminals that transmit a detection signal from the detector portion, and a housing portion, which integrally supports the detector portion and metal terminals, formed from resin, leading end portions of the plural metal terminals configuring connector terminals, and the plural metal terminals being disposed with at least one portion thereof aligned when seen from the axial direction of the connector terminals, wherein protruding portions protruding in a direction differing from the axial direction of the connector terminals are provided on the metal terminals.

Abstract: The present invention relates to a pulse signal generation circuit for changing a pulse width of an input pulse signal and outputting an output pulse signal having the changed pulse width. In an aspect, the pulse signal generation circuit may include a control signal generator configured to generate at least one control signal according to a pulse width of a input pulse signal and a pulse signal generator configured to control a pulse width of an input pulse signal in response to a control signal and to generate an output pulse signal with the controlled pulse width. The control signal controls the pulse width of the output pulse signal.

Abstract: A strobe signal generation device includes an enable signal generating section, a buffering section and a strobe signal driving section. The enable signal generation section generates a division enable signal in response a strobe signal. The buffering section configured to generate a delayed strobe signal from the strobe signal while the division enable signal is enabled. The strobe signal driving section configured to generate a plurality of data strobe signals with a larger pulse width than the delayed strobe signal, in response to the division enable signal and the delayed strobe signal.

Abstract: A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.

Abstract: A receiver for decoding a communication signal is disclosed. The receiver includes an input port and a filter. The input port receives the communication signal from a communication medium. The communication signal comprises a sequence of symbols. Each symbol of the symbol sequence is an analog pulse that has a leading edge of exponential shape. The exponential shape has an exponential growth parameter value that has been selected from values ?0 and ?1, which are distinct positive values. For each symbol of the symbol sequence, the exponential growth parameter value for the leading edge of the symbol has been selected based on a corresponding bit from a stream of information bits. The filter receives the communication signal from the input port and filters the communication signal to obtain an output signal. The transfer function of the filter has one or more zeros at ?0.

Abstract: Circuits and methods for detecting the presence of a leading-edge phase-cut dimmer. The dimmer detector comprises an edge detector, a pulse stretcher and a filter. The edge detector detects whether an input signal has a rapidly rising edge and generates an output signal pulse if a rapidly rising edge is detected. If the edge detector outputs a signal pulse, the pulse stretcher generates a stretched pulse having a duration that is longer than the signal pulse received from the edge detector. The filter produces a dimmer detect signal that indicates whether a leading-edge phase-cut dimmer is detected. If the pulse stretcher output signal comprises at least a predetermined number of stretched pulses within a predetermined amount of time, the dimmer signal signals the presence of a leading-edge phase-cut dimmer.

Abstract: The pulse width adjusting circuit includes a pulse delaying circuit for inputting an inputted pulse signal a and for outputting a plurality of different delayed pulse signals b1, b2, . . . , a transmission gate for inputting an inputted pulse signal a and controlling the passage of the inputted pulse signal a in response to the application of two delayed pulse signals from among the plurality of different delayed pulse signals b1, b2, . . . , and a pulse width setting circuit connected to the transmission gate for setting the pulse width of an outputted pulse signal c generated on the basis of the inputted pulse signal a passing through the transmission gate.

Abstract: A method adjusts a pulse width of a signal. The method provides a fixed voltage input trigger pulse (34), of a certain pulse width, to a pulse width generator circuit (10) and provides an output pulse (52) from the pulse width generator circuit such that a pulse width of the output pulse is longer than the certain pulse width, without changing a voltage or frequency of the input trigger pulse. The method is used to drive an injector of a diesel reductant delivery system to inject fluid into an exhaust flow path.

Abstract: A method and apparatus for controlling the frequency of a clock signal using a clock-gating circuit is disclosed. In one embodiment, a root clock signal and an enable signal are provided to a clock-gating circuit. The clock-gating circuit is configured to provide an operational clock signal (based on the root clock signal) when the enable signal is asserted. The operational clock signal is inhibited when the enable signal is de-asserted. The frequency of the operational clock signal can be output at a reduced frequency (relative to the root clock signal) by asserting the enable signal for one of every N clock cycles. Furthermore, the frequency of the operational clock signal can be dynamically changed by changing the rate of asserting the enable signal relative to the root clock signal, without suspending operation of a functional unit receiving the operational clock signal.

Abstract: A pulse generator is provided. The pulse generator includes: a time delayed pulse generation unit including a plurality of delay cells for receiving a first pulse having a first pulse width and outputting pulses delayed by a particular time delay value on the basis of one of a rising edge and a falling edge of the first pulse; an edge combiner configured to receive the plurality of time delayed pulses from the time delayed pulse generation unit and generate second pulses having a second pulse width; and a channel selector configured to regulate the number of outputs of the second pulses generated by the edge combiner.

Abstract: A pulse width modulation circuit of the present invention changes a voltage of a charging circuit based on an input signal voltage and in synchronization with a first switching signal; changes, during a predetermined second period following a first period during which the voltage of the charging unit is changed, the voltage of the charging unit in an opposite direction to a direction in which the voltage is changed during the first period, based on a constant bias current; detects time starting from when the second period starts to when the voltage of the charging unit reaches a predetermined reference voltage; and generates, based on the detected time which is repeatedly output each time the first switching signal is output, a pulse signal having a pulse width of the time.

Abstract: An activate signal generating circuit, to which a first and a second activate signals which are pulse signals are applied, and which generates an internal activate signal, has a first delay element. The internal activate signal is activated based on timings of front (active transient) edges of the first and second activate signals. When a timing of a rear (inactive transient) edge of the first activate signal is earlier than a timing of a rear edge of the second activate signal, the internal activate signal goes inactivate based on the timing of the rear edge of the first activate signal, and when the timing of the rear edge of the first activate signal is later than the timing of the rear edge of the second activate signal, the internal activate signal goes inactivate after a predetermined delay time based on a delay time of the first delay element.

Abstract: A pulse stretching circuit having a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal, and a pulse adjustment circuit, connected to the pulse delay circuit, receiving the input pulse signal and the delay pulse signal and for outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal. The pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, keeps a state in which the output pulse signal is displaced with the leading edge thus caused longer than a total time of times for both pulse widths of the input pulse signal and the delay pulse signal, and causes a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal.

Abstract: A pulse signal generation circuit includes a transfer path configured to receives and transfer a first pulse signal, a pulse adjustment unit configured to adjust a pulse width of the first pulse signal by applying charges to the transfer path in response to a control signal, and a pulse output unit configured to output a second pulse signal of the adjusted pulse width in response to an output of the transfer path.

Abstract: A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generating control signals for controlling operation of the first and second transistors. The control signals are generated responsive to the values in certain triggered counting circuits satisfying programmable thresholds.

Abstract: Systems, methods, and apparatus for improving steady state operation of a pulse width modulator during transient and soft start events are described herein. An apparatus can include a phase component configured to adaptively modify a pulse width of a first pulse width modulated (PWM) output signal based on a pulse width of a PWM input signal. Further, the apparatus can include a power stage component configured to source at least one of a voltage or a current to a load based on the first PWM output signal. In one example, the phase component can be configured to linearly extend the pulse width of the first PWM output signal based on the pulse width of the PWM input signal. In another example, the phase component can be configured to adaptively modify the pulse width of the first PWM output signal based on a predetermined maximum pulse width.

Abstract: A signal delay circuit including a clock transfer control circuit configured to transmit or block a clock signal, and a pulse signal generation circuit configured to delay a first pulse signal in response to the transmitted clock signal to generate a second pulse signal which has a longer active period than the first pulse signal.

Abstract: The invention relates to a duty cycle corrector for generating from an input clock signal an output clock signal having a desired duty cycle. The duty cycle corrector comprises a pulse generating stage for generating from the input clock signal a pulsed clock signal. The pulse generating stage converts rising edges of the input clock signal into pulses, each of which pulses is shorter than the desired duty cycle times the clock period. The duty cycle corrector further comprises a pulse stretching stage for generating from the pulsed clock signal the output clock signal, the pulse stretching stage delaying falling edges of the pulsed clock signal by a controlled delay.

Abstract: A duty cycle correcting circuit includes a first duty ratio correcting unit that widens a high-level period of an input clock in response to a detection signal, thereby correcting a duty ratio of the input clock to output a first corrected clock. A second duty ratio correcting unit narrows the high-level period of the input clock in response to the detection signal, thereby correcting the duty ratio of the input clock to output a second corrected clock. A clock selecting unit selectively outputs the first corrected clock or the second corrected clock as an output clock in response to the detection signal. A duty ratio detecting unit detects a duty ratio of the output clock, thereby generating the detection signal.

Abstract: A switching power supply system has a control circuit that controls an output voltage by causing a switching device to turn ON and OFF. The control circuit includes a control pulse supplying unit that supplies a pulsed signal that keeps the switching device turned-ON and -OFF. A protection circuit shuts down the switching power supply system upon occurrence of an abnormality. A delay circuit produces a delay signal that delays by a specified time duration the termination of a state of the pulsed signal in which the pulsed signal keeps the switching device turned-ON. The protection circuit is responsive to the pulsed signal or the delay signal to switch between an operation state and a stand-by state.

Abstract: The invention relates to a pulse width modulator, more particularly to a cross-coupled pulse width modulator. A crossing input signal modulator according to the present invention comprises: a positive path block which includes a first integrator for performing the first-order integration of feedback signals in first input and output signals and then transmitting the first-order integrated signals to a second integrator, and a second integrator for performing the second-order integration of a signal from the first integrator and a second input signal and then transmitting the second-order integrated signals; and a negative path block which includes a third integrator for performing the first-order integration of feedback signals in the second input and output signals and integration of a signal from the third integrator and the first input signal and then transmitting the second-order integrated signals.

Abstract: A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generating control signals for controlling operation of the first and second transistors. The control signals are generated responsive to the values in certain triggered counting circuits satisfying programmable thresholds.

Abstract: An input circuit comprises a buffer enable signal generating circuit for generating a buffer enable signal having an predetermined enable period in response to an external command, and a buffer circuit for buffering and outputting the external command and an external address signal in response to the buffer enable signal.

Abstract: Systems, methods, and apparatus for improving steady state operation of a pulse width modulator during transient and soft start events are described herein. An apparatus can include a phase component configured to adaptively modify a pulse width of a first pulse width modulated (PWM) output signal based on a pulse width of a PWM input signal. Further, the apparatus can include a power stage component configured to source at least one of a voltage or a current to a load based on the first PWM output signal. In one example, the phase component can be configured to linearly extend the pulse width of the first PWM output signal based on the pulse width of the PWM input signal. In another example, the phase component can be configured to adaptively modify the pulse width of the first PWM output signal based on a predetermined maximum pulse width.

Abstract: A digital signal converter (CNV) converts a digital input signal (PCM) into a pulse width modulated signal (PWM), which is a binary signal that comprises pulses of varying width. The digital signal converter can operate in a signal mode and a transition mode. In the transition mode, the digital converter provides the pulse width modulated signal (PWM) by applying an anti-transient noise shaping function (NSH2) to a direct current modification signal (SC). In the signal mode, the digital signal converter provides the pulse width modulated signal by applying a signal noise shaping function (NSH1) to the digital input signal.

Abstract: A design structure for a circuit for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device is provided. The circuit has a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.

Abstract: A mechanism is provided for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device. The mechanism employs a circuit having a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.

Abstract: A signal delay circuit including a clock transfer control circuit configured to transmit or block a clock signal, and a pulse signal generation circuit configured to delay a first pulse signal in response to the transmitted clock signal to generate a second pulse signal which has a longer active period than the first pulse signal.

Abstract: A clock generating circuit includes a source clock, a first clock generated from the source clock through a first header, a second clock generated from the source clock through a second header and an inverter, wherein the second clock is out of phase with respect to the first clock, a first delayed falling edge clock, wherein the first delayed falling edge clock corresponds to the first clock with a first delayed falling edge, and a second delayed falling edge clock, wherein the second delayed falling edge clock corresponds to the second clock with a second delayed falling edge. The first delayed falling edge clock is generated from a first leading edge path and a first falling edge path, both originating from the source clock, that are inputted to a first delay chain.

Abstract: A pulse width modulation (PWM) device, system and method for high resolution fan control are disclosed. In one embodiment, the method comprises determining a target duty cycle of a PWM signal, determining the number of PWM cycles in the period of the PWM signal, pseudo-randomly selecting a duty cycle for each PWM cycle using one or more look-up tables and generating the PWM signal based on the duty cycle.

Abstract: A duty cycle correcting circuit includes a first duty ratio correcting unit that widens a high-level period of an input clock in response to a detection signal, thereby correcting a duty ratio of the input clock to output a first corrected clock. A second duty ratio correcting unit narrows the high-level period of the input clock in response to the detection signal, thereby correcting the duty ratio of the input clock to output a second corrected clock. A clock selecting unit selectively outputs the first corrected clock or the second corrected clock as an output clock in response to the detection signal. A duty ratio detecting unit detects a duty ratio of the output clock, thereby generating the detection signal.

Abstract: A duty cycle correction circuit comprises a frequency divider, a duty cycle detector and a delay circuit. The frequency divider receives a first clock signal and divides the frequency of the first clock signal to generate a second clock signal. The duty cycle detector receives the second clock signal and a correction clock signal and generates a control signal according to the second clock signal and the correction clock signal. The delay circuit receives the first clock signal and the control signal and adjusts a delay time of a falling edge of the first clock signal according to the control signal to generate the correction clock.

Abstract: A frame pulse signal latch circuit has: a pulse-width expanding unit which outputs a frame pulse signal FPIN having a pulse width longer than a m-clock cycle; a phase adjustment unit which generates a phase-adjusted output clock CLK?; a flip-flop which latches the frame pulse signal FPIN; a racing detection unit which generates signals, which are shifted by one to m clocks with respect to a frame pulse signal FPOUT, and detects a racing state based on a result of an AND operation of the frame pulse signal FPOUT and the clock-shifted signals; and a control unit which sequentially selects and directs different phase adjustment amounts to the phase adjustment unit, determines an optimal phase adjustment amount based on a worst phase adjustment amount of the case in which the racing state is detected, and gives a direction about the optimal phase adjustment amount to the phase adjustment unit.

Abstract: Disclosed is waveform width adjusting circuit that comprises: a delay circuit having a prescribed delay time is provided in a signal propagation path and a delay adjusting circuit which applies an adjustment in such a manner that when a waveform width extending from either a positive-going transition or a negative-going transition of the signal waveform at an input terminal to the next negative-going transition or positive-going transition is greater than the delay time of the delay circuit, a signal having a reduced waveform width is output, and such that when the waveform width of the signal at the input terminal is less than or equal to the delay time, the waveform width is not reduced and the signal that is output has the waveform width of the original signal. Thus, the waveform width of a signal for which the waveform width is less than a limit is not reduced.

Abstract: A pulse width modulator for use in a digital amplifier, includes a pop noise reducer for reducing pop noise by controlling a width and a phase of a pulse of a PWM signal output from the pulse width modulator, wherein the pop noise reducer contains: a PWM pulse register for storing a width and a phase values of a pulse of the PWM signal; and a pulse generator for outputting the PWM signal according to the values stored in the PWM pulse register. The pulse width modulator reduces pop noise generated when power supply to a digital amplifier is started and interrupted.

Abstract: A hybrid digital pulse width modulator can have a delay line with digitally programmable delay cells. The digitally programmable delay cells can be adjusted by a digital correction signal from a delay matching circuit.

Abstract: System and method for creating a time alignment analog notch. An embodiment includes a digital power amplifier coupled to an enable signal line and to a digital control bits bus, and a matching network coupled to the digital power amplifier. The matching network to provide impedance matching and the digital power amplifier to produce a current based on a value on the digital control bits bus. The digital power amplifier comprises a selection circuit and a plurality of transistors. The transistors, controlled by outputs of the selection circuit, provide a current based on the value on the digital control bits bus. The adjustment of a delay between a signal on the enable signal line and the values on the digital control bits bus creates an analog notch at about Fs/2, where Fs is a sampling frequency of a sigma-delta modulator used to modulate data provided to the digital power amplifier.