Rectangular (e.g., Clock, Etc.) Or Pulse Waveform Width Control Patents (Class 327/172)
  • Patent number: 11116055
    Abstract: A system may include a memory configured to store instructions and a processor. The processor may be configured to execute the instructions to cause the system to determine a PWM frequency of the input PWM signal and generate a first PWM signal to power a first light emitting diode (LED), a second PWM signal to power a second LED, and a third PWM signal to power a third LED. Each of the first PWM signal, the second PWM signal, and the third PWM signal may have the PWM frequency of the input PWM signal and may be in phase with the input PWM signal.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 7, 2021
    Assignee: Lumileds LLC
    Inventors: Yifeng Qiu, Alan Andrew McReynolds
  • Patent number: 11075579
    Abstract: A switching time generation circuit can include: a regulation circuit configured to generate a regulation signal in accordance with change information of an output signal of a switching converter; and the regulation circuit being configured to adjust a switching state of a power switch based on the regulation signal, where the switching converter includes a power stage circuit having the power switch.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: July 27, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Fusong Huang, Yonggang Fan
  • Patent number: 11061577
    Abstract: A system on chip includes a first clock generator that generates a first clock to be sent to a memory device, a second clock generator that generates a second clock to be sent to the memory device, a command and address generator that generate a code for adjusting a duty cycle of a third clock generated within the memory device based on the second clock and generates a command for storing the code to mode registers of the memory device, the third clock being used for a data input/output of the memory device, a data receiver that receives a data strobe signal and a data input/output signal output from the memory device receiving the command and the code synchronized with the first clock, and a training circuit that calculates a plurality of valid window margins for the code based on the data strobe signal and the data input/output signal.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yongseob Kim
  • Patent number: 11064295
    Abstract: Systems and methods for scrambling data-port audio in SOUNDWIRE™ systems include a scramble enable feature that allows a data source to scramble an outgoing channel content with a cyclic linear feedback shift register (LFSR) using a pseudo-random binary sequence (PRBS) such as, but not limited to, the PRBS defined in the SOUNDWIRE specification. Data ports for audio sinks receiving the scrambled content descramble the content for use by the audio sink. In a specific exemplary aspect, an output of the LFSR is added or subtracted with the audio data to make the microphones independent of one another and reduce crosstalk.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: July 13, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Lior Amarilio, Yiftach Benjamini, Sharon Graif
  • Patent number: 11038506
    Abstract: A drive assist circuit includes a pulse generation circuit which outputs a pulse to control an assist operation when an assist signal makes a first transition corresponding to a transition of a gate signal from a high level to a low level. The pulse generation circuit includes a delay circuit provided in one of two inputs of a logic gate. The delay circuit is configured such that a delay is greater when an input makes a transition corresponding to the first transition of the assist signal, as compared to a case where the input makes a transition corresponding to an inverse of the first transition.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: June 15, 2021
    Assignee: SOCIONEXT INC.
    Inventors: Toshiya Suzuki, Tomohiko Koto
  • Patent number: 11038492
    Abstract: In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: June 15, 2021
    Assignee: Apple Inc.
    Inventors: Steven F. Schicht, William R. Weier
  • Patent number: 11012058
    Abstract: A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: May 18, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sumit Dubey, Jasjot Singh Chadha
  • Patent number: 10990146
    Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Ramnarayanan Muthukaruppan, Pradipta Patra, Gaurav Goel, Uday Bhaskar Kadali
  • Patent number: 10992381
    Abstract: A method is provided for transmitting information and a device for carrying out the method, in which images are photographed by a camera with an image-taking rate, thus, especially frame rate, a controllable illuminant being disposed in the responsive range of the camera, where the control frequency (f_PWM) of the illuminant is less than the image-taking rate f1.
    Type: Grant
    Filed: September 1, 2014
    Date of Patent: April 27, 2021
    Assignee: SEW-EURODRIVE GMBH & CO. KG
    Inventors: Zhidong Hua, Christoph Steffen Keppler, Henning Schäfer, Andreas Wanjek
  • Patent number: 10921403
    Abstract: Power systems and circuitry for generation of gradient magnetic fields in magnetic resonance imaging (MRI) systems are discussed herein. Embodiments may include the use of multiple gradient amplifiers that share a high-frequency power distribution unit, that may perform power distribution and power supply roles. The high-frequency power distribution unit may allow the use of a single power supply to drive multiple gradient amplifiers via a shared power bus. The gradient amplifiers may make use of modern semiconductor materials that provide high-frequency, high voltage performance, and may be implemented using single semiconductor bridges.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: February 16, 2021
    Assignee: GE PRECISION HEALTHCARE LLC
    Inventors: Viswanathan Kanakasabai, Jayanti Ganesh, Juan Antonio Sabate
  • Patent number: 10884486
    Abstract: A pulse width compensation circuit may include a voltage control circuit and a pulse width adjustment circuit. The voltage control circuit may sense a voltage level of a first power supply voltage and generate a voltage control signal. The pulse width adjustment circuit may generate an output signal by changing a pulse width of an input signal based on the voltage control signal.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: January 5, 2021
    Assignee: SK hynix Inc.
    Inventors: Min Soo Park, Sung Soo Chi
  • Patent number: 10826412
    Abstract: A method for the activation of power semiconductors in an inverter using a microprocessor controlling a pulse width modulation (PWM). The method serves for improving the electromagnetic compatibility (EMC) and is in particular applicable in electric refrigerant compressors of motor vehicles.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: November 3, 2020
    Assignee: Hanon Systems
    Inventors: Stephan Werker, Gregor Sanzen, Mario Lenz
  • Patent number: 10819324
    Abstract: A semiconductor apparatus includes a first clock path which generates a first output clock signal by delaying a first phase clock signal, and a second clock path which generates a second output clock signal by delaying a second phase clock signal based on a delay compensation signal. The oscillating path generation circuit forms oscillating paths with the first clock path and the second clock path. The delay information generation circuit generates a delay compensation signal based on oscillating signals generated by forming the oscillating paths.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: October 27, 2020
    Assignee: SK hynix Inc.
    Inventor: Young Suk Seo
  • Patent number: 10791589
    Abstract: A sensor circuit and a method for compensating for temperature changes are provided. In accordance with an embodiment, sensor circuit includes at least one sensor for determining a measurement variable; a heating structure; and at least one compensation circuit. The compensation circuit is configured to acquire information about a temperature change in an environment of the sensor, and to counteract a temperature change in the sensor on the basis of the information by driving the heating structure.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: September 29, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Ulrich Krumbein, Werner Simbuerger, Dietmar Straeussnigg, Andreas Wiesbauer
  • Patent number: 10763831
    Abstract: A circuit includes a base pulse generator to generate a first pulse width modulated (PWM) pulse, a first clock generation circuit to generate M clocks of a first frequency and phase-shifted with respect to each other, and a second clock generation circuit to receive the M clocks and to generate N clocks each at a second lower frequency and the M clocks are phase-shifted with respect to each other. Each of a plurality of flip-flops includes a clock input to receive a different one of the N clocks, a data input coupled to receive the first PWM pulse, and a flip-flop output. A selection circuit includes a plurality of inputs and a selection circuit output. Each of the plurality of inputs is coupled to a corresponding flip-flop output. The selection circuit provides, responsive to a control signal, a selected one of the flip-flop outputs as the selection circuit output.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: September 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Subrahmanya Bharathi Akondy, Nirav Ginwala
  • Patent number: 10739391
    Abstract: Methods and systems for measuring a duty cycle of a signal include applying a first branch of an input signal directly to a latch. A delay of a second branch of the input signal is incrementally increased, with the second branch being applied to the latch, until the latch changes its output. A delay, corresponding to the latch's changed output, is divided by a period of the input signal to determine a duty cycle of the input signal.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Keith A. Jenkins
  • Patent number: 10700672
    Abstract: An electronic system includes a clock generation circuit to generate a clock signal; and a duty cycle monitoring circuit, DTC, to monitor a duty cycle of the generated clock signal. The DTC includes a differential signal generator circuit to generate an inverted and a non-inverted representation of the generated clock signal. An averaging circuit averages the non-inverted representation and the inverted representation of the generated clock signal. A comparison circuit includes at least a first comparator to compare the averaged non-inverted representation of the generated clock signal with a second respective reference voltage threshold and a second comparator configured to compare the averaged inverted representation with a first respective reference voltage threshold.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: June 30, 2020
    Assignee: NXP USA, Inc.
    Inventors: Pierre Savary, Cristian Pavao Moreira, Matthis Bouchayer, Jean-Stephane Vigier
  • Patent number: 10689226
    Abstract: An elevator car travels in a lane (113, 115, 117) of an elevator shaft (111). A linear propulsion system imparts force to the car (214). The system includes a first part (116) mounted in the lane of the shaft and a second part (118) mounted to the elevator car configured to co-act with the first part to impart movement to the car. Car state sensors (360a-c) are disposed in the lane and determine a state space vector of the car within the lane. A sensed element (364) on the car is sensed by the plurality of car state sensors when the car is in proximity to the respective car state sensor. A control system (225) applies an electrical current to at least one of the first part and the second part and the plurality of car state sensors communicate with the control system and the linear propulsion system to provide state space vector data.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: June 23, 2020
    Assignee: OTIS ELEVATOR COMPANY
    Inventors: Peter DePaola, Jr., Richard N. Fargo, David Ginsberg, Dang V. Nguyen, Shashank Krishnamurthy
  • Patent number: 10693385
    Abstract: An apparatus comprises a first capacitor and a second capacitor connected in series, a diode and the second capacitor connected in parallel, wherein a cathode of the diode is connected to a common node of the first capacitor and the second capacitor and a plurality of adjustable capacitance networks connected in parallel with the second capacitor.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: June 23, 2020
    Assignee: Quanten Technologies Limited
    Inventor: Hengchun Mao
  • Patent number: 10671113
    Abstract: Technologies for synchronized sampling of counters include a computing device to determine a global clock to which the computing device and a plurality of other computing devices are to be synchronized. The computing device receives a request to sample a counter of the computing device from an administration server and records a state of the counter based on the global clock in response to receiving the request.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventor: Thomas D. Lovett
  • Patent number: 10659029
    Abstract: An apparatus in a PWM modulator includes a triangular wave generator that generates a triangular wave and a comparator that is responsive to a signal input to generate a signal output. An output of the PWM modulator is responsive to the comparator signal output. A polarity inversion circuit, coupled between the triangular wave generator and the comparator, is configured in one of the following ways: to provide the triangular wave to the comparator when the triangular wave has a first slope polarity and to provide a polarity-inverted version of the triangular wave to the comparator when the triangular wave has a second slope polarity opposite the first slope polarity; and to provide the signal input to the comparator when the triangular wave has the first slope polarity and to provide a polarity-inverted version of the signal input to the comparator when the triangular wave has the second slope polarity.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: May 19, 2020
    Assignee: CIRRUS LOGIC, INC.
    Inventors: Ramin Zanbaghi, Anuradha Parsi, Kyehyung Lee, John L. Melanson
  • Patent number: 10627852
    Abstract: A method and system for synchronized switching of voltage regulators in an IHS. The method includes determining, via a master voltage regulator (VR) controller, a plurality of phase shifts for a plurality of VRs configured as a master VR and at least one slave VR. The phase shifts are determined such that the VRs switch at different times from each other. A common clock signal and the phase shifts are transmitted to each of the slave VRs.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: April 21, 2020
    Assignee: Dell Products, L.P.
    Inventors: Ralph H. Johnson, Stuart A. Berke, Lei Wang
  • Patent number: 10573476
    Abstract: Contacts of a relay may glue together during operation. This state may be measured and a controller may issue a pulse width-modulated signal at a certain duty cycle and frequency in order to vibrate the relay contacts to make them open again. Once this is the case, the process is stopped. This process may be repeated a certain number of times, and if successfully degluing is not possible, a notification may be generated. Also after a certain number of degluing cycles, a signal may be generated to indicate replacement of the relay.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: February 25, 2020
    Assignee: Electrolux Appliances Aktiebolag
    Inventors: Laurent Jeanneteau, Alex Viroli, Massimo Nostro, Fabio Angeli
  • Patent number: 10566962
    Abstract: This application relates to digital PWM modulation. A PWM modulator (400, 1100) has a PWM generator (402) configured to receive pulse width data (PWidth) and to output a PWM signal (SPWM) comprising a plurality of repeating PWM cycle periods, in which the duration of any pulse of the PWM signal in each PWM cycle period is based on the pulse width data. The PWM generator is configured to synchronise the PWM cycle periods, and the start and end of any PWM pulse, to a received first clock signal. The PWM generator is operable to generate pulses that have a positional error from a centred position within the PWM cycle period and a pulse position controller (403) is configured to control the position of a pulse in a PWM cycle period so as to at least partly compensate for the positional error of one or more preceding pulses.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: February 18, 2020
    Assignee: Cirrus Logic, Inc.
    Inventor: Toru Ido
  • Patent number: 10566939
    Abstract: A circuit comprising: an input terminal configured to receive an input-signal; an output terminal configured to provide an output-signal; a reference circuit comprising: a first output terminal configured to provide a first-reference-signal; a second output terminal configured to provide a second-reference-signal; and a third output terminal configured to provide a third-reference-signal. A comparator-block configured to compare a comparator-input-voltage-signal representative of signalling received at the input terminal with: (i) the first-reference-signal, (ii) the second-reference-signal and (iii) the third-reference-signal in order to generate a comparison-signal. A control-block configured to set the output-signal as one of at least two voltage levels based on the comparison-signal; and an input-control-circuit configured to apply a feedback-control-signal to the input-terminal based on the comparison-signal.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: February 18, 2020
    Assignee: NXP B.V.
    Inventors: Marco Berkhout, Paulus Petrus Franciscus Maria Bruin
  • Patent number: 10557901
    Abstract: Power systems and circuitry for generation of gradient magnetic fields in magnetic resonance imaging (MRI) systems are discussed herein. Embodiments may include the use of multiple gradient amplifiers that share a high-frequency power distribution unit, that may perform power distribution and power supply roles. The high-frequency power distribution unit may allow the use of a single power supply to drive multiple gradient amplifiers via a shared power bus. The gradient amplifiers may make use of modern semiconductor materials that provide high-frequency, high voltage performance, and may be implemented using single semiconductor bridges.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: February 11, 2020
    Assignee: General Electric Company
    Inventors: Viswanathan Kanakasabai, Jayanti Ganesh, Juan Antonio Sabate
  • Patent number: 10547315
    Abstract: A frequency divider may include: a core circuit including a first flip-flop loop and a second flip-flop loop, wherein each of the first flip-flop loop and the second flip-flop loop divides a frequency of a clock signal received via a control terminal of a flip-flop, wherein the core circuit is configured to: output a frequency-divided signal, based on a first signal output by the first flip-flop loop and a second signal output by the second flip-flop loop, the first and second signals having same frequency-division ratios and different phases, and feed back the frequency-divided signal via an input terminal of each of the first and second flip-flop loops; a duty correction circuit that receives the frequency-divided signal and outputs a differential output signal that is generated by correcting a duty ratio of the frequency-divided signal; and an output circuit that outputs a first output signal, which is a signal amplified from the differential output signal, and a second output signal that is a quadrature s
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: January 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-won Choi, Nam-seog Kim
  • Patent number: 10547297
    Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: January 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
  • Patent number: 10541610
    Abstract: An integrated circuit. The integrated circuit comprises a timebase generator and a switch mode direct current-to-direct current (DC-to-DC) converter coupled to the timebase generator. The timebase generator comprises a linear feedback shift register (LFSR) having an output and a logic circuit comprising a first logic inverter, a first AND logic gate, and a first multiplexer, wherein the first logic inverter has an input coupled to a most significant bit of the output of the LFSR, wherein the first AND logic gate has a first input coupled to a second most significant bit of the output of the LFSR and a second input coupled to an output of the first logic inverter, wherein a selector input of the first multiplexer is coupled to an output of the first AND logic gate.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 21, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Joerg Erik Goller
  • Patent number: 10530342
    Abstract: Clock distribution circuitry configured for duty cycle control, the circuitry comprising: a plurality of buffers connected in series along a clock path, each of the buffers having an input terminal and an output terminal, the input terminal being connected to the clock path via a corresponding AC coupling capacitor, and the clock, path configured to receive an input clock signal at its input node and output an output clock signal at its output node, the output clock signal having an output duty cycle; and control circuitry connected to apply a DC bias signal to the input terminal of each of the plurality of buffers, wherein the control circuitry is configured to: obtain a measurement signal indicative of the output duty cycle; and control the DC bias signals, based on a difference between the measurement signal and a reference signal, so as to control the output duty cycle.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: January 7, 2020
    Assignee: SOCIONEXT INC.
    Inventors: Sylvain Panier, Behzad Farzaneh, Darren Walker, Ian Juso Dedic
  • Patent number: 10530344
    Abstract: In described examples, a method of generating a pulse width modulation (PWM) signal includes repeatedly master control counting, by a master control counter generator, which includes one or both of incrementing and decrementing a master control counter with a minimum value and a maximum value, and repeatedly slave control counting with a phase delay with respect to the master control counting, and during a transition period, slave control counting to a new maximum value or a new phase delay. A maximum count of the transition period is selected to result in the transition period reaching the minimum value at the new phase delay count. The PWM signal is generated by generating rising edges when the slave control counter reaches a rising edge threshold, and generating falling edges when the slave control counter reaches a falling edge threshold.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hrishikesh Ratnakar Nene, Subrahmanya Bharathi Akondy, Kristopher Sean Parrent
  • Patent number: 10498317
    Abstract: Various arrangements for decreasing harmonics of an output digital signal are presented. A programmable current rise-time circuit may be present that controls a rising edge of the output digital signal, wherein the output digital signal is output to an input/output (I/O) pad. A programmable current fall-time circuit may be present that controls a falling edge of the output digital signal. A feedback circuit may be present that monitors a rise-time of the rising edge of the output digital signal and fall-time of the falling edge of the output digital signal. A control circuit may be present that provides a first input to the programmable current rise-time circuit to adjust the rise-time of the rising edge of the output digital signal and a second input to the programmable current fall-time circuit to adjust the fall-time of the falling edge of the output.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: December 3, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Hassan Elwan
  • Patent number: 10482935
    Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: November 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-june Park, Jeong-Don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
  • Patent number: 10483913
    Abstract: A Pierce oscillator is provided with a transconductance amplifier transistor having a DC drain voltage that is regulated to equal a reference voltage independently from a DC gate voltage for the transconductance amplifier transistor.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: November 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Ali Najafi, Soheil Golara, Rabih Makarem, Shervin Moloudi
  • Patent number: 10367480
    Abstract: A method for generating a pulse width modulation (PWM) signal, by a processor communicatively coupled to a system memory element, is provided. The method computes, by the processor, a coarse adjustment PWM output signal and a modified fine adjustment input signal, using a low speed clock rate; performs, by the processor, a fine adjustment to the coarse adjustment PWM output signal, using a high speed clock rate, based on the modified fine adjustment input signal; and generates an increased resolution PWM output signal, by the processor, based on the fine adjustment.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: July 30, 2019
    Assignee: HONEYWELL INTERNATIONAL INC.
    Inventors: Thom Kreider, Paul D. Kammann, Vincent James Gavagan, IV
  • Patent number: 10333735
    Abstract: The present invention provides an electronic circuit for controlling an actuator comprising a transceiver unit (1) for a bus system the bus terminal (2) of which has a monostable behavior with an active period of greater than 1 ms, wherein the transceiver unit (1) is controlled by a microcontroller (3), wherein the monostable behavior of the transceiver unit (1) is switched off with additionally superimposed control pulses, wherein the time interval between two control pulses is smaller than the monostable active period of the transceiver unit (1) and the control pulses are generated by temporal combination of two control signals the time resolution of which is lower than the pulse duration of the control pulses derived therefrom, which is implemented by use of a RC combination (4) and/or a logic gate (6) with a differentiating or delaying effect.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: June 25, 2019
    Assignee: IFM ELECTRONIC GMBH
    Inventor: Jörg Schulz
  • Patent number: 10300272
    Abstract: A system and method are presented that electrically stimulates the phrenic nerve whereby said stimulation results in muscle activation of the diaphragm as observed by a measurement of work or power of breathing associated with the inspiratory portion of a stimulated breath.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: May 28, 2019
    Assignee: Stimdia Medical, Inc.
    Inventors: John O'Mahony, Patrick J. Wethington
  • Patent number: 10291218
    Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 14, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
  • Patent number: 10250241
    Abstract: An apparatus and corresponding method for outputting a protocol pulse based on a speed signal representing speed of an object. The apparatus includes a zero-crossing circuit, and a delay circuit. The zero-crossing circuit is configured to output the protocol pulse at a zero-crossing of the speed signal. The delay circuit is coupled to the output of the zero-crossing circuit and configured to delay the protocol pulse. A first edge of the protocol pulse is asynchronous with a clock, and a second edge of the protocol pulse is synchronous with the clock.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: April 2, 2019
    Assignee: Infineon Technologies AG
    Inventors: Simon Hainz, Theodor Kranz, Hubert Fischer, Tobias Werth
  • Patent number: 10243550
    Abstract: An electronic device includes a power switch having a control terminal coupled to a first node, a first conduction terminal coupled to a second node, and a second conduction terminal coupled to a third node. A monitoring circuit has a first input coupled to the first node and a second input coupled to the second node, the monitoring circuit to generate a monitor signal indicating gate oxide stress on the power switch as a function of first and second voltages received at the first and second inputs thereof. A protection circuit actuates to protect the power switch from the gate oxide stress when the monitor signal indicates the gate oxide stress on the power switch. The monitoring signal is generated based upon a comparison of currents generated based upon the voltages at the first and second node, as well as a current generated based upon a programmable reference voltage.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics, Inc.
    Inventor: Pavan Nallamothu
  • Patent number: 10243460
    Abstract: A voltage converter includes a power stage coupled to a power source, a passive circuit coupling the power stage to an output capacitor, a synchronous rectification (SR) switch operable to couple the passive circuit to ground when the SR switch is conducting, a linear controller and an adaptive voltage positioning (AVP) circuit. The linear controller is operable to control switching of the SR switch and switch devices included in the power stage, to regulate an output voltage of the voltage converter based on a reference voltage. The AVP circuit operable to generate an offset voltage applied to the reference voltage based on a first signal representing output current of the voltage converter, and to subtract a second signal from the first signal. The second signal approximates a surge current applied to the output capacitor via the passive circuit for charging the output capacitor during transitions in the reference voltage.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 26, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Amir Babazadeh
  • Patent number: 10211841
    Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: February 19, 2019
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
  • Patent number: 10171093
    Abstract: A method of controlling and maintaining a constant slew rate at an output of a buffer is provided. The method includes the following steps: (a) receiving, (i) a first input signal and (ii) at least one of a control voltage using the buffer; (b) generating a threshold voltage using a first reference voltage generator; (c) comparing (i) the threshold voltage with an output of the buffer using at least one of a comparator; (d) determining a phase difference using a phase detector; (e) producing a DC voltage using a loop filter; (f) generating a reference voltage; (g) receiving the DC voltage and the reference voltage using an amplifier; (h) amplifying the difference between (a) said DC voltage, and (b) the reference voltage to obtain a control voltage using the amplifier; and (i) feeding the control voltage to the buffer.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: January 1, 2019
    Inventors: Himamshu Gopalakrishna Khasnis, Sujith Kumar Nagaraj
  • Patent number: 10135274
    Abstract: A charging circuit for charging a battery of an electronic device includes a first switch having one side connected to an interface into which external power is input, a second switch having one side connected to the other side of the first switch, a third switch having one side connected to the other side of the second switch, a fourth switch having one side connected to the other side of the third switch, a flying capacitor located between the other side of the first switch and the other side of the third switch, an inductor having one side connected to the other side of the second switch, and a control circuit for controlling a charging function of the battery by controlling on/off of the first switch, the second switch, the third switch and the fourth switch.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: November 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kisun Lee
  • Patent number: 10057046
    Abstract: The present disclosure relates to a method and system for calibrating transceivers by providing a stored index that was calculated of a race condition count. The race condition is based at least in part to a rat race between a clock signal and an input signal that has been sampled by a random or jitter signal. The stored index corresponds to a relative timing error between the clock signal and the sampled input signal. The stored index is used to scramble subsequent input signals that are thermo-coded signals, thereby eliminating timing errors.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: August 21, 2018
    Assignee: SITUNE CORPORATION
    Inventors: Hamid Nejati, Vahid M. Toosi, Saeid Mehrmanesh, Marzieh Veyseh
  • Patent number: 10038432
    Abstract: A duty correction circuit may be provided. The duty correction circuit may include a control circuit configured to generate a duty correction control signal by detecting edges of first and second differential clock signals. The duty a duty correction clock signal generation circuit may be configured to generate a duty correction clock signal according to edges of the duty correction control signal.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 31, 2018
    Assignee: SK hynix Inc.
    Inventor: In Hwa Jung
  • Patent number: 9979394
    Abstract: The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The first latch input may be coupled to a fixed logic value. The one of the set input or the reset input may be coupled to a clock signal or an inverted clock signal, respectively. The apparatus may include an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output. The clock signal may be coupled to the first AND gate input. The first latch output may be coupled to the second AND gate input. The AND gate output may be configured to output a pulsed clock. The pulsed clock may be coupled to the first pulse clock input.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: May 22, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Qi Ye, Animesh Datta, Venkatasubramanian Narayanan, Venugopal Boynapalli
  • Patent number: 9979382
    Abstract: A method of detecting clock duty cycle and adjusting clock duty cycle to achieve a clock with low jitters, low noise, high common mode rejection and high power supply rejection for sampling circuit. Adjusting the duty cycle of the sampling clock can enhance data converter's performance.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: May 22, 2018
    Inventors: Yuan-Ju Chao, Ta-Shun Chu
  • Patent number: 9966934
    Abstract: A duty correction device may be provided. The duty correction device may include a duty controller configured to output a control signal by controlling a duty of a duty corrected signal, and detect a level of a feedback signal to convert the duty based on a code signal which is applied at a section where the level of the feedback signal corresponds to a logic level. The duty correction device may include a power gating circuit configured to generate the feedback signal by driving the control signal.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: May 8, 2018
    Assignee: SK hynix Inc.
    Inventors: Geun Ho Choi, Dong Kyun Kim, Min Su Park, Dong Uk Lee
  • Patent number: 9952334
    Abstract: A pulse detection circuit according to an embodiment includes a conversion circuit, a delay circuit, first and second comparators, a latch, and a generation circuit. The conversion circuit converts an input signal into a thermometer code signal. The delay circuit outputs a delay signal being the thermometer code signal delayed by a predetermined delay time. The first comparator (The second comparator) compares the thermometer code signal with the delay signal and outputs an increase signal (a decrease signal) indicating whether the input signal is larger (smaller) than the input signal before the delay time. Based on the increase signal and the decrease signal, the latch outputs an increase-decrease signal indicating whether the input signal is increasing or decreasing. Based on the thermometer code signal and the increase-decrease signal, the generation circuit generates a pulse detection signal and a pileup detection signal.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: April 24, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hirokatsu Shirahama, Tetsuro Itakura, Masanori Furuta, Shunsuke Kimura, Go Kawata, Hideyuki Funaki