Abstract: Apparatuses, duty cycle adjustment circuits, adjustment circuits, and methods for duty cycle adjustment are disclosed herein. An example duty cycle adjustment circuit may be configured to receive a signal and adjust a duty cycle of the signal a first amount using a coarse adjustment. The duty cycle adjustment circuit may further be configured, after adjusting the duty cycle of the signal a first amount, to adjust the duty cycle of the signal a second amount different from the first amount using a fine adjustment to provide a duty cycle adjusted signal.

Abstract: A multi-segment digital-to-time converter is provided. The digital-to-time converter includes a plurality of delay stages arranged in series, and a plurality of local synchronization logic circuits each configured to control an associated delay stage of the plurality of delay stages. Each local synchronization logic circuit provides a digital-to-time converter code and a reset signal to the associated delay stage synchronized to a local input clock and a local output clock of the associated delay stage.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to buffer an input voltage. An example apparatus includes first inverter circuitry to invert the input voltage and produce a first inverted voltage; second inverter circuitry coupled to the first inverter circuitry, the second inverter circuitry to invert the first inverted voltage and produce a second inverted voltage at a rate based on a first current controlled transistor; third inverter circuitry coupled to the second inverter circuitry, the third inverter circuitry to invert the second inverted voltage and produce a third inverted voltage at a rate based on a second current controlled transistor; and fourth inverter circuitry coupled to the third inverter circuitry, the fourth inverter circuitry to invert the third inverted voltage and produce an output voltage, wherein the output voltage matches the input voltage.

Abstract: A BD type pulse width modulation (PWM) circuit is configured to convert a pair of complementary input signals to a pair of output PWM signals. The BD PWM circuit modulates a basic modulation signal according to the pair of input signals, to generate a basic PWM signal. The common mode levels of the pair of input signals and the basic modulation signal are the same. The BD PWM circuit modulates an offset modulation signal according to the pair of input signals to generate an offset PWM signal. The offset modulation signal and the basic modulation signal have a non-zero offset in between. The BD PWM circuit selects the offset PWM signal or a heavy load PWM signal as the pair of output PWM signals. The heavy load PWM signal is correlated with the basic PWM signal.

Abstract: Aspects of the present disclosure control aging of a signal path in an idle mode to mitigate aging. In one example, an input of the signal path is alternately parked low and high over multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, a clock signal (e.g., a clock signal with a low frequency) is input to the signal path during idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, the input of the signal path is parked high or low during each idle period based on an aging pattern.

Abstract: A memory includes: a clock generation circuit, configured to generate a first oscillation signal and a second oscillation signal. The first oscillation signal and the second oscillation signal have a same frequency but opposite phases, and a duty cycle of the first oscillation signal and a duty cycle of the second oscillation signal are both within a first preset range. The memory further includes a differential input circuit, which is configured to receive a first external signal and a second external signal, and generate a first internal signal and a second internal signal. The clock generation circuit is configured to monitor the duty cycle of the first internal signal or the duty cycle of the second internal signal, and enable the duty cycle of the first internal signal or the duty cycle of the second internal signal to be within a second preset range.

Abstract: A voltage supply circuit includes a charging circuit, a window adjustment circuit, a driving voltage adjustment circuit, a sampling and feedback circuit and a storage circuit. The charging circuit includes a modulation input terminal for receiving a control voltage; and an energy supply terminal for selectively outputting a charging energy according to the control voltage. The window adjustment circuit is used to adjust the control voltage according to a sampling output voltage corresponding to an output voltage signal, and output the control voltage. The driving voltage adjustment circuit is used to keep the control voltage within a clamping voltage according to the output voltage signal. The sampling and feedback circuit is used to generate the output voltage signal according to a voltage at the energy supply terminal. The storage circuit is used to store the charging energy to pull up the voltage at the energy supply terminal.

Abstract: An apparatus includes a regulator, a modulation circuit, a first delay generator, and a second delay generator. The regulator generates a regulator control output signal to control a current of a power converter to regulate an output voltage of the power converter, the modulation circuit modulates a switching frequency of the power converter, the first delay generator controls a first delay time to turn on a switch of the power converter in a switching cycle, based on a change in the switching frequency of the power converter, and the second delay generator controls a second delay time to turn the switch of the power converter off in the switching cycle, based on the first delay time and a duty cycle of the power converter.

Abstract: To provide a power converter which can distribute heat generation of the switching devices with good accuracy, even when the maximum heating phase of the positive electrode side and the maximum heating phase of the negative electrode side are different phases, and even when the maximum heating phase of the positive electrode side and the maximum heating phase of the negative electrode side changes before and after combining the offset voltage. The power converter calculates the offset voltage that makes the positive electrode side maximum heating evaluation value and the negative electrode side maximum heating evaluation value coincide with each other, in a state of controlling on/off the switching devices based on the combined AC voltage commands of the offset voltage.

Abstract: To provide a filter circuit and a semiconductor device capable of preventing circuit malfunction even when power supply voltage fluctuates. A filter circuit includes: a latch circuit configured to latch a set signal input to a first input terminal and a reset signal input to a second input terminal, respectively; and a rise adjustment unit configured to make a rise time of the set signal or the reset signal at power-on shorter than a time specified by a time constant circuit arranged in a preceding stage of the latch circuit.

Abstract: An apparatus includes: a generation unit that generates a PWM wave based on a sound signal; and a processing unit that converts the PWM wave to a square wave. The processing unit includes: a first counter that determines a pulse width of the PWM wave; a comparison unit that compares a first difference value, obtained by subtracting the pulse width in a second cycle being a cycle immediately preceding a first cycle from the pulse width in the first cycle, and a second difference value obtained by subtracting the pulse width in a cycle immediately preceding the second cycle from the pulse width in the second cycle; and an output unit that outputs the square wave while switching a state thereof in a case where a sign of the first difference value changes from that of the second difference value.

Abstract: A duty margin monitoring circuit, coupled to a functional circuit which generates a first output signal in response to a target signal, includes a modulation circuit, a replica circuit and an error detection circuit. The modulation circuit is arranged to receive the target signal and modulate the target signal to generate a modulated target signal. The replica circuit is arranged to receive the modulated target signal and generate a second output signal in response to the modulated target signal. The error detection circuit is coupled to the functional circuit and the replica circuit to receive the first output signal and the second output signal and arranged to generate an error detection result according to the first output signal and the second output signal.

Abstract: A method for multiple copies of a set of multi-kernel set operations in a hardware accelerated neural network includes a word line for receiving a pixel value of an input image. A bit line communicates a modified pixel value. An analog memory cell including a first capacitor stores a first kernel weight of a first kernel in one of a plurality of kernel sets such that the pixel value is operated on by the first kernel weight to produce the modified pixel value. A charge connection connects the first capacitor to at least a second capacitor storing a second kernel weight of a related kernel of a second one of the plurality of kernel sets such that charge is shared between the first capacitor and at least the second capacitor to normalize the first kernel weight and the second kernel weight.

Abstract: The present disclosure relates to circuitry comprising: pulse-width modulation (PWM) circuitry configured to generate a PWM output signal; and monitoring circuitry configured to monitor a supply voltage to the PWM circuitry and to output a control signal for controlling operation of the PWM circuitry, wherein the control signal is based on the supply voltage.

Abstract: This application discloses a method and an apparatus for processing a nuclear energy spectrum. The apparatus includes: a detector, a nuclear pulse processing module, and a nuclear energy spectrum processing module; the detector is configured to detect nuclear radiation and convert the nuclear radiation into nuclear pulse signals with corresponding amplitudes; the nuclear pulse processing module is configured to shape the nuclear pulse signals into narrow pulses, and perform amplitude analysis on the narrow pulses to generate the nuclear energy spectrum; the nuclear energy spectrum processing module is configured to reduce a value of an energy resolution of the nuclear energy spectrum to obtain the nuclear energy spectrum with the energy resolution of the reduced value.

Abstract: The inventive concepts relate to methods for duty cycle correction of an input signal and circuits thereof. The method comprising following operations of generating, a plurality of intermediate delayed input signals, each delayed by at least a unit delay, through a delay line driven by the input signal, selecting from among the plurality of delayed input signals, through a first control signal, where the selection is based on number of unit delays in the input signal, generating at least an incremented duty signal and a decremented duty signal based on the selected delayed signals and the input signal, generating, a corrected duty cycle based on the selection of at least one of: the incremented duty cycle or decremented duty cycle by providing a second control signal. The inventive concepts offer low power consumption and low area for correction or adjustment of the duty cycle of the input signal with higher probability or guaranteed monotonicity.

Abstract: An image sensor includes a pixel array having a plurality pixels arranged in a plurality of pixel clusters coupled to a plurality of column busses, a plurality of voltage supplies coupled to the plurality of pixel clusters, and ping-pong readout circuitry. Pixel clusters in adjacent column busses are supplied with different voltage supplies. The ping-pong readout circuitry includes multiplexing circuitry coupled to the plurality of column busses, and a plurality of analog-to-digital converters coupled to the multiplexing circuitry. The image sensor also includes a controller configured to selectively couple a pixel signal of a pixel cluster to a column bus to an ADC for signal conversion.

Abstract: A system may include a memory configured to store instructions and a processor. The processor may be configured to execute the instructions to cause the system to determine a PWM frequency of the input PWM signal and generate a first PWM signal to power a first light emitting diode (LED), a second PWM signal to power a second LED, and a third PWM signal to power a third LED. Each of the first PWM signal, the second PWM signal, and the third PWM signal may have the PWM frequency of the input PWM signal and may be in phase with the input PWM signal.

Abstract: A switching time generation circuit can include: a regulation circuit configured to generate a regulation signal in accordance with change information of an output signal of a switching converter; and the regulation circuit being configured to adjust a switching state of a power switch based on the regulation signal, where the switching converter includes a power stage circuit having the power switch.

Abstract: A system on chip includes a first clock generator that generates a first clock to be sent to a memory device, a second clock generator that generates a second clock to be sent to the memory device, a command and address generator that generate a code for adjusting a duty cycle of a third clock generated within the memory device based on the second clock and generates a command for storing the code to mode registers of the memory device, the third clock being used for a data input/output of the memory device, a data receiver that receives a data strobe signal and a data input/output signal output from the memory device receiving the command and the code synchronized with the first clock, and a training circuit that calculates a plurality of valid window margins for the code based on the data strobe signal and the data input/output signal.

Abstract: Systems and methods for scrambling data-port audio in SOUNDWIRE™ systems include a scramble enable feature that allows a data source to scramble an outgoing channel content with a cyclic linear feedback shift register (LFSR) using a pseudo-random binary sequence (PRBS) such as, but not limited to, the PRBS defined in the SOUNDWIRE specification. Data ports for audio sinks receiving the scrambled content descramble the content for use by the audio sink. In a specific exemplary aspect, an output of the LFSR is added or subtracted with the audio data to make the microphones independent of one another and reduce crosstalk.

Abstract: In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.

Abstract: A drive assist circuit includes a pulse generation circuit which outputs a pulse to control an assist operation when an assist signal makes a first transition corresponding to a transition of a gate signal from a high level to a low level. The pulse generation circuit includes a delay circuit provided in one of two inputs of a logic gate. The delay circuit is configured such that a delay is greater when an input makes a transition corresponding to the first transition of the assist signal, as compared to a case where the input makes a transition corresponding to an inverse of the first transition.

Abstract: A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.

Abstract: A method is provided for transmitting information and a device for carrying out the method, in which images are photographed by a camera with an image-taking rate, thus, especially frame rate, a controllable illuminant being disposed in the responsive range of the camera, where the control frequency (f_PWM) of the illuminant is less than the image-taking rate f1.

Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.

Abstract: Power systems and circuitry for generation of gradient magnetic fields in magnetic resonance imaging (MRI) systems are discussed herein. Embodiments may include the use of multiple gradient amplifiers that share a high-frequency power distribution unit, that may perform power distribution and power supply roles. The high-frequency power distribution unit may allow the use of a single power supply to drive multiple gradient amplifiers via a shared power bus. The gradient amplifiers may make use of modern semiconductor materials that provide high-frequency, high voltage performance, and may be implemented using single semiconductor bridges.

Abstract: A pulse width compensation circuit may include a voltage control circuit and a pulse width adjustment circuit. The voltage control circuit may sense a voltage level of a first power supply voltage and generate a voltage control signal. The pulse width adjustment circuit may generate an output signal by changing a pulse width of an input signal based on the voltage control signal.

Abstract: A method for the activation of power semiconductors in an inverter using a microprocessor controlling a pulse width modulation (PWM). The method serves for improving the electromagnetic compatibility (EMC) and is in particular applicable in electric refrigerant compressors of motor vehicles.

Abstract: A semiconductor apparatus includes a first clock path which generates a first output clock signal by delaying a first phase clock signal, and a second clock path which generates a second output clock signal by delaying a second phase clock signal based on a delay compensation signal. The oscillating path generation circuit forms oscillating paths with the first clock path and the second clock path. The delay information generation circuit generates a delay compensation signal based on oscillating signals generated by forming the oscillating paths.

Abstract: A sensor circuit and a method for compensating for temperature changes are provided. In accordance with an embodiment, sensor circuit includes at least one sensor for determining a measurement variable; a heating structure; and at least one compensation circuit. The compensation circuit is configured to acquire information about a temperature change in an environment of the sensor, and to counteract a temperature change in the sensor on the basis of the information by driving the heating structure.

Abstract: A circuit includes a base pulse generator to generate a first pulse width modulated (PWM) pulse, a first clock generation circuit to generate M clocks of a first frequency and phase-shifted with respect to each other, and a second clock generation circuit to receive the M clocks and to generate N clocks each at a second lower frequency and the M clocks are phase-shifted with respect to each other. Each of a plurality of flip-flops includes a clock input to receive a different one of the N clocks, a data input coupled to receive the first PWM pulse, and a flip-flop output. A selection circuit includes a plurality of inputs and a selection circuit output. Each of the plurality of inputs is coupled to a corresponding flip-flop output. The selection circuit provides, responsive to a control signal, a selected one of the flip-flop outputs as the selection circuit output.

Abstract: Methods and systems for measuring a duty cycle of a signal include applying a first branch of an input signal directly to a latch. A delay of a second branch of the input signal is incrementally increased, with the second branch being applied to the latch, until the latch changes its output. A delay, corresponding to the latch's changed output, is divided by a period of the input signal to determine a duty cycle of the input signal.

Abstract: An electronic system includes a clock generation circuit to generate a clock signal; and a duty cycle monitoring circuit, DTC, to monitor a duty cycle of the generated clock signal. The DTC includes a differential signal generator circuit to generate an inverted and a non-inverted representation of the generated clock signal. An averaging circuit averages the non-inverted representation and the inverted representation of the generated clock signal. A comparison circuit includes at least a first comparator to compare the averaged non-inverted representation of the generated clock signal with a second respective reference voltage threshold and a second comparator configured to compare the averaged inverted representation with a first respective reference voltage threshold.

Abstract: An elevator car travels in a lane (113, 115, 117) of an elevator shaft (111). A linear propulsion system imparts force to the car (214). The system includes a first part (116) mounted in the lane of the shaft and a second part (118) mounted to the elevator car configured to co-act with the first part to impart movement to the car. Car state sensors (360a-c) are disposed in the lane and determine a state space vector of the car within the lane. A sensed element (364) on the car is sensed by the plurality of car state sensors when the car is in proximity to the respective car state sensor. A control system (225) applies an electrical current to at least one of the first part and the second part and the plurality of car state sensors communicate with the control system and the linear propulsion system to provide state space vector data.

Abstract: An apparatus comprises a first capacitor and a second capacitor connected in series, a diode and the second capacitor connected in parallel, wherein a cathode of the diode is connected to a common node of the first capacitor and the second capacitor and a plurality of adjustable capacitance networks connected in parallel with the second capacitor.

Abstract: Technologies for synchronized sampling of counters include a computing device to determine a global clock to which the computing device and a plurality of other computing devices are to be synchronized. The computing device receives a request to sample a counter of the computing device from an administration server and records a state of the counter based on the global clock in response to receiving the request.

Abstract: An apparatus in a PWM modulator includes a triangular wave generator that generates a triangular wave and a comparator that is responsive to a signal input to generate a signal output. An output of the PWM modulator is responsive to the comparator signal output. A polarity inversion circuit, coupled between the triangular wave generator and the comparator, is configured in one of the following ways: to provide the triangular wave to the comparator when the triangular wave has a first slope polarity and to provide a polarity-inverted version of the triangular wave to the comparator when the triangular wave has a second slope polarity opposite the first slope polarity; and to provide the signal input to the comparator when the triangular wave has the first slope polarity and to provide a polarity-inverted version of the signal input to the comparator when the triangular wave has the second slope polarity.

Abstract: A method and system for synchronized switching of voltage regulators in an IHS. The method includes determining, via a master voltage regulator (VR) controller, a plurality of phase shifts for a plurality of VRs configured as a master VR and at least one slave VR. The phase shifts are determined such that the VRs switch at different times from each other. A common clock signal and the phase shifts are transmitted to each of the slave VRs.

Abstract: Contacts of a relay may glue together during operation. This state may be measured and a controller may issue a pulse width-modulated signal at a certain duty cycle and frequency in order to vibrate the relay contacts to make them open again. Once this is the case, the process is stopped. This process may be repeated a certain number of times, and if successfully degluing is not possible, a notification may be generated. Also after a certain number of degluing cycles, a signal may be generated to indicate replacement of the relay.

Abstract: A circuit comprising: an input terminal configured to receive an input-signal; an output terminal configured to provide an output-signal; a reference circuit comprising: a first output terminal configured to provide a first-reference-signal; a second output terminal configured to provide a second-reference-signal; and a third output terminal configured to provide a third-reference-signal. A comparator-block configured to compare a comparator-input-voltage-signal representative of signalling received at the input terminal with: (i) the first-reference-signal, (ii) the second-reference-signal and (iii) the third-reference-signal in order to generate a comparison-signal. A control-block configured to set the output-signal as one of at least two voltage levels based on the comparison-signal; and an input-control-circuit configured to apply a feedback-control-signal to the input-terminal based on the comparison-signal.

Abstract: This application relates to digital PWM modulation. A PWM modulator (400, 1100) has a PWM generator (402) configured to receive pulse width data (PWidth) and to output a PWM signal (SPWM) comprising a plurality of repeating PWM cycle periods, in which the duration of any pulse of the PWM signal in each PWM cycle period is based on the pulse width data. The PWM generator is configured to synchronise the PWM cycle periods, and the start and end of any PWM pulse, to a received first clock signal. The PWM generator is operable to generate pulses that have a positional error from a centred position within the PWM cycle period and a pulse position controller (403) is configured to control the position of a pulse in a PWM cycle period so as to at least partly compensate for the positional error of one or more preceding pulses.

Abstract: Power systems and circuitry for generation of gradient magnetic fields in magnetic resonance imaging (MRI) systems are discussed herein. Embodiments may include the use of multiple gradient amplifiers that share a high-frequency power distribution unit, that may perform power distribution and power supply roles. The high-frequency power distribution unit may allow the use of a single power supply to drive multiple gradient amplifiers via a shared power bus. The gradient amplifiers may make use of modern semiconductor materials that provide high-frequency, high voltage performance, and may be implemented using single semiconductor bridges.

Abstract: A frequency divider may include: a core circuit including a first flip-flop loop and a second flip-flop loop, wherein each of the first flip-flop loop and the second flip-flop loop divides a frequency of a clock signal received via a control terminal of a flip-flop, wherein the core circuit is configured to: output a frequency-divided signal, based on a first signal output by the first flip-flop loop and a second signal output by the second flip-flop loop, the first and second signals having same frequency-division ratios and different phases, and feed back the frequency-divided signal via an input terminal of each of the first and second flip-flop loops; a duty correction circuit that receives the frequency-divided signal and outputs a differential output signal that is generated by correcting a duty ratio of the frequency-divided signal; and an output circuit that outputs a first output signal, which is a signal amplified from the differential output signal, and a second output signal that is a quadrature s

Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

Abstract: An integrated circuit. The integrated circuit comprises a timebase generator and a switch mode direct current-to-direct current (DC-to-DC) converter coupled to the timebase generator. The timebase generator comprises a linear feedback shift register (LFSR) having an output and a logic circuit comprising a first logic inverter, a first AND logic gate, and a first multiplexer, wherein the first logic inverter has an input coupled to a most significant bit of the output of the LFSR, wherein the first AND logic gate has a first input coupled to a second most significant bit of the output of the LFSR and a second input coupled to an output of the first logic inverter, wherein a selector input of the first multiplexer is coupled to an output of the first AND logic gate.

Abstract: In described examples, a method of generating a pulse width modulation (PWM) signal includes repeatedly master control counting, by a master control counter generator, which includes one or both of incrementing and decrementing a master control counter with a minimum value and a maximum value, and repeatedly slave control counting with a phase delay with respect to the master control counting, and during a transition period, slave control counting to a new maximum value or a new phase delay. A maximum count of the transition period is selected to result in the transition period reaching the minimum value at the new phase delay count. The PWM signal is generated by generating rising edges when the slave control counter reaches a rising edge threshold, and generating falling edges when the slave control counter reaches a falling edge threshold.

Abstract: Clock distribution circuitry configured for duty cycle control, the circuitry comprising: a plurality of buffers connected in series along a clock path, each of the buffers having an input terminal and an output terminal, the input terminal being connected to the clock path via a corresponding AC coupling capacitor, and the clock, path configured to receive an input clock signal at its input node and output an output clock signal at its output node, the output clock signal having an output duty cycle; and control circuitry connected to apply a DC bias signal to the input terminal of each of the plurality of buffers, wherein the control circuitry is configured to: obtain a measurement signal indicative of the output duty cycle; and control the DC bias signals, based on a difference between the measurement signal and a reference signal, so as to control the output duty cycle.

Abstract: Various arrangements for decreasing harmonics of an output digital signal are presented. A programmable current rise-time circuit may be present that controls a rising edge of the output digital signal, wherein the output digital signal is output to an input/output (I/O) pad. A programmable current fall-time circuit may be present that controls a falling edge of the output digital signal. A feedback circuit may be present that monitors a rise-time of the rising edge of the output digital signal and fall-time of the falling edge of the output digital signal. A control circuit may be present that provides a first input to the programmable current rise-time circuit to adjust the rise-time of the rising edge of the output digital signal and a second input to the programmable current fall-time circuit to adjust the fall-time of the falling edge of the output.

Abstract: A Pierce oscillator is provided with a transconductance amplifier transistor having a DC drain voltage that is regulated to equal a reference voltage independently from a DC gate voltage for the transconductance amplifier transistor.