Abstract: First and second current detection resistors connected in series are used as current detection resistors for detecting a main current of a switching element. A single-fault detection circuit divides a voltage detected from the main current by first to third resistors. A first comparator compares a voltage at a Detect terminal with a voltage at a connection point of the first and second resistors, and a second comparator compares the voltage at the Detect terminal with a voltage at a connection point of the second and third resistors. When either one of the first and second current detection resistors is short-circuited, the corresponding one of the first and second comparators outputs an L-level signal. Accordingly, an AND circuit outputs a signal indicating a single fault. Since this signal reduces a threshold voltage of the individual comparator by half, the same output voltage as before the fault is maintained.

Abstract: A reverse-conducting insulated gate bipolar transistor, particularly a bi-mode insulated gate transistor, is controlled by responding to an ON command by applying high-level gate voltage for a first period, during which a current is fed into a connection point, from which it flows either through the RC-IGBT or along a different path. Based hereon, it is determined whether the RC-IGBT conducts in its forward/IGBT or reverse/diode mode, and the RC-IGBT is either driven at high or low gate voltage. Subsequent conduction mode changes may be monitored in the same way, and the gate voltage may be adjusted accordingly. A special turn-off procedure may be applied in response to an OFF command in cases where the RC-IGBT conducts in the reverse mode, wherein a high-level pulse is applied for a second period before the gate voltage goes down to turn-off level.

Abstract: Switch cells consist of an array of power switches and passive components which can replace the main switches in many power topologies, allowing reduced switching loss without altering the power topology directly. The switch cell topology discussed herein utilizes a saturable resonant inductor to reduce the size and power loss of the cell. Additionally, the cell transfers energy stored in the inductor into a capacitor for efficient energy storage during the cell's conduction region. This energy is then transferred back to the system when the cell turns off, thus reducing the total switching energy.

Abstract: An electrical resonance network comprising a first capacitor and a first inductor whose resonance frequency can be tuned by means of a second capacitor and/or a second inductor. The resulting effective capacitor- or inductor value of a network period is controlled by a variable coupling respectively decoupling interval by means of at least one coupling switch. The coupling respectively decoupling interval is synchronized by a sign change of a current and/or voltage in the network.

Abstract: The duty correcting circuit includes a duty cycle corrector, a duty detector and a duty correction code generator. The duty cycle corrector corrects a duty cycle of an input clock signal to generate an output clock signal. The duty detector adjusts a delay time of the output clock signal to generate a sampling clock signal, samples the output clock signal in response to the sampling clock signal to generate sample data, and detects a duty of the output clock signal based on logic states of the sample data. Therefore, the duty correcting circuit precisely detects and corrects a duty of the output clock signal.

Abstract: A synchronizing circuit compatible with a quad switching scheme in a digital-to-analog converter (DAC) to synchronize turning on or off of switches for steering current to a differential output. The synchronizing circuit receives signals from a decoder and synchronizes control signals to the switches by a clock signal. In one embodiment, the synchronizing circuit includes a predictor circuit and a latch circuit. The latch circuit may include four sets of cross-coupled inverters where a set of cross-coupled inverters are activated at a time. By using the synchronizing circuit in conjunction with the quad switching scheme, linearity of analog output from the DAC can be improved and data dependent noise in the analog output can be removed or reduced.

Abstract: A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.

Abstract: Method and circuitry for controlling duty cycle of an input signal towards a desired value comprising a sequence of at least two inverters arranged in series and feedback circuitry. A first inverter is arranged to receive the input signal and a last inverter is arranged to output a signal having the same frequency as the input signal. The output signal is an adjusted version of the input signal. The feedback circuitry is arranged to receive the output signal and comprises a comparing and supplying means. The comparing means compares the output signal with a reference signal indicative of a desired value and generates a feedback signal based on the comparison of the output and reference signal. The supplying means supplies the feedback signal to adjust operating conditions of at least one of the inverters, such that the duty cycle of the output signal is controlled towards the desired value.

Abstract: Systems, methods, and apparatus for improving steady state operation of a pulse width modulator during transient and soft start events are described herein. An apparatus can include a phase component configured to adaptively modify a pulse width of a first pulse width modulated (PWM) output signal based on a pulse width of a PWM input signal. Further, the apparatus can include a power stage component configured to source at least one of a voltage or a current to a load based on the first PWM output signal. In one example, the phase component can be configured to linearly extend the pulse width of the first PWM output signal based on the pulse width of the PWM input signal. In another example, the phase component can be configured to adaptively modify the pulse width of the first PWM output signal based on a predetermined maximum pulse width.

Abstract: A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generates PWM control signals for controlling operation of the first and second transistors. The control signals are generated responsive to source PWM signals processed through programmable delay timers to generate set/reset control signals which set an output PWM control signal duty cycle.

Abstract: Dead-time detector includes an N-type power switch and a resistor. The N-type power switch includes a first end coupled to the output end of the output-stage circuit for receiving an output voltage, a second end for outputting a dead-time detecting signal, and a control end for receiving a gate-controlling voltage. The resistor is coupled between the second end of the N-type power switch and a voltage source providing a high voltage for keeping the voltage of the dead-time detecting signal when the N-type power switch does not output the dead-time detecting signal representing “ON”. When the output voltage is so lower than the gate-controlling voltage that the N-type power switch is turned on, the N-type power switch outputs the dead-time detecting signal representing “ON”. When the dead-time detecting signal represents “ON”, the output-stage circuit leaves the dead-time state.

Abstract: A rapidly adjustable local oscillation (LO) module for use in a radio transmitter or a radio receiver includes an oscillation generating module and a high frequency switching module. The oscillation generating module is operably coupled to generate a plurality of local oscillations. The high frequency switching module is operably coupled to, for a first one of a plurality of transmission paths, provide one of the plurality of local oscillations when a first transmission path selection indication is in a first state and provide another one of the plurality of local oscillations when the first transmission path selection indication is in a second state and, for a second one of the plurality of transmission paths, provide the one of the plurality of local oscillations when a second transmission path selection indication is in a first state and provide the another one of the plurality of local oscillations when the second transmission path selection indication is in a second state.

Abstract: The present invention relates to a quadrature divider which may be used in a phase locked loop or frequency synthesizer or with a single side band mixer. According to a preferred embodiment the divider takes a quadrature input and has a quadrature output. The divider has four analog mixers 1, 2, 3 and 4. The first two mixers 1, 2 take the in-phase quadrature input, while the second mixers 3, 4 take the quadrature-phase quadrature input. The outputs and feedback loops of the mixers are properly arranged such that the in-phase and quadrature-phase outputs of the divider have a determinisitic phase sequence relationship based on the phase sequence relationship of the corresponding quadrature inputs. Third order harmonics may be minimized or reduced by addition or subtraction of the mixer outputs. As the divider is able to take a quadrature input, there is no need for a dummy divider in the phase locked loop, thus saving space and power.

Abstract: A multi-mode PLL frequency synthesizer of a wireless multi-mode transceiver is provided which includes a reference frequency source providing an oscillator signal with a constant reference frequency, a first frequency synthesizer subunit for converting the signal into carrier signals with frequencies in the range of a first frequency band, a second frequency synthesizer subunit for transforming the oscillator signal into carrier signals having frequencies in the range of a second frequency band, and a third frequency synthesizer subunit for converting the oscillator signal into an auxiliary signal with a fixed frequency. The auxiliary signal is used together with the carrier signals of the second frequency band to generate carrier signals with frequencies in the range of a third and fourth frequency band.

Abstract: A pulse width modulation (PWM) device, system and method for high resolution fan control are disclosed. In one embodiment, the method comprises determining a target duty cycle of a PWM signal, determining the number of PWM cycles in the period of the PWM signal, pseudo-randomly selecting a duty cycle for each PWM cycle using one or more look-up tables and generating the PWM signal based on the duty cycle.

Abstract: A PWM generator system provides improved duty cycle resolution using a sub-cycle generator for generating a sub-cycle with a period that is a small fraction of the maximum PWM period to be generated. An integral sub-cycle estimator is coupled to said sub-cycle generator for determining the integral number of said sub-cycles for on and off time of the PWM waveform. An additional sub-cycle estimator determines the additional fractional sub-cycle required to provide the on and off time. A timer coupled to the integral sub cycle estimator and the additional sub cycle estimator controls PWM output switching for the on and off time of the integral and additional fractional sub cycles.

Abstract: A pulse width modulation (PWM) control circuit is applied to a power converter with a charging capacitor. The PWM control circuit includes a PWM signal generator, a first comparator, and a reference voltage modulator. A PWM signal generator generates a PWM signal to control a power switch in the power converter. Two input terminals of the first comparator respectively receive a first reference voltage and a sensing voltage, which is proportional to a primary-side current of a transformer. When the power switch is turned on and the sensing voltage rises to the level of the first reference voltage, the first comparator outputs a first control signal to the PWM signal generator. Then, the PWM signal generator outputs a signal to turn off the power switch. The reference voltage modulator outputs the first reference voltage according to a feedback voltage relative to the output voltage of the power converter.

Abstract: In one embodiment, a PWM controller is configured to form a control signal that has reduced noise. The control signal is used to adjust a frequency of a clock signal of the PWM controller.

Abstract: A circuit arrangement for switching a load includes at least one at least partially inductive load, at least one high side switch with a controlled path connected in series with the load and between supply terminals for a supply voltage. At least one freewheeling diode is connected with a first tap between the high side switch and the load. At least one clamp circuit is connected to a control terminal of the high side switch and is used to limit the control potential applied to the control terminal to a first pre-determined voltage value when the high side switch is switched off.

Abstract: A multi-turn pulse width modulation (PWM) generator for generating a PWM output corresponding to multiple 360 degree turns. A counter receives a reference signal, and counts a number of cycles of the reference signal to generate a binary output corresponding to the number of cycles counted. A frequency divider receives a sensor output signal, and divides the frequency of the sensor output signal by the number of turns in the multiple turns to generate a frequency divided signal. The sensor output signal has substantially the same frequency as the reference signal, but can be offset in phase from the reference signal. A demultiplexer receives the binary output, and generates a plurality of turn indicator signals, each corresponding to one of the multiple turns. A multiplexer receives the turn indicator signals and a mechanical turn indication signal, and selects one of the turn indicator signals that corresponds to the mechanical turn indication signal.

Abstract: In a switching arrangement, a plurality of modules are connected such that the main switching elements, FETs, are in series. Control of and power to the FETs is supplied via a single turn primary passing through a plurality of toroidal secondary transformers. A train of control pulses is applied to the single turn primary and their polarity determines whether the main FET is switched on or off, the length of the pulse train determining the pulse width and PRF of the output of the switching arrangement. The control pulses are also used to supply power to the main driver of the main FET.

Abstract: A pulse width control IC circuit that greatly reduces price, increases packaging density,and improves reliability for switching power supply units, wherein the IC circuit is on a single chip and includes a main converter control section that controls the ON and OFF actions of a main switch outside the IC, an output MOSFET, and an auxiliary converter control section that controls the ON and OFF actions of the output MOSFET.

Abstract: Pulse width modulation driver circuitry both limits and regulates the voltage that is applied to a load from a power source which provides a voltage that may far exceed the maximum safe load voltage. The driver circuitry includes a reactive filter coupled to the load, a voltage sensor for sensing the instantaneous voltage across the load, a timer, and a comparator. The reactive filter alternately takes in energy from the power source and discharges it into the load. The voltage sensor, timer, and comparator cooperate with a switch to modulate the application of power to the load and to the reactive filter in response to the instantaneous magnitudes of the load voltage and the power source voltage.

Abstract: A fast, high voltage modulator circuit (10) has a drive circuit (12) apply input pulses to an on-section (88) and an off-section (90). The on-section (88) and off-section (90) having a common output (46). A pair of transformers (18,24) connects the drive circuit (12) to the on-section (88) and off-section (90) respectively. The drive circuit (12) applies a pulse to the first transformer (18), which transmits the pulse to a first MOSFET (32) closing the first MOSFET (32) to connect an input high voltage (40) to the output (46). The drive circuit (12) applies an off pulse to the second transformer (24), which transmits the pulse to second and third MOSFETS (62,82), closing the second MOSFET (62) and connecting a lower input voltage (68) to the output (46). Also, closing the third MOSFET (82) that shorts out a gate (34) of the first MOSFET (32), thus opening the first MOSFET (32). The entire circuit is modular, being stackable to switch higher voltages.

Abstract: High-efficiency clock generator circuits having single or complementary outputs for driving capacitive loads. The clock generator has therein at least one pair of complementary FET switches, coupled between the output of the generator and power supply rails, and an inductor. The generator is operated at a frequency approximately equal the resonant frequency of the inductor combined with the capacitance of the load. Energy normally stored in the load and dissipated in the FETs as in conventional clock generators is instead stored in the inductor and returned to the loads for reuse.