Abstract: High-performance ultra-wideband Phased Array Sensors (PAS) are disclosed, which have unique capabilities, enabled through photonic integrated circuits and novel optical architectures. Unique capabilities for a Receive PAS are provided by wafer scale photonic integration including heterogeneous integration of III-V materials and ultra-low-loss silicon nitride waveguides, combining key component technologies into complex PIC devices. Novel aspects include optical multiplexing combining wavelength division multiplexing and/or a novel extension to array photodetectors providing the capability to combine many RF photonic signals with very low loss. The architecture also includes optical down-conversion, as well as digital signal processing to improve the linearity of the system. Simultaneous multi-channel beamforming is achieved through optical power splitting of optical signals to create multiple exact replicas of the signals that are then processed independently.

Abstract: A circuit and method for adaptively controlling an equalizer circuit to reduce intersymbol interference at low frequencies relative to a transmit frequency of an input signal from a transmitter. The input signal is converted into a data signal by a receiver. At least one delayed data signal is formed by delaying the data signal by at least one unit interval (UI) beyond a length of a decision feedback equalizer (DFE) in the receiver. An error signal is formed by comparing the input signal to a threshold value. An error signal sample is correlated with at least one delayed data signal sample to determine whether to adjust a control coefficient of the equalizer. Thus the equalizer is controlled as if the DFE had at least one additional tap.

Abstract: A solid-state imaging apparatus includes an imaging section in which a plurality of pixels, each of which has a photoelectric conversion element, are disposed in a matrix; a clock generation section; a reference signal generation section configured to generate a reference signal whose amplitude increases or decreases with the passage of time; a comparison section disposed corresponding to a column in an array of the plurality of pixels; a latch section disposed corresponding to the comparison section and configured to latch logic states of the plurality of phase signals; and a latch control section disposed corresponding to the comparison section, wherein the comparison section includes a differential amplifier, a current output element, and a third transistor, and wherein the comparison section outputs a second comparison signal based on the current output from the current output element after the second timing.

Abstract: Architectures of ?? difference-of-squares RMS-to-digital converters employing multiple feedback paths. Additional feedback paths enable a stable ?? closed-loop behavior in different topologies where the RMS level of the quantization error processed by the squaring non-linearity is minimized. Such feedback paths include lowpass filtered and constant gain feedback paths, lowpass and highpass filtered paths or multiple lowpass filtered paths. These can be combined with multiple integrators in the forward path, with frequency compensation provided by additional feedforward or feedback paths. Electronic configurability can further extend the total input referred dynamic range (DR) of such architectures.

Abstract: A sigma-delta (??) difference-of-squares LOG-RMS to digital converter” by merging a traditional ?? modulator with an analog LOG-RMS to DC converter based on a difference-of-squares concept. Two basic architectures include one based on two squaring cells in the feedforward and feedback paths and a second based on a single squaring cell in the forward path. High-order ?? LOG-RMS can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The embodiments as described allow the implementations of ?? difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range.

Abstract: A sigma-delta (??) difference-of-squares LOG-RMS to digital converter for true RMS detection by merging a ?? modulator with an analog LOG-RMS to DC converter based on a difference-of-squares. Chopper-stabilization, implemented through commutators running at two different frequencies, can be employed to reduce sensitivity to DC offsets and low-frequency errors, resulting in an extension of the useful input-referred dynamic range. High-order ?? LOG-RMS converters can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The resulting implementations are ?? difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range.

Abstract: A zero-crossing gain control system is disclosed herein. The system comprises a gain control unit for amplifying an input signal to an output signal, a zero-crossing monitoring circuit for monitoring the input signal or output signal, and a register for latching the digital control signal and generating a gain control signal that controls the gain control unit. The system may further comprise a maximum write time setting circuit for generating a write signal. The digital control signal is written into the register when a zero-crossing state is monitored or a maximum write time since a change occurred on of the digital control signal is expired. An automatic gain control system is also disclosed herein and further comprises a peak detecting circuit for detecting the level of output signal, a logic circuit for lowering or restoring the digital control signal according to the result from the peak detecting circuit.

Abstract: An electronic device according to one or more embodiments of the present invention comprises an output line, a current mirror circuit and a comparator. Current signals from a plurality of signal sources are output to the output line. The current mirror circuit is electrically connected to the output line. The comparator is configured to compare a mirrored current signal from the current mirror circuit with a reference current signal. The comparator is configured to output a signal representing a comparison result of amplitudes of the mirrored current signal and the reference current signal.

Abstract: A system includes a switching power supply, an electric load connected to the switching power supply, a voltage regulation circuit, and a detect device. The voltage regulation circuit is connected to the electric load and configured to output a Pulse Width Modulation (PWM) signal to regulate a voltage supplied to the electric load. The detect device is connected to the switching power supply for detecting whether the switching power supply is powered off when a current flowing to the electric load exceeds a preset tolerance value.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol interference, high-frequency loss, skew between the clock and data channels, and differential skew within a differential signal are compensated by analog circuits which are automatically tuned for best performance by observing the quality of the recovered analog signal. Oversampling is used to provide a 24-bit digital representation of the analog signal for determining the quality of the signal. A corresponding method of deskewing a differential signal and a system and circuit therefor are also provided.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: A differential signal driver includes a pre-driver configured to generate a constant charging current and a constant discharging current. A first capacitor of the pre-driver is charged with the charging current when a differential input signal has a first state, and discharged with the discharging current when the differential input signal has a second state, thereby developing a first output control voltage on the first capacitor. A second capacitor of the pre-driver is discharged with the discharging charging current when the differential input signal has the first state, and charged with the charging current when the differential input signal has the second state, thereby developing a second output control voltage on the second capacitor. An output driver circuit generates a differential output signal in response to the first and second output control voltages. The slew rate of the differential output signal is controlled by the charging and discharging currents.

Abstract: A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol interference, high-frequency loss, skew between the clock and data channels, and differential skew within a differential signal are compensated by analog circuits which are automatically tuned for best performance by observing the quality of the recovered analog signal. Oversampling is used to provide a 24-bit digital representation of the analog signal for determining the quality of the signal.

Abstract: As in a conventional technology, a hard clipping process and a filtering process are performed on a transmission signal. An original transmission signal is subtracted from a signal on which the processes have been performed, and an inverse sign signal to the suppressed signal is retrieved. By giving a gain to the signal, and adding up to the original transmission signal, a peak voltage is suppressed. The gain can be a ratio of a difference signal between a hard clipped signal and an original transmission signal to a signal of suppression of a filtered signal from the original transmission signal, or a value determined by a simulation depending on the cutoff frequency of a low pass filter used in the filtering process.

Abstract: A High-Definition Multimedia Interface (HDMI) cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves. Methods are provided for deskewing, equalizing, and boosting the differential signals in the embedded circuits that are mounted on a PCB.

Abstract: This invention relates to adjusting a filter of a time-continuous Sigma-Delta converter arranged to convert an analog input signal (Sin) to a digital output signal. A control signal indicative of a gain of the filter is provided, and the gain of the filter is adjusted in dependence of the control signal. The control signal is provided from the digital output signal of the Sigma-Delta converter. In this way the performance of the Sigma-Delta converter can be improved in a simple way that requires no or few additional analog components, and the Sigma-Delta converter itself is used to adjust its performance. Using a signal from the digital domain of the Sigma-Delta converter is advantageous in that it is typically easier, faster and more precise to process signals in the digital domain.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: The present invention is an automatic gain control system for use with a multiple wavelength laser LIDAR system that transmits sets of time-separated interrogating signals to generate sets of time-separated return signals. A comparator defines a plurality of unique peak amplitudes and a corresponding plurality of unique binary words associated therewith. The comparator receives each of the laser LIDAR system's return signal from an i-th set thereof and outputs a binary word indicative of a peak amplitude achieved thereby. The binary word is one of the plurality of unique binary words. A memory has each of a plurality of address locations defined by one of the plurality of unique binary words. Each address location stores a unique gain value. An adjustable gain amplifier has a signal input for receiving each return signal and a gain adjustment input coupled to the memory.

Abstract: A method and system for providing a voltage-sensing preamplifier for use with a magnetoresistive sensor is disclosed. The method includes providing a gain stage and providing a control circuit. The system includes the gain stage and the control circuit. The gain stage includes at least one input device that is coupled with the magnetoresistive sensor through an interconnect having a characteristic impedance. The at least one input device has a first input impedance. The control circuit provides at least one signal to the at least one input device. The at least one signal controls the first input impedance of the at least one input device to control a second input impedance of the voltage-sensing preamplifier, such that the preamplifier input impedance is modified toward the characteristic impedance of the interconnect to improve the bandwidth of the signal amplified by the system.

Abstract: A circuit and method implement a configurable clock generator comprising a logic circuit, a configurable matrix and a phase-locked loop. The logic circuit may be configured to generate a plurality of control signals. The configurable matrix may comprise a plurality of interconnections that may be configured to (i) receive the plurality of control signals from the logic circuit and (ii) bus the control signals to the phase-locked loop. The plurality of control signals may control the operation of the phase-locked loop. In one example, the logic circuit may comprise a sea of gates logic array.

Abstract: A current mirror type sense amplifier can prevent the lowering of gain when the input signal and the inverted input signal are swung around the power voltage level, and also stably performs the sensing & amplifying operation in wide range from low power voltage to high power voltage.

Abstract: A frequency gain display apparatus for an L/C band frequency up unit which is capable of generating a pulse for adjusting the gain of an L/C band frequency up unit used in a satellite system and a pulse for selecting a band width of a SAW (surface acoustic wave) filter and is capable of displaying a gain step of the same.

Abstract: A magnetic-field-to-voltage transducer includes a Hall element and a digitally gain-controlled Hall-voltage amplifier that produces an analog voltage Vsig having excursions of one polarity corresponding to the passing of magnetic articles. Vsig is applied to the input of a signal-manipulating circuit that generates a proximity- detector binary output voltage, Vout, having transitions of one direction each time a predetermined point is reached in Vsig. A digitally gain-controlled gain amplifier is connected to the Hall element. A comparator circuit generates a binary signal Vbig (or V.sub.toobig) that changes from one to another binary level each time that Vsig exceeds a DC target voltage, V.sub.TG.

Abstract: A gain control circuit according to the present invention comprises an amplifier circuit for controlling gain thereof to amplify an input signal and a control circuit. The amplifier circuit includes an input terminal for inputting the signal, a first transistor having a drain electrode connected to a first potential through a first resistive means and a source electrode connected to a second potential, and an output terminal connected to a first electrode and varies the value of a resistance between the source and drain of the first transistor based on the signal supplied to the input terminal. The control circuit is composed of a second transistor having a source electrode connected to the source of the first transistor, a drain electrode connected to the drain of the first transistor and a gate electrode supplied with a control signal and varies the value of a resistance therebetween based on the control signal supplied to the gate electrode.

Abstract: A peak detector for extracting pulses in a magnetoresistive sensor circuit while suppressing the recovery transients created by thermal asperities. The disclosed peak detector circuit is a simplified variation of the standard magnetoresistive sensor peak detector circuit. The signal differentiation is performed ahead of the usual amplification to remove transient pulse amplitudes before they can affect the AGC gain. The resulting differentiated signal is processed by a modified amplitude qualification circuit to extract data output pulses. The thermal asperity transient recovery period is eliminated without additional circuit complexity, leaving only the initial thermal asperity pulse effects to be corrected by any suitable relatively simple error correction code (ECC).

Abstract: An automatic gain and level control output circuit. The inventive circuit (10) includes a first component (12) for multiplying an input signal by a first reference signal to provide a gain adjusted signal. The input signal is level shifted by a second reference signal by a second component (16) to provide a level adjusted signal. The gain and level adjusted signals are compared to third and fourth reference signals by third and fourth components (26 and 28), respectively. The outputs of the third and fourth components (26 and 28) are combined to provide a first signal. Either the output of the third component (26) or the fourth component (28) is selected to provide a second signal having a first or a second level respectively. The first signal is integrated to provide the first reference signal and the fourth signal is integrated to provide the second reference signal.

Abstract: In an amplifier circuit with an offset cancel circuit, on the output side of a non-inversion amplifier circuit, there is connected a sampling circuit including an analog switch composed of two MOS transistors. A source-follower circuit is connected to the output terminal of the sampling circuit. The output voltage of the source-follower circuit is applied to a series resistance formed between two resistances. A connecting point between the resistances is connected to the inversion input terminal of an operational amplifier forming the non-inversion amplifier circuit and thus the divisional component of the output signal of the source-follower circuit is applied to the inversion input terminal of the operational amplifier.

Abstract: A device for restoring DC and non-zero average components of a serially transmitted binary signal which has been AC coupled. The device comprises an input port for the binary signal, a clamping circuit, a feedback network, a summing node, and an output port. The input port includes a capacitor for coupling the binary signal to the summing node and the clamping circuit. The feedback network includes an input and an output which are also connected to the summing node. The clamping circuit clamps the positive and negative peaks of the AC coupled binary signal which exceed a predetermined range. The feedback network latches the AC coupled binary signal and produces a current signal. For a binary signal which is within the predetermined range, the clamping circuit exhibits a very high input impedance, thereby causing the current signal to charge the coupling capacitor and produce a voltage which is added to the AC coupled binary signal at the summing node.