Abstract: A wireless charging in-band communication system includes a channel encoding for message error correction and detection. A modulation module performs biphase modulation for DC balanced signals and impedance switching to change reflected impedance seen by the source. A synchronization module prepends the message with a synchronization sequence having Golay complementary codes. A receiver module receives the message from the transmitter module. A preamble detection block has a Golay complementary code correlator used for message detection, synchronization, and equalization coefficient estimation and selection. A decoding module that performs biphase demodulation with error correction with a DC offset being estimated as the average value of the signal over the length of the message before channel decoding. The decoding module performs equalization, error correction and detection channel decoding.

Abstract: A frequency jittering control circuit includes a frequency jittering circuit, a feedback compensation circuit, a comparator and a control circuit. The frequency jittering circuit generates a frequency jittering signal. The feedback compensation circuit generates a feedback compensation signal in response to the frequency jittering signal and an output signal. The comparator outputs a comparison output signal according to the feedback compensation signal and an oscillation signal. The control circuit outputs a frequency jittering control signal for switching a main switch in a power supply apparatus, according to the comparison output signal, such that the power supply apparatus correspondingly generates the output signal.

Abstract: A differential microphone with improved biasing and a well defined common mode output voltage is connected to an amplifier that includes a differential amplifier stage and a common mode feedback circuit. The amplifier is in a feedback configuration.

Abstract: Disclosed herein are low-noise multi-output power supply circuits and methods. In one embodiment, a method of controlling a low-noise multi-output power supply circuit, can include: (i) detecting operation states of each of a plurality of switch mode power supplies; (ii) generating a frequency modulation signal to control an operating frequency of a switch mode power supply to be substantially equal to a main frequency signal when the switch mode power supply is detected to operate in a heavy-load steady state; and (iii) controlling the operating frequency of the switch mode power supply to be independent of the main frequency signal when the switch mode power supply is detected to operate in a light-load or a dynamic state.

Abstract: There is provided a test apparatus that is capable of applying, to a device under test, a current that rises within a short period. A test apparatus for testing a device under test, includes a current source that supplies the device under test with a current, a dummy load that has an electrical characteristic corresponding to an electrical characteristic of the device under test, and a switching section that switches whether the current source is connected to the dummy load or the device under test. Here, after connecting the current source to the dummy load, the switching section disconnects the current source from the dummy load and connects the current source to the device under test when a voltage applied to the dummy load reaches a voltage within a predetermined range.

Abstract: A receiver for decoding a communication signal is disclosed. The receiver includes an input port and a filter. The input port receives the communication signal from a communication medium. The communication signal comprises a sequence of symbols. Each symbol of the symbol sequence is an analog pulse that has a leading edge of exponential shape. The exponential shape has an exponential growth parameter value that has been selected from values ?0 and ?1, which are distinct positive values. For each symbol of the symbol sequence, the exponential growth parameter value for the leading edge of the symbol has been selected based on a corresponding bit from a stream of information bits. The filter receives the communication signal from the input port and filters the communication signal to obtain an output signal. The transfer function of the filter has one or more zeros at ?0.

Abstract: A method for controlling pulsed power that includes measuring a first pulse of power from a power amplifier to obtain data. The method also includes generating a first signal to adjust a second pulse of delivered power, the first signal correlated to the data to minimize a power difference between a power set point and a substantially stable portion of the second pulse. The method also includes generating a second signal to adjust the second pulse of delivered power, the second signal correlated to the data to minimize an amplitude difference between a peak of the second pulse and the substantially stable portion of the second pulse.

Abstract: A first transmitter transmits symbols. The leading edge of each symbol has the form Djexp{?jt}, where Dj is real, where ?j is selected from N possible values based on a current group of bits. The receiver has N filters whose transfer functions correspond respectively to the N possible values. The filter outputs are used to recover the group of bits. A second transmitter transmits an exponential symbol or a zero symbol depending on a current bit to be transmitted. The zero symbol has zero amplitude over the symbol period. The corresponding receiver applies threshold detection to estimate the transmitted bits. A third transmitter transmits a sequence of analog pulses with known interpulse time separation(s). The pulse sequence reflects from a moving object. A receiver captures the reflected pulse sequence. The interpulse separation(s) of the reflect pulse sequence is used to determine the radial velocity of the object.

Abstract: The present specification provides a method, apparatus and system for sensing a signal with automatic adjustments for changing signal levels. A novel fractional peak discriminator circuit is provided which can be incorporated into a system for measuring periodic signals from moving elements. The circuit can be used regardless of whether the periodic signals are detected using optics, magnetic detector or other methods.

Abstract: A control circuit configured to control a switching power supply including a ramp generator configured to generate a triangular waveform. A comparator is configured to generate a series of pulse width modulated (PWM) pulses at a first frequency and to regulate the switching power supply. The ramp generator includes a capacitor, a charging current source configured to provide a charging current to charge the capacitor, and a discharging current source configured to provide a discharging current to discharge the capacitor. The ramp generator also includes a closed loop current balancing current source configured to balance the currents from the charging and discharging current sources to establish a substantially zero direct current (DC) bias across the capacitor. The controller also includes a multi-phase configuration to provide a stackable multi-channel architecture.

Abstract: The present specification provides a method, apparatus and system for sensing a signal with automatic adjustments for changing signal levels. A novel fractional peak discriminator circuit is provided which can be incorporated into a system for measuring periodic signals from moving elements. The circuit can be used regardless of whether the periodic signals are detected using optics, magnetic detector or other methods.

Abstract: Recycling energy in a clock distribution network is provided. A circuit includes a clock driver associated with a clock signal and having an output connected to a first load capacitance. The circuit also includes a second load capacitance connected in parallel with the first load capacitance. The circuit further includes a power transfer circuit including an inductor and a transmission gate connected in series between the first load capacitance and the second load capacitance. The power transfer circuit controls a flow of energy between the first load capacitance and the second load capacitance based on the clock signal.

Abstract: A method for controlling pulsed power that includes measuring a first pulse of power from a power amplifier to obtain data. The method also includes generating a first signal to adjust a second pulse of delivered power, the first signal correlated to the data to minimize a power difference between a power set point and a substantially stable portion of the second pulse. The method also includes generating a second signal to adjust the second pulse of delivered power, the second signal correlated to the data to minimize an amplitude difference between a peak of the second pulse and the substantially stable portion of the second pulse.

Abstract: A data signal generation device comprising a microprocessor and a digital potential divider, in which the microprocessor is adapted to generate a square wave output signal, and in which the digital potential divider is adapted to receive said square wave output signal, and to ramp up and down an output signal voltage and/or current according to state transitions in said square wave output signal.

Abstract: Disclosed herein are SOC devices with peripheral units having power management logic.

Abstract: A buffer for converting sinusoidal waves to square waves with reduced phase noise is described herein. The buffer shunts current from the outputs of a differential amplifier during sinusoidal state transition periods at the differential amplifier inputs to increase the finite slope of square wave transition periods of the output square wave. More particularly, a sinusoidal wave having alternating peaks and valleys connected by sinusoidal state transition periods is applied to differential inputs of a differential amplifier to generate a square wave at the differential outputs, where the output square wave comprises alternating high and low states connected by square wave state transition periods having a finite slope. The output square wave is shaped to increase the finite slope of the square wave transition periods by providing additional paths between the differential outputs and ground that shunt current from the differential amplifier during the sinusoidal state transition periods.

Abstract: A zero-crossing gain control system is disclosed herein. The system comprises a gain control unit for amplifying an input signal to an output signal, a zero-crossing monitoring circuit for monitoring the input signal or output signal, and a register for latching the digital control signal and generating a gain control signal that controls the gain control unit. The system may further comprise a maximum write time setting circuit for generating a write signal. The digital control signal is written into the register when a zero-crossing state is monitored or a maximum write time since a change occurred on of the digital control signal is expired. An automatic gain control system is also disclosed herein and further comprises a peak detecting circuit for detecting the level of output signal, a logic circuit for lowering or restoring the digital control signal according to the result from the peak detecting circuit.

Abstract: A signal sampling circuit includes: a signal output unit configured to output a level signal to an output node in response to a control signal; a signal sampling unit coupled to the output node and configured to sample the level signal in a sampling period; a first current sinking unit configured to sink a constant current from the output node; and a second current sinking unit configured to sink a current from the output node after a time point where the control signal is deactivated.

Abstract: An electronic device according to one or more embodiments of the present invention comprises an output line, a current mirror circuit and a comparator. Current signals from a plurality of signal sources are output to the output line. The current mirror circuit is electrically connected to the output line. The comparator is configured to compare a mirrored current signal from the current mirror circuit with a reference current signal. The comparator is configured to output a signal representing a comparison result of amplitudes of the mirrored current signal and the reference current signal.

Abstract: A system and method for reducing power consumption within clock distribution on a semiconductor chip. A 4-phase clock generator within a clock distribution network provides 4 non-overlapping clock signals dependent upon a received input clock. A reduced voltage swing clock generator receives the non-overlapping clock signals and charges and discharges a second set of clock lines in a manner sequenced by the non-overlapping clock signals. The sequencing prevents a voltage range from reaching a magnitude equal to a power supply voltage for each of the second set of clock lines. In one embodiment, the magnitude reaches half of the power supply voltage. The reduced voltage swing latch receives the second set of clock lines. The reduced voltage swing latch updates and maintains logical state based at least upon the received second set of clock lines.

Abstract: A current reference generating circuit including a first multiplier module, configured to receive a rectified voltage waveform signal of a switch mode power supply and an output signal generated by an average current loop, and to generate a sinusoidal half-wave signal having the same frequency and phase as the rectified voltage waveform signal, the sinusoidal half-wave signal varies with the output signal generated by the average current loop. A second multiplier module, configured to receive the sinusoidal half-wave signal and a control signal to generate a pulse signal. An average current loop for comparing the average of the pulse signal to a predetermined average current loop reference signal. The circuit can generate a self-adapted reference signal that follows the primary-side current signal of main circuit of the switch mode power supply, which is then supplied to the constant current switch mode power supply control circuit with high power factor.

Abstract: A system includes a switching power supply, an electric load connected to the switching power supply, a voltage regulation circuit, and a detect device. The voltage regulation circuit is connected to the electric load and configured to output a Pulse Width Modulation (PWM) signal to regulate a voltage supplied to the electric load. The detect device is connected to the switching power supply for detecting whether the switching power supply is powered off when a current flowing to the electric load exceeds a preset tolerance value.

Abstract: A level formatter is provided that has differentially coupled closed loop current sources, each configured to precisely establish a current proportional to a reference voltage. A bridge circuit is differentially coupled to two supplementary current sources and controlled to rapidly switch the current from the supplementary current sources to produce output voltages at respective outputs that are approximately equal to respective one of two reference voltages.

Abstract: A signal generating circuit and method are disclosed that do not require a phase-locked-loop and a low frequency temperature-stable oscillator. The method may include generating an oscillating output signal responsive to a feedback signal, where the feedback signal controls a frequency of the oscillating output signal, generating a current output signal having a magnitude corresponding to the frequency of the oscillating output signal, and then comparing the current output signal to a reference signal to generate the feedback signal. The signal generating circuit may include an oscillator circuit responsive to a feedback signal and a frequency-to-current conversion circuit configured to generate a frequency dependent current signal that is compared to a reference current to generate an output signal corresponding to the frequency of the oscillating output signal. A feedback conversion circuit compares the output signal with a reference signal to generate the feedback signal to the oscillator circuit.

Abstract: The invention relates to a pulse width modulator, more particularly to a cross-coupled pulse width modulator. A crossing input signal modulator according to the present invention comprises: a positive path block which includes a first integrator for performing the first-order integration of feedback signals in first input and output signals and then transmitting the first-order integrated signals to a second integrator, and a second integrator for performing the second-order integration of a signal from the first integrator and a second input signal and then transmitting the second-order integrated signals; and a negative path block which includes a third integrator for performing the first-order integration of feedback signals in the second input and output signals and integration of a signal from the third integrator and the first input signal and then transmitting the second-order integrated signals.

Abstract: A periodic signal generating circuit which is dependent upon temperature for establishing a temperature independent refresh frequency is presented. The periodic signal generating circuit includes a reference voltage generating unit and a periodic signal generating unit. The reference voltage generating unit produces a reference voltage which exhibits a variable voltage level in response to temperature. The periodic signal generating unit produces a periodic signal in response to a set voltage to determine the reference voltage and an oscillation period, wherein a transition timing of the set voltage is controlled by the reference voltage. As a result the periodic signal has a relatively constant period which can be produced regardless of the temperature variation.

Abstract: Systems (400, 500, 600) and methods (300) for generating a chaotic amplitude modulated signal absent of cyclostationary features by preserving a constant variance. The methods involve: generating a PAM signal including pulse amplitude modulation having a periodically changing amplitude; generating a first part of a constant power envelope signal (FPCPES) by dividing the PAM signal by a square root of a magnitude of the PAM signal; generating a second part of the constant power envelope signal (SPCPES) having a magnitude equal to a square root of one minus the magnitude of the PAM signal; and generating first and second spreading sequences (FSS and SSS). The methods also involve combining the FPCPES with the FSS to generate a first product signal (FPS) and combining the SPCPES with the SSS to generate a second product signal (SPS). A constant power envelope signal is generated using the FPS and SPS.

Abstract: A digital pulse width modulation device includes a counter, a first comparator and a second comparator, wherein the first and second comparators are connected in parallel with each other and in series with the counter. The counter is capable of sending a count signal to the first and second comparators simultaneously, starting a count when the counter receives a clock signal, and transmitting the count signal to the first and second comparators. If the first comparator receives a pulse duty width signal, the count of the count signal will generate a pulse output of the corresponding duty cycle. If the second comparator receives a total pulse duty length signal and the count of the count signal reaches a number of the total length, a clear signal will be outputted to the counter to reset the counter to zero, so as to achieve the effect of correcting the output pulse.

Abstract: An embodiment of regulation and shaping circuit includes a first input terminal for receiving a first input signal with a first frequency; a second input terminal for receiving a second input signal with a second frequency higher than the first frequency; a first circuital branch coupled to the first input terminal and, through first coupling means active at the first frequency, to an output terminal for providing an output signal; a second circuital branch coupled to the second input terminal and to the output terminal, wherein said second circuital branch comprises a negative feedback circuital loop adapted to control the output signal according to the second input signal.

Abstract: A driver boost signaling circuit provides a pulse boost to the first cycle of an output pulse wave applied to an associated load. The circuit includes a signal generator circuit generating a signal including a series of pulses, a determining circuit determining a high impedance state of a signal load line and a first one or more cycles of the series of pulses applied to the load line following the high impedance condition, and a receiving circuit receiving a control signal. A logic circuit generates first and second logical signals responsive to the control signal and to the determining circuit determining the first one or more cycles and other cycles of the series of pulses.

Abstract: Disclosed herein are SOC devices with peripheral units having power management logic.

Abstract: A driver boost signaling circuit provides a pulse boost to the first cycle of an output pulse wave applied to an associated load. The circuit includes a signal generator circuit generating a signal including a series of pulses, a determining circuit determining a high impedance state of a signal load line and a first one or more cycles of the series of pulses applied to the load line following the high impedance condition, and a receiving circuit receiving a control signal. A logic circuit generates first and second logical signals responsive to the control signal and to the determining circuit determining the first one or more cycles and other cycles of the series of pulses.

Abstract: An integrated circuit device includes a first rectangular wave signal generation section that outputs a first rectangular wave signal when an amplitude of an oscillation signal inputted is greater than a first amplitude, and a second rectangular wave signal generation section that outputs a second rectangular wave signal when the amplitude of the oscillation signal is greater than a second amplitude that is greater than the first amplitude, and that controls the power supply voltage of an oscillation circuit by the first and second rectangular wave signals so as to maintain an appropriate potential difference with respect to a stop voltage against changes in the oscillation stop voltage associated with changes in a temperature condition.

Abstract: An electronic monitor for monitoring characteristics of an AC power line for swells, sags, RMS voltage, impulses, total harmonic distortion (THD) and frequency. The waveform is received at the monitor, scaled to a lower magnitude, rectified by an op amp with zero offset voltage, converted a digital form which is representative of the waveform and processed to determine the occurrence of any irregularity in the AC power waveform. Two DMA channels are used to store each cycle, or groups of cycles, of the waveform into two buffers for further processing. An input surge protective circuit limits impulse voltage to the power supply. Related methods are also disclosed.

Abstract: A power supply controller and method for improving the transient response of the power supply controller. The power supply controller includes a pulse width modulation control module connected to a feedback network. The feedback network is composed of an amplifier having an inverting input terminal, a non-inverting input terminal, and an output terminal. A compensation network is coupled between the inverting input terminal and the output terminal of the amplifier and a reference voltage is coupled to the non-inverting input terminal of the amplifier. A switch is coupled between the output terminal of the amplifier and an input terminal of the compensation network. The transient response of the controller is improved by operating the controller in a closed loop compensation configuration during a continuously pulsing operating mode and in an open loop compensation configuration during a pulse skip operating mode.

Abstract: A level formatter is provided that has differentially coupled closed loop current sources, each configured to precisely establish a current proportional to a reference voltage. A bridge circuit is differentially coupled to two supplementary current sources and controlled to rapidly switch the current from the supplementary current sources to produce output voltages at respective outputs that are approximately equal to respective ones of two reference voltages.

Abstract: A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.

Abstract: A voltage generation circuit comprises a voltage generation control unit configured to output one of a first voltage level determination signal having a fixed data value and a second voltage level determination signal having a varying data value in response to a selection signal, and a voltage generation unit configured to generate a voltage having a single pulse form or a voltage having a pulse form whose rising edge portion rises in incremental voltage steps in response to the voltage level determination signal outputted from the voltage generation control unit.

Abstract: Pulse width modulation (PWM) controllers and output stage driver circuits and related methods of communicating switching regulator mode information. The controller includes circuitry that recognizes intervals when the load driven by the regulator is in a low power mode. Responsive to recognizing the low power mode, the controller generates a PWM mode signal having at least three (3) different levels including at least one intermediate level that is coupled to at least one driver. Based on the PWM mode signal, the regulator is switched into a power saving low power operational mode.

Abstract: An actuator driving device includes: an actuator made of a shape metal alloy having a property that a predetermined shape is memorized in advance, and that the predetermined memorized shape is recovered when the actuator is heated to a predetermined temperature; an applier for applying, to the actuator, a pulse current or a pulse voltage at least having a predetermined current value or a predetermined voltage, and a predetermined duty ratio to heat the actuator; and a determiner for determining the current value or the voltage value, and the duty ratio of the pulse current or the pulse voltage to be applied to the actuator by the applier, wherein the determiner is operative to determine the pulse current or the pulse voltage having: the current value larger than a current value of a constant current required for displacing the actuator by a predetermined targeted displacement amount, or the voltage value corresponding thereto; and the duty ratio of making an applied current amount smaller than an applied curr

Abstract: A data signal generation device comprising a microprocessor and a digital potential divider, in which the microprocessor is adapted to generate a square wave output signal, and in which the digital potential divider is adapted to receive said square wave output signal, and to ramp up and down an output signal voltage and/or current according to state transitions in said square wave output signal.

Abstract: The present disclosure provides for a processor that can include digital processing circuitry that receives a digital clock signal from a supply regulated phase locked loop. The supply regulated phase locked loop can include a voltage controlled oscillator that can output an analog signal and a level restorer that can receive the analog signal from the voltage controlled oscillator and can translate the analog output into a digital signal that corresponds to an analog output of the voltage controlled oscillator. The supply regulated phase locked loop can receive an analog input having an input voltage that is within a range of acceptable input voltages. The supply regulated phase locked loop can also be configured to generate the digital output signal, such that the range of acceptable input voltages includes voltage values that are greater than and less than the output voltage.

Abstract: The invention discloses a signal converting device, and more particularly, to a signal converting device that improves the signal quality. The signal converting device comprises a first input end, a second input end, an output end, a first circuit and a second circuit. The first circuit is coupled between the first input end and the output end. The first circuit determines whether to charge up the output end to generate an output signal or not according to a first differential input signal. The second circuit is coupled between the second input end and the output end. The second circuit determines whether to discharge the output end to generate the output signal or not according to a second differential input signal.

Abstract: An electronic monitor for monitoring characteristics of an AC power line for swells, sags, RMS voltage, impulses, total harmonic distortion (THD) and frequency. The waveform is received at the monitor, scaled to a lower magnitude, rectified by an op amp with zero offset voltage, converted a digital form which is representative of the waveform and processed to determine the occurrence of any irregularity in the AC power waveform. Two DMA channels are used to store each cycle, or groups of cycles, of the waveform into two buffers for further processing. An input surge protective circuit limits impulse voltage to the power supply. Related methods are also disclosed.

Abstract: This patent pertains to a new technique of increasing the amount of energy absorbed by an antenna. It accomplishes this by broadcasting a spike that attracts the signal when the fields of its oscillating charge are at their strongest.

Abstract: At an occasion of a level transition when a second periodic voltage becomes equal to a main reference voltage a first periodic voltage generating circuit starts a first monotonically changing time-period in which a voltage value of a first periodic voltage increases monotonically from 0, which is an initial value, towards a voltage value of the main reference voltage. At an occasion of a level transition of a first main switching signal when the first periodic voltage becomes equal to the main reference voltage, a second periodic voltage generating circuit starts a second monotonically changing time-period in which a voltage value of the second periodic voltage increases monotonically from 0, which is an initial value, towards a voltage value of the main reference voltage.

Abstract: Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.

Abstract: A semiconductor integrated circuit includes a voltage supplying unit that supplies a first regulated voltage and a second regulated voltage by using a first reference voltage and a second reference voltage, respectively, and a clock buffer unit that supplies an output clock clocking within a range of the first regulated voltage and the second regulated voltage.

Abstract: A circuit for generating a square wave signal (UN2) comprising a DC voltage source (UG), a driver stage (TS), which alternately connects a control node (SK) to ground (GND) or the DC voltage (UG), a diode (D1) and a first capacitor (C1), which are coupled in series between a first pole (P1) of the DC voltage source and the control node (SK). The circuit further comprises an output stage (AS) comprising a first transistor (TR1) and a second transistor (TR2), which are connected such that the output stage (AS) the transistors are alternately conductive. The transistors (TR1, TR2) are coupled in series between a connecting node (N1), formed between the diode (D1) and the first capacitor (C1), and the control node (SK). A connecting node (N2) between the first transistor (TR1) and the second transistor (TR2) forms an output terminal for emitting the square wave signal.

Abstract: The present disclosure provides for a processor that can include digital processing circuitry that receives a digital clock signal from a supply regulated phase locked loop. The supply regulated phase locked loop can include a voltage controlled oscillator that can output an analog signal and a level restorer that can receive the analog signal from the voltage controlled oscillator and can translate the analog output into a digital signal that corresponds to an analog output of the voltage controlled oscillator. The supply regulated phase locked loop can receive an analog input having an input voltage that is within a range of acceptable input voltages. The supply regulated phase locked loop can also be configured to generate the digital output signal, such that the range of acceptable input voltages includes voltage values that are greater than and less than the output voltage.