Abstract: A method includes capturing a video of a plurality of drops being jetted through a nozzle of a printer. The method also includes measuring a signal proximate to the nozzle based at least partially upon the video. The method also includes determining one or more metrics that characterize a behavior of the drops based at least partially upon the signal.

Abstract: A strobe generation circuit includes: a main hybrid multiplexing circuit outputting a main pull-up signal and a main pull-down signal to first and second nodes, respectively, the main pull-up and pull-down signals being selectively controlled based on first pull-up and pull-down control signals generated by removing an input loading of main data; a sub hybrid multiplexing circuit outputting a sub pull-up signal and a sub pull-down signal to the first and second nodes, respectively, the sub pull-up and pull-down signals being selectively controlled based on second pull-up and pull-down control signals generated by removing an input loading of sub data; a latch circuit latching a signal of the first node and a signal of the second node to output a first latch signal and a second latch signal; and an output driver outputting a strobe signal according to the first and second latch signals.

Abstract: An electronic assembly including a plurality of electrically conductive elements separated by insulative material and a digital FM demodulator circuit coupled to some of the electrically conductive elements. The FM demodulator circuit having an FM detector circuit and a DC drift reducing circuit. The FM detector circuit has a detector input and a detector output that is the output of a comparator that is AC coupled to the rest of the FM detector circuit, the detector input receiving an input signal. The DC drift reducing circuit is electrically coupled to the detector output of the comparator, the DC drift reducing circuit detecting a DC drift of the detector output, the DC drift reducing circuit being additionally coupled to an input of the comparator, the DC drift reducing circuit substantially eliminating DC drift at the output of the FM demodulator circuit.

Abstract: In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.

Abstract: An amplification device (100) comprises an amplifier circuit (110) and a limiter (120). The amplifier circuit (110) comprises a signal input (111) for an input signal to be amplified and a first signal output (112) for a first output signal. The limiter (120) comprises a differential amplifier (125) comprising a first differential amplifier input (129) for a threshold control signal, a second differential amplifier input (113) for a feedback signal, and a differential amplifier output (124) for a threshold signal indicative of a difference between the threshold control signal and the feedback signal. The limiter (120) also comprises a first diode (121) having a first anode (122) coupled to the first signal output (112) and a first cathode (123) coupled to the differential amplifier output (124), and a feedback stage (128) coupled between the differential amplifier output (124) and the second differential amplifier input (113).

Abstract: A method and system for designing and implementing a finite impulse response (FIR) filter to create a plurality of output signals, each output signal having the same frequency but at a different phase shift from the other output(s), is described. Values are determined for the resistors, or other elements having impedance values, in a FIR filter having a plurality of outputs, such that each output has the same frequency response but a different phase than the other output(s). This is accomplished by the inclusion of a phase factor in the time domain calculation of the resistor values that does not change the response in the frequency domain. The phase shift is constant and independent of the frequency of the output signal.

Abstract: A control method for a data reception chip. The data reception chip includes a voltage generation module including a plurality of resistors and a selection unit. The resistors are connected in series with one another and divide an operation voltage to generate a plurality of divided voltages. The selection unit selects one of the divided voltages as a reference voltage according to a control signal. The control method includes controlling the selection unit to set the level of the reference voltage to an initial level; receiving data and comparing the data with the reference voltage to generate a compared result; determining whether the compared result is equal to pre-determined data; and directing the selection unit to select another divided voltage when the compared result is not equal to the pre-determined data.

Abstract: A voltage multiplier circuit. The voltage multiplier circuit includes a storage element, a first transistor, a second transistor and third transistor. The storage element has a first end and a second end. The second end is coupled to a clock signal input. The first transistor has a gate coupled to a voltage node, a first terminal coupled to a supply node, and a second terminal coupled to the first end of the storage element. A second transistor has a first terminal coupled to the first end of the storage element and a second terminal coupled to the voltage output. The third transistor has a gate in communication with the clock input and a first terminal coupled to the voltage node.

Abstract: A voltage mode transmitter includes a resistive network and a de-emphasis value controller. The resistive network receives plural input voltages and provides plural weighting values corresponding to respective input voltages. A sum of the products of the plural input voltages and the corresponding weighting values is equal to an output voltage. The de-emphasis value controller receives a first signal. After the first signal is inverted as an inverted first signal and the inverted first signal is delayed for a time period, the de-emphasis value controller generates a second signal. The de-emphasis value controller further receives a value control signal. At least one of the plural input signals is provided by the first signal and at least one of the plural input signals is provided by the second signal according to the value control signal.

Abstract: A system includes a capacitively-coupled touch sensor having a conductive first layer and a conductive second layer on a first insulative layer. The width of the second layer varies along an axis of the first layer. A first excitation signal is applied to one of the first and second layers and is capacitively coupled through a touch element to the other layer, producing a first signal that produces a second signal which is digitized. Digitized peak values of the second signal are processed to compute a value for a touch element location. A conductive third layer can be placed on the opposite side of the first layer has width varying oppositely to the second layer. The first excitation signal is applied to the second layer and a non-overlapping second excitation signal is applied to the third layer. The resulting digitized peak values are processed to cancel errors due to variations.

Abstract: A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.

Abstract: A high-speed current-mode clock driver includes feedback circuitry to maintain the voltage swing of a biasing node within a defined range. The current-mode clock driver includes a PMOS and an NMOS transistor receiving an oscillating signal at their gate terminals. The drain terminals of the PMOS and NMOS transistors are respectively coupled to input terminals of first and second variable conductivity circuits whose output terminals are coupled to a common node. A control circuit increases the conductivities of the first and second variable conductivity circuits in response to decreases in voltage swing of the common node, and decreases the conductivities of the first and second variable conductivity circuits in response to increases in voltage swing of the common node. The first and second variable conductivity circuits are optionally PMOS and NMOS transistors respectively.

Abstract: Aspects of the subject technology allow an output driver to be implemented using one or more transistors having an oxide-breakdown voltage below the output voltage swing of the output driver. The output driver can include one or more source followers, where a source follower provides voltage-level shifting of a voltage before the voltage is supplied to a gate of a transistor to prevent a source-to-gate voltage or a gate-to-source voltage of the transistor from exceeding the oxide-breakdown voltage of the transistor.

Abstract: In one aspect, a current driver, includes an operational amplifier that includes a first input port configured to receive a reference signal and a second input port configured to receive a variable signal. The variable signal is a function of an output current of the current driver. The reference signal corresponds to a selected maximum output current of the current driver. The current driver also includes a feedback transistor comprising a gate coupled to the output of the operational amplifier and a summing junction coupled to a drain of the feedback transistor and configured to receive a signal from the drain to enable clamping of the output current of the current driver to the maximum output current when the variable signal exceeds the reference signal. The summing junction is coupled to a set of transistors configured to provide the output current of the current driver.

Abstract: A power management device of a touchable control system includes a boost circuit boosting an output voltage according to an input voltage, a controlling signal for ballasting charging, and a controlling signal for boosting charging, a detection circuit detecting a predetermined value of the output voltage, a modulation circuit, and a loading circuit. The modulation circuit separately modulates the output voltage by the controlling signal for ballasting charging after the output voltage reaches the predetermined value and by the controlling signal for boosting charging before the output voltage reaches the predetermined value according to the detecting of the detection circuit. The loading circuit receives the reached predetermined value of the output voltage according to the modulation of the modulation circuit, wherein the controlling signal for boosting charging modulating the output voltage is more rapid than the controlling signal for ballasting charging modulating the output voltage.

Abstract: A limiter circuit in a voltage controlled oscillator (VCO) includes a first control circuit, a second control circuit and a driving circuit having a pull-up transistor and a pull-down transistor. The first control circuit generates a first driving control signal for controlling the pull-up transistor based on an AC input signal and a first DC bias voltage. The second control circuit generates a second driving control signal for controlling the pull-down transistor based on the AC input signal and a second DC bias voltage. The driving circuit generates an output signal based on the first driving control signal and the second driving control signal. The output signal swings between a first voltage at the pull-up transistor and a second voltage at the pull-down transistor.

Abstract: A gate driving circuit for driving a voltage-driven switching device is provided with a current limiting circuit for limiting a gate current ig that flows into a gate terminal through a gate resistor at turn-on to a current limit value IL which defines an upper limit value. The current limit value IL is set at a value which is larger than a gate current value I2 at turn-on of the switching device during a period when the Miller effect occurs but is smaller than a gate current value I1 at a point in time when a main current begins to flow at turn-on in a case where the gate current ig is not limited by the current limiting circuit. This arrangement makes a variation in a collector current of the switching device moderate at turn-on thereof when the collector current begins to flow, thereby reducing high-frequency noise.

Abstract: A switch circuit is disclosed. The switch circuit may include one or more arrangements of transistors coupled in a cascode configuration. The transistors used to implement the switch circuit may be configured for operation within a first range of voltages. The application in which the switch circuit may be implemented may require conveying signals within a second range of voltages that is greater than the first range of voltages. Thus, the switch circuit may include one or more additional transistors to ensure that a voltage drop between any two terminals of the transistors used in the switch circuit is within the first range of voltages.

Abstract: A system for processing an input signal, the system including: (a) a hardware memory module configured to store a lookup table; and (b) a signal processing module, configured to clip the input signal to provide a second signal that does not exceed a magnitude threshold, wherein the signal processing module is configured to clip the input signal by processing the input signal using at least one filtering parameter that is retrieved from the lookup table using at least one lookup table index which is selected in response to the input signal.

Abstract: A system includes a switching power supply, an electric load connected to the switching power supply, a voltage regulation circuit, and a detect device. The voltage regulation circuit is connected to the electric load and configured to output a Pulse Width Modulation (PWM) signal to regulate a voltage supplied to the electric load. The detect device is connected to the switching power supply for detecting whether the switching power supply is powered off when a current flowing to the electric load exceeds a preset tolerance value.

Abstract: An architecture for processing signal communications between a frequency translation module and an integrated receiver decoder. According to an exemplary embodiment, the signal processing apparatus comprises a demodulator for generating a first signal responsive to an FSK signal, said first signal comprising a varying amplitude and a clamping means for generating a second signal, wherein said second signal has a first value when the amplitude of the first signal is above a predetermined value, and wherein said second signal has a second value when the amplitude is below a second predetermined value.

Abstract: An electronic monitor for monitoring characteristics of an AC power line for swells, sags, RMS voltage, impulses, total harmonic distortion (THD) and frequency. The waveform is received at the monitor, scaled to a lower magnitude, rectified by an op amp with zero offset voltage, converted a digital form which is representative of the waveform and processed to determine the occurrence of any irregularity in the AC power waveform. Two DMA channels are used to store each cycle, or groups of cycles, of the waveform into two buffers for further processing. An input surge protective circuit limits impulse voltage to the power supply. Related methods are also disclosed.

Abstract: A switch circuit is disclosed. The switch circuit may include one or more arrangements of transistors coupled in a cascode configuration. The transistors used to implement the switch circuit may be configured for operation within a first range of voltages. The application in which the switch circuit may be implemented may require conveying signals within a second range of voltages that is greater than the first range of voltages. Thus, the switch circuit may include one or more additional transistors to ensure that a voltage drop between any two terminals of the transistors used in the switch circuit is within the first range of voltages.

Abstract: Embodiments of a potential converter circuit include a converter for converting a bipolar input signal to a unipolar output signal that only consumes current at a change of potential of the input signal.

Abstract: A transmitter includes: a limiter performing clipping in which an amplitude part at a level higher than an amplitude level based on a predetermined clipping level is clipped from an input signal, separating the input signal into an input signal after the clipping, which contains a predetermined out-of-band component, and a clip signal clipped from the input signal through the clipping, and outputting the input signal after the clipping and the clip signal; a high-pass filter subjecting the clip signal inputted from the limiter to high-pass filtering for blocking an in-band component contained in the clip signal while passing an out-of-band component contained in the clip signal, which is opposite in phase to the out-of-band component contained in the input signal after the clipping; an adder performing an addition process on the out-of-band component received from the high-pass filter and the input signal after the clipping received from the limiter; and an amplifier performing power amplification on a signal

Abstract: As in a conventional technology, a hard clipping process and a filtering process are performed on a transmission signal. An original transmission signal is subtracted from a signal on which the processes have been performed, and an inverse sign signal to the suppressed signal is retrieved. By giving a gain to the signal, and adding up to the original transmission signal, a peak voltage is suppressed. The gain can be a ratio of a difference signal between a hard clipped signal and an original transmission signal to a signal of suppression of a filtered signal from the original transmission signal, or a value determined by a simulation depending on the cutoff frequency of a low pass filter used in the filtering process.

Abstract: Embodiments of a potential converter circuit include a converter for converting a bipolar input signal to a unipolar output signal that only consumes current at a change of potential of the input signal.

Abstract: A circuit arrangement for switching a load includes at least one at least partially inductive load, at least one high side switch with a controlled path connected in series with the load and between supply terminals for a supply voltage. At least one freewheeling diode is connected with a first tap between the high side switch and the load. At least one clamp circuit is connected to a control terminal of the high side switch and is used to limit the control potential applied to the control terminal to a first pre-determined voltage value when the high side switch is switched off.

Abstract: A slew rate control circuit includes a receiver for receiving input signals and an output generator for generating output signals based on the input signals. The slew rate control circuit also includes an electrical interconnection coupling an output of the receiver and an input of the output generator. In addition, the slew rate control circuit includes a voltage clamp for clamping a voltage on the electrical interconnection between two known voltage reference levels. The voltage clamp may include a first current source for providing driving capacity to a driver circuit to prevent the voltage on the electrical interconnection from falling below one known voltage reference level. The voltage clamp may also include a second current source and a third current source for providing sinking capacity to the driver circuit to prevent the voltage on the electrical interconnection from rising above the other known voltage reference level.

Abstract: A circuit, system, and method is provided for regulating the pulse width and/or duty cycle of a signal indirectly or directly used to drive, e.g., a transmitter. The load of the transmitter can be, for example, an optical signal transmitter. The circuit includes a feedback loop that adjusts the output signal so that the lower voltages are chopped at a reference voltage input into the driver. The magnitude of the reference voltage will regulate the pulse width of the output signal, as well as the duty cycle of the output signal. A low input voltage swing is well-suited to be operated upon by the driver circuit to produce a symmetric pulse width that is particularly adapted to high-speed optical data communication applications. The gain and slew rate of the feedback circuit and, predominantly, the comparator and pull-down transistor of the feedback circuit is tuned to ensure the pull-down transistor is always on and, therefore, the comparator will toggle, but within constrained (i.e., regulated) voltage limits.

Abstract: A clipping circuit (20) for clipping an input signal to a level corresponding to a regulated power supply voltage (AVDD). The clipping circuit (20) includes a current mirror-like arrangement having a reference transistor (30) and a mirror transistor (32) The input signal (BDATA) is received at the drain of the mirror transistor (32), with the source of the mirror transistor (32) producing the output signal (CLPBDATA). The reference transistor (30) receives a bias current (IBIAS) that is mirrored by the mirror transistor (32) to limit the pull-up drive of the mirror transistor (32) in pulling up the output (CLPBDATA). Disclosed embodiments of the clipping circuit (20; 20′, 20″) include a current source (29) for producing a DC bias current (IBIAS), and a charge pump (34) for producing a transient bias current (IPUMP).

Abstract: A method and device for limiting peaks of an input signal. The device and method isolate peaks of an input signal based on a clipping threshold voltage, generate an extrema signal representing the local extrema of the peak isolated signal, filter the extrema signal based on an appropriate impulse filter response to generate a filter signal, and combine the filter signal with the input signal delayed by a predetermined time period to generate an impulse clipped signal. The impulse clipped signal has a reduced P/A ratio and is without significant out-of-band spectrum artifacts.

Abstract: An input signal voltage clamping circuit that provides asymmetrical, or unipolar, voltage clamping for an input signal terminal of a circuit. For a circuit having a positive power supply voltage relative to its ground, or reference, terminal and an input signal having positive and negative signal peaks, the input signal terminal voltage is clamped at positive and zero voltage levels. The input signal terminal voltage is clamped at a positive clamp voltage level which is intermediate to the power supply and ground potentials when the input signal voltage is greater than such positive clamp voltage. The input signal terminal voltage is clamped at a zero volt level when the input signal voltage is negative.

Abstract: A driver circuit and a receiver circuit. The driver circuit is coupled to drive two complementary signals and the receiver is coupled to receive the two complementary signals. The receiver circuit generates a reference voltage from the two complementary signals.

Abstract: A low power pulse amplifier with low duty cycle errors. The amplifier provides several differential amplifier stages with a biasing and canceling network. To minimize duty cycle errors for large input signals, cascode transistors are added between the drains of the differential amplifiers and the outputs. The result is an amplifier having a duty cycle error of less than 5% at amplitude input ranges from 5 millivolts to the supply voltage.

Abstract: An integrated circuit driver drives a differential signal over a communication cable, such as a twisted-pair cable. The integrated circuit driver includes a differential pre-driver that receives an input signal having an about 50% duty cycle and produces an amplified differential signal that swings between a power rail level and a ground level. A signal conditioner circuit receives the amplified differential signal and outputs a conditioned differential signal. The conditioned differential signal swings between the power rail level and an intermediate power level. The integrated circuit driver further includes an output driver that receives the conditioned differential signal that swings between the power rail level and the intermediate power level. The output driver produces a differential output signal that is communicated to the communication cable. The differential output signal has an about zero signal crossing and maintains the about fifty percent duty cycle.

Abstract: The present invention relates to a static and monolithic current limiter and circuit-breaker component including, between two terminals, a one-way conduction current limiter, a sensor of the voltage between the terminals, and a mechanism for inhibiting the conduction of the current limiter when the voltage sensed exceeds a given threshold.

Abstract: A driver for providing binary signals from a data system to a transmission line includes a data input node and an output transistor coupled between a data output node and ground. The output transistor has a gate, a source and a corresponding gate-source voltage therebetween. A first transistor is coupled to the gate of the output transistor and is responsive to signals applied to the input node. It conducts a discharge current from the gate of the output transistor for discharging the gate of the output transistor to reduce its gate-source voltage. A clamping circuit clamps the gate-source voltage of the output transistor to a first voltage level above ground to prevent the discharge current from reducing the, gate-source voltage of the output transistor to ground.

Abstract: An inductive load driver circuit with shared flyback protection includes a first transistor (209) which drives a first load (229), and a second transistor (231) drives a second load (251). A first clamp voltage steering diode (217) is coupled between an input terminal (207) of the first transistor (209) and a zener diode (203), and a second clamp voltage steering diode (239) coupled between an input terminal (233) of the second transistor (231) and the zener diode (203). A power supply terminal (201) is coupled to the zener diode (203).

Abstract: A digital base band section includes spread units for directly spreading input transmission data every channel by different spread codes to output spread signals, a summer for summing up the spread signals to output a multiplexed spread signal, a limiter for limiting an amplitude of the multiplexed spread signal not to exceed a predetermined value, and a roll-off filter limits a transmission spectrum by shaping a waveform of the transmission signal to output a digital base band signal to an analog base band/RF section, where it is converted into an analog base band signal by a digital-to-analog converter and a carrier is modulated to convert the analog base band signal into an RF signal in a modulator, which RF signal is amplified in a transmission power amplifier to transmit the amplified RF signal through a transmission antenna.

Abstract: An analog signal is sampled at sampling rates which are low relative to the highest frequency components of the analog signal. The digitized sample signals are processed and amplitude limited in a digital signal processor. Real and imaginary components for each data sample are determined. The magnitude of the complex phasor corresponding to the data sample is calculated using those real and imaginary components. If the calculated magnitude of the complex phasor exceeds a preset limit, then the sample is scaled by a suitable scaling factor, (i.e. the ratio of the preset limit to the actual calculated phasor magnitude) without changing the phase of the input sample. By operating at minimum sampling rates, digital signal processing resources are conserved while still reliably limiting the processed signal.

Abstract: A differential amplifier or delay cell for use in a voltage controlled oscillator comprises a pair of clipper transistors coupled across the output nodes of the amplifier for limiting the voltage swing of the output to a transistor threshold and improving the frequency response of the amplifier. A cross-coupled pair of transistors are included to provide a hysteresis response further improving the noise immunity of the amplifier. A variable control voltage is converted to a current and used to control the frequency of the output signal. An oscillator is formed from three stages, cascaded together, each stage comprising the improved differential amplifier and controlled by a differential reference signal.

Abstract: In a D.C. restoration circuit for a digital FM radio receiver, in which demodulated signals may be presented at the output of the demodulator as low-level differential signals superimposed on a variable D.C. level, the differential signal paths are capacitively coupled to the inputs of a comparator, and the voltage excursions at these inputs are clamped when the voltage between the inputs exceeds a predetermined value.

Abstract: Disclosed is a bus driver circuit that dynamically clamps the bus voltage for a predetermined period following a transition of the bus voltage, thereby reducing overshoot and ringing. The disclosed circuit dynamically clamps the initial overshoot at approximately the bus terminating voltage VT. The clamping is dynamic in that it is active for only a limited, prescribed period, which is adjustable. In a preferred embodiment, a driver receives an input signal (VIN) and provides an OUTPUT signal to a bus terminated with a terminating voltage (VT). A clamp circuit receives a CLAMP GATE signal and sinks current from the OUTPUT signal, thus reducing ringing and overshoot of the output signal. A delay circuit disables the clamp after a prescribed delay following a transition of the OUTPUT signal.

Abstract: AC voltage clipper for a MOS-circuit having two input terminals (In1, In2) receiving an ac supply voltage, wherein one input terminal (In1) is connected to a point of common voltage through a first MOS-transistor (MCL41) and the other input terminal (In2) is connected to said point of common voltage through a second MOS-transistor (MCL42). The gates of MOS-transistors (MCL41, MCL42) are connected to each other and receive a gate voltage (Vg4) of a control circuit (MCL2, MCL3, DCL11,DCL12), in such a way that both transistors (MCL41, MCL42) will conduct when the absolute value of the ac supply voltage, being applied as an input signal to the control circuit (MCL2, MCL3, DCL11, DCL12) exceeds a predetermined threshold value.

Abstract: An output buffer circuit has a pull-up output transistor controlled by a first node and a pull-down output transistor controlled by a second node. The first node is coupled to the second node through a switching stage controlled by feedback from the output terminal. When the output buffer circuit is switched between the high and low output states, the switching stage is initially on, switches off shortly after the potential of the output terminal begins to change, then switches on again when the output terminal reaches a certain intermediate potential.

Abstract: A device for restoring DC and non-zero average components of a serially transmitted binary signal which has been AC coupled. The device comprises an input port for the binary signal, a clamping circuit, a feedback network, a summing node, and an output port. The input port includes a capacitor for coupling the binary signal to the summing node and the clamping circuit. The feedback network includes an input and an output which are also connected to the summing node. The clamping circuit clamps the positive and negative peaks of the AC coupled binary signal which exceed a predetermined range. The feedback network latches the AC coupled binary signal and produces a current signal. For a binary signal which is within the predetermined range, the clamping circuit exhibits a very high input impedance, thereby causing the current signal to charge the coupling capacitor and produce a voltage which is added to the AC coupled binary signal at the summing node.