Abstract: A power converter is provided with a power semiconductor module having a switching element. The power converter includes a gate drive circuit, a first detection unit, a second detection unit, a time measuring unit, and an abnormality diagnostic unit. The gate drive circuit drives the switching element and outputs a feedback signal based on a switching operation of the switching element. The first detection unit detects a change in a feedback signal of an upper arm of the power converter. The second detection unit detects a change in a feedback signal of a lower arm of the power converter. The time measuring unit measures a difference between detection timings of a signal change by the first detection unit and a signal change by the second detection unit. The abnormality diagnostic unit performs diagnosis of the power converter based on a measurement result by the time measuring unit.

Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

Abstract: Techniques for duplex communication and power transfer across an isolator are provided. In an example, a first transceiver coupled to a first side of an isolator can include a transmit modulator configured to receive first data and timing signals, to provide control signals to oscillate an output of the transceiver to transmit power and to order each half-cycle of an oscillation cycle of the output to transmit the first data. A second transceiver coupled to a second side of the isolator can include a receive detection circuit configured to compare a received oscillation cycle with a plurality of thresholds and to provide a plurality of comparator outputs indicative of reception of the positive half-cycle and the negative half-cycle, and a receive decoder configured to identify the order of half-cycles and to provide an output indicative of logic level of the first data.

Abstract: A system and method of improving data link performance between two or more wireless data transceivers includes: clipping and inverting the data components of a communication signal which are calculated to cause non-linear saturation effects in the downstream power amplifier; delaying a first time series to align the first time series with the clipped and inverted data components of a second time series; adding the clipped and inverted data components of the second time series to the delayed first time series to obtain a modified composite waveform; creating a sacrificial band containing principal energy of the clipped and inverted data components of the second time series; combining the sacrificial band to the modified composite waveform in non-overlapping signal space to obtain an optimized composite waveform; and amplifying the optimized composite waveform with the downstream power amplifier of one or more of the two or more wireless data transceivers.

Abstract: To provide a motor control device capable of properly compensating the fluctuation in inverter output voltage during a dead time. The motor control device is for an inverter including switching elements composing upper and lower arms to convert a direct-current voltage to an alternating-current voltage and apply the alternating-current voltage to a motor thereby controlling a current of the motor to be a current target value, the motor control device including a dead time compensation unit that compensates fluctuation in inverter output voltage during a dead time with each switching between the upper and lower arms by a dead time compensation voltage, wherein the dead time compensation unit acquires an input parameter that determines a polarity of motor current during the dead time in a half-cycle of a fundamental wave of the motor current, and varies the dead time compensation voltage according to magnitude of the input parameter.

Abstract: An apparatus of a power amplifier is provided. The apparatus includes an input boosting circuit configured to match a second harmonic input signal using a harmonic control circuit of an input stage to maximize an efficiency and an output power, a die cell configured to receive and amplify an output signal of the input boosting circuit, and an output boosting circuit configured to receive an output signal of the die cell and to match a second harmonic output signal of the output signal of the die cell using a harmonic control circuit of an output stage to maximize the efficiency and the output power.

Abstract: Provided with one or more first transistors of a first conductivity type each including a gate, a source, and a drain, the gate being connected to an input terminal, the source being configured to be connected to a first voltage source, the drain being connected to an output node, one or more second transistors of a second conductivity type each including a gate, a source, and a drain, the gate being connected to the input terminal, the source being configured to be connected to a second voltage source, the drain being connected to the output node, a first resistor that is inserted and connected between the input terminal and the output node, a first output terminal that is connected to the input terminal, and a second output terminal that is directly or indirectly connected to the output node.

Abstract: A method for controlling pulsed power that includes measuring a first pulse of power from a power amplifier to obtain data. The method also includes generating a first signal to adjust a second pulse of delivered power, the first signal correlated to the data to minimize a power difference between a power set point and a substantially stable portion of the second pulse. The method also includes generating a second signal to adjust the second pulse of delivered power, the second signal correlated to the data to minimize an amplitude difference between a peak of the second pulse and the substantially stable portion of the second pulse.

Abstract: Pulse-generator circuits that permit independent control of pulse widths and the delays between successive pulses. In several embodiments, a pulse-generator subcircuit includes a transmission-line segment comprising first and second conductors, configured such that the first conductor is coupled to a first DC potential. The pulse-generator subcircuit further includes a terminating resistor coupled to a first end of the second conductor of the first transmission-line segment; this terminating resistor is matched to the characteristic impedance of the transmission-line segment. The pulse-generator subcircuit further includes first and second switches, controlled by first and second timing signals, respectively, and configured to selectively and independently connect respective first and second ends of the first conductor to a second DC potential.

Abstract: There is provided a signal generator outputting an analog frequency signal based on a digital value according to a set frequency, which provides excellent noise characteristics, requires no ROM table corresponding to waveform data, and has a simple configuration. A digital signal having a digital value according to a set frequency is integrated to generate a waveform in a sawtooth shape, a waveform in a triangular wave shape is generated based on the waveform, and this waveform output is differentiated and then D/A converted and integrated. A comparator using, for example, the voltage at a midpoint of the triangular wave as a threshold value is used for the integrated output, and a frequency signal of an objective frequency is obtained from the comparator.

Abstract: A circuit for providing an AC signal includes an amplifier having an input and an output. A sinusoidal signal is applicable at the input of the amplifier. The output of the amplifier is connected to the input via a lowpass filter or via a part of the lowpass filter.

Abstract: The disclosure relates to a method for the scheduling and/or the operation of a system of at least two power supplies (11) providing DC pulses to a consumer (5), typically an electrostatic precipitator, wherein the power supplies (11) are energised by a common feeding (1). According to the proposed method one power supply (11) is defined to be the reference power supply, and the initial pulses of each further power supply (11) are shifted by controlled delays (?Pri) with respect to the pulses of the reference power supply so as to fill the gaps between the pulses of the reference power supply by the pulses of the further power supplies (11).

Abstract: An AC electric motor, an inverter and a controller are mounted on an electric powered vehicle. The controller includes a voltage deviation calculating unit, a modulation factor calculating unit, and a mode switching determination unit. The voltage deviation calculating unit calculates a voltage deviation between a first voltage command when the rectangular wave voltage control is executed and a second voltage command when pulse width modulation control is executed, by inputting a current deviation to a voltage equation of the AC electric motor. Modulation factor calculating unit calculates the modulation factor based on the first voltage command and the voltage deviation. The mode switching determination unit determines whether or not control mode of the AC electric motor from the rectangular wave voltage control to the pulse width modulation control is necessary, based on the modulation factor.

Abstract: An input priority determination circuit is configured such that: (i) when a set signal S is asserted and a reset signal R is negated, an intermediate set signal S? is asserted and an intermediate reset signal R? is negated; (ii) when the set signal S is negated and the reset signal R is asserted, the intermediate set signal S? is negated, and the intermediate reset signal R? is asserted; (iii) when a control signal P indicates a set priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S? is asserted and the intermediate reset signal R? is negated; and (iv) when the control signal P indicates a reset priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S? is negated and the intermediate reset signal R? is asserted.

Abstract: A signal transmission device for transmitting a signal along a transmission path including a sinusoidal-signal transmitting unit configured to generate a sinusoidal signal that has a period the same as a period of a square-wave digital signal whose voltage level changes in correspondence with a logical value and that has a phase which differs based on change in the logical value of the square-wave digital signal, and configured to transmit the sinusoidal signal. The signal transmission device includes a sinusoidal-signal receiving unit configured to receive the sinusoidal signal, and configured to reproduce the square-wave digital signal from the sinusoidal signal based on change in the phase of the sinusoidal signal.

Abstract: A solid state imaging device includes: an AD conversion section having a comparing section, which receives a reference signal from a predetermined reference signal generating section and which compares the reference signal with an analog signal to be processed, and a counter section, which receives a count clock for AD conversion and performs a count operation on the basis of a comparison result of the comparing section, and acquiring digital data of the signal on the basis of output data of the counter section; a count operation period control section controlling an operation period of the counter section on the basis of the comparison result; and a driving control section controlling the reference signal generating section and the AD conversion section such that for the signal to be processed, data of upper N?M bits is acquired in first processing and data of lower M bits is acquired in second processing.

Abstract: A clock conditioning circuit including a phase detector circuit configured to provide an analog tuning signal indicative of a phase relationship between a reference clock to be conditioned and a generated clock. The controlled oscillator is configured to produce the generated clock, with the generated clock having an output frequency adjustable in response to an analog tuning signal applied to a control signal input of the controlled oscillator. Converter circuitry is provided to produce a digital representation of the analog tuning signal when the mode control circuitry is in a tracking mode. In the event the reference clock is lost, the mode control circuitry switches to a holdover mode so as to provide an analog holdover signal to the control signal input based upon the digital representations produced just prior to the loss of the reference clock.

Abstract: There is provided a signal generator outputting an analog frequency signal based on a digital value according to a set frequency, which provides excellent noise characteristics, requires no ROM table corresponding to waveform data, and has a simple configuration. A digital signal having a digital value according to a set frequency is integrated to generate a waveform in a sawtooth shape, a waveform in a triangular wave shape is generated based on the waveform, and this waveform output is differentiated and then DIA converted and integrated. A comparator using, for example, the voltage at a midpoint of the triangular wave as a threshold value is used for the integrated output, and a frequency signal of an objective frequency is obtained from the comparator.

Abstract: A circuit for providing an AC signal includes an amplifier having an input and an output. A sinusoidal signal is applicable at the input of the amplifier. The output of the amplifier is connected to the input via a lowpass filter or via a part of the lowpass filter.

Abstract: An input priority determination circuit is configured such that: (i) when a set signal S is asserted and a reset signal R is negated, an intermediate set signal S? is asserted and an intermediate reset signal R? is negated; (ii) when the set signal S is negated and the reset signal R is asserted, the intermediate set signal S? is negated, and the intermediate reset signal R? is asserted; (iii) when a control signal P indicates a set priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S? is asserted and the intermediate reset signal R? is negated; and (iv) when the control signal P indicates a reset priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S? is negated and the intermediate reset signal R? is asserted.

Abstract: A system is provided for generating a plurality of different voltage level clock signals. The system comprises an electrical energy storage pack having a plurality of series coupled electrical energy storage cells that provide a plurality of different output voltage level, a reference oscillator that provides a reference clock signal and a plurality of voltage clamps that receive the plurality of different output voltage levels and output the plurality of different voltage level clock signals at respective output nodes. The plurality of voltage clamps are configured to clamp each of a given output node to a respective high-side voltage level in response to pulling up of the given output node toward a respective high output voltage level and to clamp each of the given output node to a respective low-side voltage level in response to pulling down of the output node toward a low output voltage level.

Abstract: An impulse waveform generating apparatus comprises an oscillator for generating a reference signal having a center frequency in a frequency band of an impulse to generate, a timing matching circuit for shifting a phase of the reference signal by 90 degrees, a frequency demultiplier for dividing a frequency of the phase shift signal and obtaining a timing signal having a frequency component having a frequency width of an impulse to generate, a memory storing a waveform shape table, a waveform forming section for forming a waveform in synchronism with the timing signal, according to information of a shape table having a predetermined waveform, a low-pass filter for obtaining an envelope signal from an output signal of the waveform forming section, and a waveform generating section for changing an amplitude of the reference signal according to a value of the envelope signal.

Abstract: Eight or more transition points are generated during a given period, and are used in tracking movement of an interferometer reflector. Duty cycles of generated square waves are used to establish precise intervals between the transition points, and precise wave-phase relationships.

Abstract: A system is disclosed for generating a rectangular pulse with a transmission line, the pulse having a duration of twice the electrical length of the line and a voltage of up to twice the charge voltage. The system includes a voltage source, a switching means, and an output circuit. The voltage source is for providing a voltage potential to a first conductor of a transmission line. The switching means is for controllable coupling the first conductor of the transmission line to a second conductor of the transmission line at a first end of the transmission line, with the second conductor of the transmission line being coupled to a fixed voltage potential at a second end of the transmission line. The output circuit is coupled to the first conductor of the transmission line for providing an output pulse to a load.

Abstract: Clock generation circuitry is arranged in stages so as to convert a slow slew rate input signal into a high slew rate clock signal in a low power environment. Each stage includes a capacitor and an inverter, both fed by respective current mirrors. The capacitor is trickle-charged through its current mirror, and charge of the capacitor is dumped onto an output of the stage at a controlled timing. Two or more such stages may be provided, so as to improve the slew rate of both of the leading and trailing edges of the clock signal, and also so as to provide a convenient source of timing for dumping charge of each capacitor. Each stage might also include a diode switchably connected across the capacitor, so as to discharge the capacitor at appropriate timings, to reduce interference on succeeding stages that might otherwise be caused by residual charge on the capacitor.

Abstract: A signal transmission device for transmitting a signal along a transmission path including a sinusoidal-signal transmitting unit configured to generate a sinusoidal signal that has a period the same as a period of a square-wave digital signal whose voltage level changes in correspondence with a logical value and that has a phase which differs based on change in the logical value of the square-wave digital signal, and configured to transmit the sinusoidal signal. The signal transmission device includes a sinusoidal-signal receiving unit configured to receive the sinusoidal signal, and configured to reproduce the square-wave digital signal from the sinusoidal signal based on change in the phase of the sinusoidal signal.

Abstract: Disclosed are various embodiments of interpolation circuits for use in conjunction with motion encoders. The analog output signals provided by incremental or absolute motion encoders are provided to an interpolation circuit, which is capable of providing high interpolation factor output signals having high timing accuracy. Problems with noise spikes common to zero-hysteresis comparators typically employed in interpolation circuits are eliminated, as are problems with time delays differing between comparators that do feature hysteresis. The disclosed interpolation circuits may be implemented using CMOS processes without undue effort.

Abstract: Eight or more transition points are generated during a given period, and are used in tracking movement of an interferometer reflector. Duty cycles of generated square waves are used to establish precise intervals between the transition points, and precise wave-phase relationships.

Abstract: A reference clock generator includes an oscillator to generate a periodic signal, a shaping circuit and a filter. The shaping circuit shapes the periodic signal to generate a clock signal. The filter is located between the oscillator and the shaping circuit.

Abstract: An electronic monitor for monitoring characteristics of an AC power line for swells, sags, RMS voltage, impulses, total harmonic distortion (THD) and frequency. The waveform is received at the monitor, scaled to a lower magnitude, rectified by an op amp with zero offset voltage, converted a digital form which is representative of the waveform and processed to determine the occurrence of any irregularity in the AC power waveform. Two DMA channels are used to store each cycle, or groups of cycles, of the waveform into two buffers for further processing. An input surge protective circuit limits impulse voltage to the power supply. Related methods are also disclosed.

Abstract: Eight or more transition points are generated during a given period, and are used in tracking movement of an interferometer reflector. Duty cycles of generated square waves are used to establish precise intervals between the transition points, and precise wave-phase relationships.

Abstract: A high voltage, fast pulse rise/fall time, and high repetition rate pulse generator solves the high pulse repetition rate limitations associated with RF power amplifiers and gap switch type pulse generators. The pulse generator employs a transmission line architecture and structural techniques that allow for continued high voltage, fast rise/fall time, and high repetition pulse rate operation of the pulse generator without impairment of the pulse generator while exceeding performance characteristics achievable with conventional RF power amplifiers and gap switch type pulse generators.

Abstract: A frequency adjusting circuit for a central processing unit (CPU) includes a transforming unit for transforming a change of a current signal of the CPU into a voltage signal, an amplifying unit for amplifying the voltage signal from the transforming unit, a switching unit being turned on or turned off by the amplified voltage signal from the amplifying unit, and a basic input/output chip for regulating a frequency of the CPU through a clock generator.

Abstract: The invention relates to a method of forming a reference pulse Ir from three signals, SIN, COS and REF, in which: the REF signal is compared with a threshold value such as to form a digital signal S1 comprising windows F having a width that is a function of the half period of signal REF; and signals SIN and COS are compared in order to form a digital signal S2 comprising, for each period, a pulse I and a combination of the pre-formed digital signals (S1, S2) such as to discriminate the reference pulse Ir. The invention also relates to a device for determining a reference state of an element that is rotating in relation to a fixed structure, comprising a treatment device that can perform one such method.

Abstract: An analog, duty cycle replicating frequency converter extracts duty cycle information from an input, pulse width modulated signal and generates an output pulse width modulated signal of the same duty cycle at a different frequency without regard to the frequency of the input signal. It uses bipolar transistor based circuitry, adaptable to an application specific integrated circuit, to derive voltages representing the on-time and period durations of the input signal, convert these voltages to currents representing the logarithms thereof, generate a voltage representing the difference between the currents, exponentially convert the voltage to a current representing the duty cycle and control an oscillator to generate an output pulse width modulated signal at a predetermined frequency with the duty cycle of the input signal.

Abstract: Provided is a control technique of a PWM conversion type power converter capable of compensating for a voltage error due to voltage drop mainly at a switching element and managing a switching time of a PWM signal at the same time, and capable of suppressing increase/decrease of software operation load and addition of a hardware circuit to the minimum. A semiconductor integrated circuit having a PWM signal generating unit which generates a PWM signal is provided with a PWM timer unit including a counter counting a pulse width of a pulse signal inputted from the outside with delay from a PWM signal, a register loading a counter value of the counter in synchronization with the PWM signal, and an A/D converting unit converting an analog signal serving as a source signal of the pulse signal inputted from the outside to a digital signal.

Abstract: Eight or more transition points are generated during a given period, and are used in tracking movement of an interferometer reflector. Duty cycles of generated square waves are used to establish precise intervals between the transition points, and precise wave-phase relationships.

Abstract: A reference clock generator includes an oscillator to generate a periodic signal, a shaping circuit and a filter. The shaping circuit shapes the periodic signal to generate a clock signal. The filter is located between the oscillator and the shaping circuit.

Abstract: Determining a slew rate of a signal from an integrated circuit under test by comparing the signal with a first reference voltage, comparing the signal with a second reference voltage different from the first reference voltage, generating an output pulse having a pulse width indicative of a slew rate of the signal, and integrating the output pulse over time to generate an output voltage proportional to the pulse width; wherein the output voltage is indicative of the slew rate of the signal produced by the integrated circuit.

Abstract: A pulse frequency modulation (PFM) controller for controlling a switching mode power supply. The controller includes an output terminal for providing a control signal to turn on and off a current in the power supply to regulate an output of the power supply. A first input terminal receives a feedback signal related to the output of the power supply, the feedback signal exhibiting a ringing waveform when the current in the power supply is turned off. The controller also includes a control circuit configured to provide the control signal in response to the feedback signal. The control signal is adapted to turn on the current in the power supply when the feedback signal is substantially at a valley of the ringing waveform of the feedback signal. In an embodiment, such a PFM controller can reduce turn-on transition loss in a power supply and provides frequency dithering to reduce electromagnetic interference.

Abstract: Eight or more transition points are generated during a given period, and are used in tracking movement of an interferometer reflector. Duty cycles of generated square waves are used to establish precise intervals between the transition points, and precise wave-phase relationships.

Abstract: A pulse generating circuit and related method, for producing extremely narrow pulses for use in monolithic microwave integrated circuits (MMICs) for radar, high-speed sampling, pulse radio and other applications. A sinusoidal input signal is supplied to two nonlinear shock wave generators, which are oppositely biased to produce periodic outputs that are mirror images of each other, one with a very steep rising edge and one with a very steep falling edge. The combined outputs would cancel each other completely but for the introduction of a slight time delay in one of them, which results in a narrow peak in the combined signals.

Abstract: An AC power source controller includes an input side, which is electrically connected to an output side via a power source controlling interface; and a phase modulator, which is electrically connected to the power source controlling interface. The phase modulator includes a microcontroller unit, an encoding DIP switch, a control signal receiving module, and a signal detecting interface, which may accurately detect the phase variation of an input power source so that, according to chosen conducting phase Pn, the microcontroller unit may automatically adjust the time delay Dn between conducting and cutting off orders sent to the power source control interface to control the power source output accurately, whereby the inaccuracy and instability of AC power source output control and phase difference between current and voltage generated by reactance load may be improved.

Abstract: A sinusoidal signal generating circuit for ensuring a small phase difference with respect to a reference signal is provided. The sinusoidal signal generating circuit comprises a capacitor for charging/discharging, a charging unit for charging a predetermined current to the capacitor, and a discharging unit for discharging a current therefrom, whereby an output signal is produced by the change in the potential of the capacitor, wherein the charging unit comprises a charging current adjusting unit for adjusting the magnitude of the charging current, and the discharging unit comprises a discharging current adjusting unit for adjusting the magnitude of the discharging current, and a control signal generating means is provided for supplying a plurality of control signals to the charging current adjusting unit and the discharging current adjusting unit in such a manner that the potential of the capacitor is changed into a sinusoidal waveform.

Abstract: A voltage-controlled oscillator circuit includes a ring oscillator circuit for generating a signal having a series of pulses. The signal with the series of pulses is ac coupled to a filter circuit which converts the series of pulses into a substantially sinusoidal signal which is substantially symmetrical about the reference potential of the system. The sinusoidal signal is applied to an amplifier which converts the sinusoidal signal into a square wave. Because the square wave is generated as an amplified sine wave, it exhibits a high degree of symmetry, i.e., it has a highly accurate 50-50 duty cycle, which makes it applicable in demanding settings such as serving as a clock signal in a high-speed microprocessor system in which both rising and falling edges of the clock signal are used to synchronize events.

Abstract: A diode detection circuit is capable of obtaining an ideal rectification voltage even the case of a minute input high-frequency voltage. The circuit includes a first diode that accepts an AC signal; a first parallel circuit consisting of a resistor and a capacitor, the first parallel circuit accepting a detection output from the first diode; a first operational amplifier having a positive input terminal that accepts a charging voltage for the capacitor of the first parallel circuit; a second diode that accepts an output from the first operational amplifier; a first switching circuit consisting of a first switch and an oscillator, the first switching circuit providing a control of the ratio of conduction to non-conduction of the first and second diodes; a second parallel circuit consisting of a resistor and a capacitor, the second parallel circuit accepting an output from the first switching circuit.

Abstract: A signal deciding apparatus which can obtain a stable digital signal OUT irrespective of an amplitude and a duty ratio of an input signal IN is provided. The input signal IN is amplified by inverters (51 to 53 and 8) and outputted as a digital signal OUT. A signal (S5) on the input side of the inverter (8) is integrated by a time constant which is equal to a data period of the input signal IN by an integrator (9) and supplied to a differential amplifier (20). A signal (S8) on the output side of the inverter (8) is integrated by a large time constant by an integrator (10), a control voltage VC supplied from a control terminal (13) is multiplexed to the integrated signal S8, and a resultant signal is sent to the differential amplifier (20). An output signal of the differential amplifier (20) is integrated by a resistor (11) and a capacitor (4) and its average level is fed back as a threshold voltage to the input side of the inverter (51) through a resistor (3) and multiplexed to the input signal IN.

Abstract: In a pulse generator, a sawtooth-shaped wave generator circuit generates a sawtooth-shaped wave by charging and discharging a capacitor. The sawtooth-shaped wave is fed to a comparator that performs pulse-width modulation on it in accordance with the voltage it receives via a terminal and thereby produces pulses. The comparator has its output grounded through a transistor that is turned on with appropriate timing by the sawtooth-shaped wave generator circuit. Thus, the maximum duty factor of the output pulses is made equal to the duty factor of the sawtooth-shaped wave.

Abstract: A clock generation system generates and distributes sinusoidal signals. Also, the clock lines are configured and shielded in a novel manner so as to provide the same overall propagation characteristics for the clock signals in all the lines, and to minimize the effects of cross-talk and electromagnetic interference.

Abstract: In a pulse generator, a sawtooth-shaped wave generator circuit generates a sawtooth-shaped wave by charging and discharging a capacitor. The sawtooth-shaped wave is fed to a comparator that performs pulse-width modulation on it in accordance with the voltage it receives via a terminal and thereby produces pulses. The comparator has its output grounded through a transistor that is turned on with appropriate timing by the sawtooth-shaped wave generator circuit. Thus, the maximum duty factor of the output pulses is made equal to the duty factor of the sawtooth-shaped wave.