Abstract: The present invention is directed to a method and apparatus for producing a square wave output signal with a clock circuit that possesses characteristics of low current consumption, relatively tight duty cycle control, and versatility over a wide range of voltages and input signal frequencies down to, and including DC. Exemplary embodiments receive an input signal, and process the input signal into an output square wave signal. A processing of the input signal is achieved using at least one current mirror for controlling a duty cycle of the output square wave signal said at least one current mirror being implemented in part with at least one pair of cascoded transistors. The processing is further achieved with an output stage having at least one inverter operatively connected with a node between the transistors of the at least one pair of cascoded transistors to control switching of the at least one pair of cascoded transistors.

Abstract: An analog-signal to square-wave-signal reshaping system for threshold-dependent reshaping of an analog input signal to a square wave signal; comprising an offset-inflicted reshaping circuit having a signal input adapted to be fed with the analog input signal, a reference input adapted to be fed with a reference voltage determining the reshaping threshold, and a signal output from which the square wave signal is available; an offset storage circuit connected to the signal input of the reshaping circuit and adapted to store a charging voltage corresponding to the offset voltage of the reshaping circuit, with this charging voltage being adapted to be superimposed on the analog input signal for offset compensation; a controllable switch circuit which in a first switching state takes no influence on the reshaping function of the reshaping circuit and, for the purpose of offset compensation, in a second switching state interrupts the reshaping operation of reshaping circuit and effects charging of the offset storag

Abstract: A phase detector provides a digital output having a linear relationship to the phase difference between a reference signal and an applied input signal. The phase detector counts the number of cycles of the reference signal within a time interval determined by the difference in arrival times of corresponding amplitude transitions of the reference signal and the input signal. A digital output representing the number of counted cycles is produced. A dither generator adds random time variation to the time interval over which the reference signal cycles are counted to introduce a corresponding random variation in the digital output.

Abstract: A trigger circuit is composed of a frequency multiplying portion which receives an electric signal to be measured and multiplies its repetitive frequency so as to output a multiple signal, a comparing portion which receives this multiple signal and outputs a square wave signal corresponding to its value, and a dividing portion which divides the square wave signal so as to output a trigger signal. Accordingly, even when a noise component is superposed on the electric signal to be measured, a trigger signal having little jitter and a repetitive frequency lower than that of the electric signal to be measured is output. Also, the electric field measuring apparatus in accordance with the present invention comprises this trigger circuit and measures, with a highly accurate timing, the electric field of the object to be measured.

Abstract: A circuit for generating a time base signal from a power line signal produced by an alternating current (AC) power source. The circuit sets the output of a latch to a first state when a positive peak of the power line signal is detected, and sets the output of the latch to a second state when a negative peak is detected. Peaks are detected based upon comparisons between the power line signal and a reference voltage. A reference circuit derives the reference voltage from the power line signal using an AC-to-DC converter to generate a peak voltage signal from the power line signal and a reference generator to generate a reference voltage based upon the peak voltage signal. Positive and negative peaks are detected using positive and negative peak detectors.

Abstract: An RF power amplifier includes an input-side tertiary harmonic wave control circuit and an output-side tertiary harmonic wave control circuit, respectively connected to a gate and a drain of a signal amplification FET. The RF power amplifier also includes a tertiary harmonic wave feedback circuit connected in parallel with the signal amplification FET. The tertiary harmonic wave feedback circuit includes an input-side tertiary harmonic wave bandpass filter, a tertiary harmonic wave amplification FET, a phase shifter and an output-side tertiary harmonic wave bandpass filter. These circuit elements are connected in series. Due to such a configuration, a voltage waveform and a current waveform each having a nearly rectangular shape can be easily generated at an output terminal (a drain) of the signal amplification FET, not only in the region around the efficiency saturation point whore the FET operates in a non-linear mode, but also in other linear-operation regions.

Abstract: A clock signal is distributed over a circuit board and across a connector as a sine wave. A circuit located near the clocked circuitry converts the sine wave into a same frequency square wave for use by the clocked circuitry. The output stage of the converter circuitry provides a high output level to drive CMOS circuitry. The output transistor is pulled up to 5 volts, but the preceding transistors are pulled up to 6.3 volts so that the base to emitter drops are compensated.

Abstract: A wave-shaping circuit is provided which converts an input alternating signal into a pulse signal. The wave-shaping circuit includes a level-adjusting circuit which is designed to integrate the input alternating signal to determine a central level of amplitude thereof for adjusting the central level to a given reference level under feedback control. This compensates for the variation in central level of amplitude of the input alternating signal caused by various noise components contained therein.

Abstract: A system for generating two or more frequencies for a borehole heterodyne measurement system for use in measuring electromagnetic propagation properties of rock is disclosed. A precision clock oscillator supplies a binary counter with clock signals. The output of the binary counter is supplied as address information to one or more pre-programmed ROMs. The ROMs are used to store multiple cycles of desired output signals. Output signals from the counter may also be supplied as square wave local oscillator signals in the system.

Abstract: An impedance-steerable circuit for an industrial phase controller inserts precise steerable trigger pulses in the sine and cosine excursions of a sine wave of high-energy capacitive and related discharge systems. Multiple pulses and Barkhausen effects are eliminated. The controller can lock capacitive discharge systems into precise phase or, in extended embodiments, serve as a power controller for radar systems, laser systems, and beam weapons. Thyristors and thyratrons provide steered elements (pulses) activated in a pulse-feedback mode.

Abstract: An integrating circuit includes first and second amplifiers for use during a zero-integrate mode and a X10 mode, respectively. The first amplifier is a low gain amplifier to ensure stability, whereas the second amplifier is a high gain amplifier to improve accuracy. During the zero-integrate mode, switches couple an integrator input lead to the first amplifier output lead and decouple it from the second amplifier output lead. During the X10 mode, the switches decouple the integrator input lead from the first amplifier output lead and couple it to the second amplifier output lead.

Abstract: AC voltage clipper for a MOS-circuit having two input terminals (In1, In2) receiving an ac supply voltage, wherein one input terminal (In1) is connected to a point of common voltage through a first MOS-transistor (MCL41) and the other input terminal (In2) is connected to said point of common voltage through a second MOS-transistor (MCL42). The gates of MOS-transistors (MCL41, MCL42) are connected to each other and receive a gate voltage (Vg4) of a control circuit (MCL2, MCL3, DCL11,DCL12), in such a way that both transistors (MCL41, MCL42) will conduct when the absolute value of the ac supply voltage, being applied as an input signal to the control circuit (MCL2, MCL3, DCL11, DCL12) exceeds a predetermined threshold value.

Abstract: An up/down counter within a phase locked loop is gated to count high frequency clock pulses during the first cycle of the input signal. Upon detection of a transition in the input signal indicating the end of the first cycle, the direction of the count is reversed until the count is reduced to zero, thereby assuring equal widths for the first and second half cycles of each output cycle. The system may be implemented with or without a voltage controlled oscillator. In the latter implementation, the count in the up/down counter at the time of a reversal in the count direction is compared with the count in a preset counter. A difference counter compares the differences in a count in the two counters and adjusts the count in the preset counter to match that in the up/down counter at the time of transition. The widths of the successive cycles, rather than half cycles, may be made by doubling the output frequency relative to the input frequency.

Abstract: A glitch trigger circuit for measuring glitches that appear on power line signals includes two comparators and two independently controllable voltage trigger levels to allow proper trigger on glitches of unknown polarity. A high pass filter rejects the power line signal while passing the glitch signals to provide triggering on glitches with voltage amplitudes less than the voltage amplitude of the power line signal.

Abstract: A full wave rectifier includes an amplifier having a minus input, a plus input and an amplifier output; an input resistor connected between a circuit input and the minus input; and a current bridge having an output terminal connected to the circuit output, a first terminal connected to the minus input and a second terminal connected to the amplifier output. The current bridge includes a first current mirror circuit and a second current mirror circuit. The first current mirror circuit includes a first current source and a second current source, a source end of each current source of the first and second current sources being connected to the first terminal, a drain end of the first current source being connected to the second terminal and a drain end of the second current source being connected to the output terminal.

Abstract: A data slice circuit is provided for slicing the caption data or the likes included in a television signal at an optimum voltage. A product between a clock-run signal sliced by a comparator at a tentative reference voltage and a clock signal which is 16 times the clock-run signal is stored in a shift register as 16 bit information, and out of them, only the 8 bits around its center are taken in a duty-factor check block, thereby judging the suitability of the slice level. Based on the result obtained, the value of the counter is increased or decreased, and it is taken as a renewed reference voltage through a pulse width conversion circuit and an integration circuit. Also with data sliced by a renewed reference voltage, the check is executed similarly, and a slicing action at an optimum level is achieved.

Abstract: Peak and valley voltages of signals from at least two analog sensors are held by the circuit. A plurality of threshold voltages is generated from the previous peak and valley voltages of the respective analog sensors. The signal of each sensor is compared to the respective threshold voltages to produce a sequences of output transitions for each sensor. The output transitions are combined such that each sequence of output transitions from each analog sensor occurs between sequences of the other analog sensor (or sensors). An optional peak and valley reset is also disclosed.

Abstract: A squaring amplifier circuit (300) generates a substantially rectangular output signal from an a.c. input signal. An amplifier stage (303) is biased at a low quiescent current by a current source network (305) and a coupling network (306). Since the amplifier stage (303) current is a non-linear function of its input voltage, application of a low-level a.c. input signal (313), through an input signal coupling network (302), results in a substantially rectangular output signal having frequency and duty cycle that are substantially identical to the frequency and duty cycle of the input signal.

Abstract: A first input signal has successive zero amplitude crossings. A first comparator generates a first bilevel output signal responsive to the first input signal. The first comparator has a hysteresis characteristic which is switched on at each said zero crossing of the first input signal and switched off prior to each occurrence of the next following zero crossing. A second input signal has successive zero amplitude crossings and is displaced in phase relative to the first input signal. A second comparator generates a second bilevel output signal responsive to the second input signal. The hysteresis characteristic is switched on by level transitions of the first bilevel output signal and switched off by level transitions of the second bilevel output signal. The first and second input signals may be sinusoidal. The hysteresis characteristic may controlled by first and second flip/flops, which are set by the first bilevel output signal and reset by the second bilevel output signal.