Abstract: A semiconductor device with low power consumption can be provided. The semiconductor device includes a differential circuit and a latch circuit, the differential circuit includes a transistor including an oxide semiconductor in a channel formation region, and the latch circuit includes a transistor including a single semiconductor or a compound semiconductor in a channel formation region. The differential circuit and the latch circuit include an overlap region.

Abstract: A receiver system for an on-off key (“OOK”) isolator system may include a pair of receivers. A first receiver may generate a first current signal representing a received OOK signal, and a second receiver may generate a second current signal from a common mode representation of the received OOK signal. The receiver system may include circuitry to compare the first and second current signals and generate an output signal therefrom.

Abstract: Octagonal phase rotator includes an I-mixer having an I-DAC for steering current between positive and negative phases of an in-phase signal depending on k I-DAC control bits of a control code, a Q-mixer having a Q-DAC for steering current between the positive/negative phases of a quadrature signal depending on k Q-DAC control bits of the code, and an IQ-mixer having n IQ-mixer units each comprising an IQ-DAC for switching a second current unit between the in-phase and quadrature signals, in dependence on a respective bit of n IQ-DAC control bits, and between the positive/negative phases of the in-phase and quadrature signals via I and Q polarity switches respectively of that component. I and Q polarity switches of some different IQ-DAC components switch depending on different I-DAC control bits and Q-DAC control bits respectively. A summation circuit sums weighted output signals from the mixers to produce an output signal of phase.

Abstract: Microfluidic oscillator circuits and pumps for microfluidic devices are provided. The microfluidic pump may include a plurality of fluid valves and a microfluidic oscillator circuit having an oscillation frequency. The fluid valves may be configured to move fluids. Each fluid valve may be connected to a node of the microfluidic oscillator circuit. The pumps may be driven by the oscillator circuits such that fluid movement is accomplished entirely by circuits on a microfluidic chip, without the need for off-chip controls.

Abstract: A flip-flop circuit includes a first unit configured to receive a reference clock signal and a reset signal, and a second unit configured to change an output node to a first level in response to the reference clock signal and change the output node to a second level by precharging the output node in response to a signal output from the first unit according to the reset signal.

Abstract: An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a first clock switch configured to couple the differential inverter to a voltage source, a second clock switch configured to couple the differential inverter to a ground, wherein the first clock switch and the second clock switch are configured to receive a differential clock signal, and wherein the first clock switch and the second clock switch are both open or both closed depending on the differential clock signal.

Abstract: A semiconductor device with low power consumption and a small area is provided. By using a transistor including an oxide semiconductor for a channel as a transistor included in a flip-flop circuit, a divider circuit in which the number of transistors is small, power consumption is low, and the area is small can be achieved. By using the divider circuit, a semiconductor device which operates stably and is highly reliable can be provided.

Abstract: A comparator includes: a differential amplifier of which operational state is switched in response to a clock-signal, and which outputs a first intermediate-output corresponding to a first input-signal and a second intermediate-output corresponding to a second input-signal; a differential latch circuit of which operational state is switched in response to the clock-signal, and a state of which is changed depending on the first intermediate-output and the second intermediate-output; a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output; and a second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output.

Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.

Abstract: Implementations of the present disclosure involve a semi-dynamic flip-flop circuit incorporating a partially floating evaluation window that provides a faster data to output delay, a PMOS keeper device may be placed in series with an existing keeper circuit of the semi-dynamic flip-flop circuit. The gate of the PMOS series keeper device may be connected to a shut-off signal of the semi-dynamic flip-flop circuit that provides a three gate delay, self-timed positive pulse to control the keeper circuit. The PMOS series keeper device effectively turns off the keeper circuit when the clock signal rises but turns in back on after a three gate delay to sustain the precharge state of the dynamic node. The effective turning on and off of the keeper circuit portion may decrease the data to output delay of the flip-flop, resulting in higher performing microprocessors.

Abstract: A solar cell having an open loop voltage that approaches a critical voltage range when exposed to light. A circuit, connected to the solar cell, is configured to load the solar cell when the open loop voltage of the solar cell reaches a threshold within a predetermined range of the critical voltage range.

Abstract: A latch circuit includes an output driver electrically coupled with a circuit. The circuit is electrically coupled with the output driver through a first path and a second path. The circuit is configured to receive a data signal. The circuit is configured to divert a signal of the output driver through the first path at a falling edge of the data signal. The circuit is configured to divert the signal of the output driver through the second path at a rising edge of the data signal.

Abstract: Standard cells that include transistors subject to aging as a result of BTI-related operating conditions are identified and replaced with BTI-resistant standard cells, for example. The BTI-resistant standard cells are typically functionally equivalent circuits (such as circuits included in standard cells in a design library) and are arranged to ensure that critical transistors are protected (e.g., by either extending recovery times and/or turning the transistor off in response to a critical edge transition).

Abstract: A latch circuit includes an output driver electrically coupled with a circuit. The circuit is electrically coupled with the output driver through a first path and a second path. The circuit is configured to receive a data signal. The circuit is configured to divert a signal of the output driver through the first path at a falling edge of the data signal. The circuit is configured to divert the signal of the output driver through the second path at a rising edge of the data signal.

Abstract: A circuit for processing a clock signal including first and second clock edges of different polarities, the circuit including an inverter for inverting a first clock edge to generate an inverted first clock edge and inverting a second clock edge to generate an inverted second clock edge; a first pass gate for receiving the inverted clock edge and outputting a first trigger signal of a first polarity; and a second pass gate for receiving the second clock edge and outputting a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and second trigger signal.

Abstract: The invention relates to a data pipeline comprising a first stage with a data input for receiving a digital data input signal, a clock input and a data output, and a first bi-stable element being adapted to be switched in response to an edge of a first clock signal, and a dynamic latch stage comprising an input transfer element, and a second bi-stable element coupled between the input transfer element and a dynamic latch data output, wherein the input transfer element is adapted to be switched by a second clock signal and a delayed second clock signal, which is delayed with respect to the second clock signal by a first period of time being shorter than half a period of the second clock signal, such that the input transfer element allows signal transfer only during the first period of time.

Abstract: A solar cell having an open loop voltage that approaches a critical voltage range when exposed to light. A circuit, connected to the solar cell, is configured to load the solar cell when the open loop voltage of the solar cell reaches a threshold within a predetermined range of the critical voltage range.

Abstract: A semiconductor device includes a plurality of CML buffering units configured to buffer, in parallel, a plurality of serially applied data signals to CML levels in a sequence responding to multi-phase source clocks; and a CMOS amplification block configured to amplify a plurality of buffered data signals, sequentially outputted from the plurality of CML buffering units, to CMOS levels in response to the multi-phase source clocks, and output amplified data signals in parallel at the same timing.

Abstract: In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a second dynamic circuit 1B is H, so that an output signal Q has an H level. In this case, when none of a plurality of pieces of data D0 to D2 is selected using selection signals S0 to S2, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal Q erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor Tr6 of the second dynamic circuit 1B is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected.

Abstract: A flop circuit comprises a precharge circuit for precharging a first node in response to an occurrence of a first phase of a timing signal, and a discharge circuit for conditionally discharging the first node in response to an occurrence of a second phase of the timing signal depending upon a data input signal. The flop circuit further comprises a voltage retention circuit, such as a latch, configured to store a retained logic value that depends upon a logic value present at the first node during at least a portion of the second phase of the timing signal, and an output circuit configured to generate an output signal that depends upon the data input signal. The output circuit may be configured to drive the output signal in a first logic state when the first node is discharged regardless of the retained logic value, and may be configured to drive the output signal in a logic state that depends upon the retained logic value when the first node is charged.

Abstract: A single-path latch, a dual-path latch, a method of operating a DFF and a library of cells. In one embodiment, the single-path latch includes: (1) a passgate coupled to the data input, (2) a feedback path coupled to the passgate, the data output coupled thereto and (3) tristate circuitry coupled to the passgate and having a single transistor pair of opposite conductivity coupled to Boolean logic gates, the Boolean logic gates configured to control operation of the single transistor pair based on the data input and a pulse clock signal to drive the feedbacks path.

Abstract: Bistable circuit switching at the edges of a clock signal, including means for pre-charging an intermediate node of the circuit, delay means including a chain of inverters defining a time window around an edge of said clock signal, means for discharging the intermediate node controlled by at least one input data item making it possible to discharge the intermediate node for the duration of said time window, characterized in that the delay means include means for temporally adjusting the duration of the time window to the time for discharging the intermediate node through said discharge means.

Abstract: In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a second dynamic circuit 1B is H, so that an output signal Q has an H level. In this case, when none of a plurality of pieces of data D0 to D2 is selected using selection signals S0 to S2, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal Q erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor Tr6 of the second dynamic circuit 1B is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected.

Abstract: A semiconductor integrated circuit includes a first data holding section, a first pull-up circuit, a first pull-down circuit, a first feedback circuit, and a second feedback circuit. The first data holding section holds first output data. The first pull-up circuit takes in input data as a pull-up control signal and, when the pull-up control signal takes one value, pulls up the first output data. The first pull-down circuit takes in the input data as a pull-down control signal and, when the pull-down control signal takes the other value, pulls down the first output data. The first feedback circuit feeds back a first feedback signal corresponding to the first output data as the pull-up control signal to the first pull-up circuit. The second feedback circuit feeds back a second feedback signal corresponding to the first output data as the pull-down control signal to the first pull-down circuit.

Abstract: A logic circuit is provided with a first differential transistor pair (Q1, Q2) operable in response to a data signal input thereto; a current source for supplying a current to the first differential transistor pair (Q1, Q2); a first transistor (Q5) connected between a common emitter of the first differential transistor pair (Q1, Q2) and the current source, and operable in response to a clock signal input thereto; and a first potential stabilizing circuit (30a) connected to a first junction between the common emitter of the first differential transistor pair (Q1, Q2) and a collector of the first transistor (Q5), for stabilizing a potential at said first junction.

Abstract: Disclosed herein are synchronization latch solutions.

Abstract: A dynamic floating input D flip-flop (DFIDFF) is provided. The DFIDFF includes a floating input stage, a first string of transistors, and a second string of transistors. At a pre-charge period, the floating input stage transmits the input data to the first string of transistors; the first string of transistors stores the logic status of the input data, and pre-charges its output node to a first level. At an evaluation period, the first string of transistors decides its output node level in accordance with data logic status stored in the first string of transistors; and the second string of transistors decides output level of the D flip-flop in accordance with logic status of the output node of the first string of transistors.

Abstract: A flip-flop circuit arrangement having a total of four differential amplifiers (1, 2, 3, 4), which are connected to one another to produce a D flip-flop, is specified. According to the suggested principle, the two shared emitter nodes (E1, E2) of the differential amplifiers (1, 2, 3, 4) are connected via a switch pair (S1, S2) to supply potential and are activated by a differential input clock signal at a control input (CN, CP). The present flip-flop circuit is operable using especially low supply voltage (VCC) and is preferably suitable for constructing frequency dividers or shift registers.

Abstract: A latch circuit includes first, second, and third inverter circuits, a switching element, and a capacitor element. The first inverter circuit and the second inverter circuit are cross-connected to each other. The third inverter circuit logically inverts an output from the first inverter circuit. The switching element is connected between the output terminal of the second inverter circuit and the output terminal of the third inverter circuit. The capacitor element is connected between the output terminal of the third inverter circuit and a reference voltage node.

Abstract: A bistable flip-flop device is provided that is triggered on the edges of a clock signal. The device has an active mode in which it is electrically powered and an inactive mode. The device includes a chain of inverters controlled by a clock signal, storage means for storing the state of the device in the active mode, and retention means for storing the state of the device in the inactive mode. The device includes a continuously-powered bistable structure that integrates the retention means and part of the storage means. The bistable structure includes a single isolation switch connected to the inverter chain and controlled by a standby logic signal that is representative of the active or inactive mode.

Abstract: In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a second dynamic circuit 1B is H, so that an output signal Q has an H level. In this case, when none of a plurality of pieces of data D0 to D2 is selected using selection signals S0 to S2, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal Q erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor Tr6 of the second dynamic circuit 1B is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected.

Abstract: An ultra low power relaxation CMOS oscillator for low frequency clock generation comprises a current source and a pair of capacitors that are alternatingly charged by the current source and discharged by thyristor-based inverters being used as comparators. No separate bias currents are needed.

Abstract: A latch is provided that includes a first inverter, a second inverter, a first latch circuit and a second latch circuit. The first inverter to receive the first clock signal from an input port and to provide a clock signal. The second inverter to receive the first clock signal from the input port and to provide a clock signal. The first latch circuit is to store data and to receive a clock signal from the second inverter. The second latch circuit is further to store data and to receive a clock signal from the first inverter.

Abstract: A semiconductor device includes: a first transistor having a control electrode coupled to an input node receiving a signal synchronized with a clock, a first conductive electrode coupled to an output node, and a second conductive electrode; a second transistor having a control electrode coupled to the input node, a first conductive electrode coupled to the output node, and a second conductive electrode coupled to a power supply node; and a first switch element connected between the power supply node and the second conductive electrode of the second transistor and turned on and off based on a first control signal indicating a detection result of a frequency of the clock.

Abstract: Circuitry for latching receives an input signal and a control signal and provides an output signal. In one embodiment, the setup time (t(SL) and t(SH)) of the input signal with reference to the control signal is to the first edge of the control signal, the holding time (t(HL) and t(HH)) of the input signal with reference to the control signal is independent of the second edge of the control signal, and the output signal goes to a predetermined state in response to the second edge of the control signal. In one embodiment, the control signal may be a clock. The circuitry for latching may be used with static circuits and/or with dynamic circuits.

Abstract: Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.

Abstract: A level shifter is provided. The level shifter includes a first input transistor, a second input transistor, a first bias transistor, a second bias transistor, a first switch transistor and a second switch transistor. At the time of change of the signal status, by raising the potential of the body terminal of the first input transistor, the threshold voltage is reduced so that the current flowing through the second input transistor is increased to shorten the time of the change of the signal status.

Abstract: A mixer circuit arrangement 30 comprises a complementary transconductor circuit 31 and a mixer stage 32. The complementary transconductor circuit 31 includes two paths in parallel between a positive supply voltage VDD and ground G and is connected directly between the voltage supply terminals VDD and G. The first path includes a P-type MOS transistor TP1 and an N-type MOS transistor TN1 connected in series. Similarly, the second path includes a P-type MOS transistor TP2 and an N-type MOS transistor TN2 connected in series. The gate electrodes of the P-type transistors TP1 and TP2 are connected to a voltage bias Vbp via high value bias resistors Rb, and the gate electrodes of the N-type transistors TN1 and TN2 are connected to a second voltage bias Vbn via high value bias resistors Rb. The mixer stage 32 is connected between the output of the complementary transconductor circuit 31 and a load, the load also being connected to one of the supply terminals.

Abstract: A semiconductor integrated circuit device includes control circuits FRQCNT, VDDCNT and VBBCNT that generate the optimum clock signal, supply voltage and substrate bias respectively and then supply them to a main circuit LSI. This operation makes it possible to suppress the variations of a CMOS circuit characteristic, thereby improving the circuit performance. Further, the low power consumption is realized without degrading the operating speed of the CMOS circuit or increasing the power consumption of the CMOS circuit.

Abstract: The semiconductor integrated circuit of this invention includes a first transistor for setting a first node at a first logic level in accordance with a clock signal; an input circuit for setting the first node at a second logic level in accordance with an input signal; a second transistor for setting a second node at the first logic level when the first node is at the first logic level; a resistor device connected between the first node and the second node; a first driving transistor for receiving, as an input, potential of the second node and controlling whether or not an output node is set at the first logic level; and a second driving transistor for receiving, as an input, a signal at a logic level identical to the logic level of the first node and controlling whether or not the output node is set at the second logic level.

Abstract: A label printer-cutter includes a frame and a print head assembly connected to the frame. The print head assembly includes a print head for printing to a label media. The label printer-cutter includes a cutting assembly connected to the frame, and the cutting assembly is for catting the label media. The printer-cutter also includes a controller in operative association with the print head assembly and cutting assembly. The controller can be programmed to control the print head assembly and the cutting assembly such that printing to and cutting of the label media does not occur simultaneously in the label printer-cutter. Printing by the print head is controlled to correspond to cutting assembly rollers being positioned in a non-cutting position. Advantageously, printing to and cutting of a label media in a single label printer-cutter unit is accomplished in an efficient and cost-effective manner.

Abstract: A pulse generator includes circuitry for starting a pulse in response to receipt of a pulse enable signal. The pulse enable signal is synchronous with a first time base. The pulse generator includes circuitry for ending the pulse after a predetermined, user selectable, number of clock cycles. The clock cycles have a second time base that is asynchronous with the first time base. Since the end pulse signal is not on the same time base as the pulse enable signal, there is up to one asynchronous clock cycle period random variation in width of pulses having the same nominal width.

Abstract: A CMOSFET switch includes a NMOSFET, a PMOSFET, an input formed at the connection of the source terminals of the MOSFETs, and an output formed at the connection of the drain terminals of the MOSFETs. At least one of the MOSFETs is characterized by a small magnitude inherent threshold voltage, or the CMOSFET switch has at least one circuit that is capable of reducing a voltage difference between the source and body terminals of a MOSFET, or both. The variations in on resistance can be reduced over a wide common mode range by reducing the threshold voltages of the NMOSFET and the PMOSFET of the CMOSFET switch.

Abstract: A logic circuit and associated method are provided to improve the switching performance of integrated circuit devices. The logic circuit includes a pass transistor logic circuit, a CMOS transistor pair connected as an inverter and having an input coupled to the output of the pass transistor logic circuit, a clocking transistor coupled between the inverter and a potential terminal to selectively enable the inverter according to a first clocking signal, and a precharge transistor coupled between the inverter output and a potential terminal to precharge the inverter output low according to a second clocking signal.

Abstract: Low voltage latches are designed such that the latch components are comprised of low threshold transistors. To overcome the effects of leakage current and ensure proper latch operation, according to the invention, the channel widths of the low threshold transistors making up the feedback components of the latch are larger than the channel widths of the low threshold transistors making up the storage components of the latch. Using the method and structure of the invention, the voltage scalability of the latch is significantly increased. One embodiment of the invention allows for minimum supply voltages of around 120 millivolts, an improvement of over six hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts.

Abstract: In a flip-flop circuit, a master latch has a data input circuit that reads data when a clock input signal is at a first level. When the clock input signal is at a second level, a first data holding circuit holds the data, and a signal switching circuit transfers the data to a slave latch. The slave latch reads the data from a data output circuit when the clock input signal is at the second level. When the clock input signal returns to the first level, a second data holding circuit holds the data read from the data output circuit.

Abstract: A logic circuit and associated method are provided to improve the switching performance of integrated circuit devices. The logic circuit includes a pass transistor logic circuit, a CMOS transistor pair connected as an inverter and having an input coupled to the output of the pass transistor logic circuit, a clocking transistor coupled between the inverter and a potential terminal to selectively enable the inverter according to a first clocking signal, and a precharge transistor coupled between the inverter output and a potential terminal to precharge the inverter output low according to a second clocking signal.

Abstract: A double data rate dynamic logic gate in which an evaluation phase is performed for each phase of a clock signal. In one embodiment, an nMOSFET pull-down logic unit is clocked by two nMOSFETs switched in complementary fashion, and dynamic latches provide the output signals. In another embodiment, two nMOSFET pull-down logic units are employed, each clocked by an nMOSFET in complementary fashion, and a static logic unit provides the output signals.

Abstract: A buffer circuit that operates with reduced voltage input and output signals receives an input signal having reduced voltage range and generates an output signal with the reduced voltage range. The reduced voltage range is from 0 volts to VRED, where VRED is less than VCC, the voltage used to operate most of the logic in the integrated circuit. The use of a buffer circuit that receives and generates signals with a reduced voltage range advantageously reduces power consumption.

Abstract: A semiconductor integrated circuit so configured to stop the supplying of an electric power to a logic circuit in a standby mode, thereby to realize a low power consumption, includes a latch circuit characterized in that as the control signal a clock signal is supplied in the active mode, and a signal for creating an information hold condition is supplied in the standby mode, and in that MOSFETs applied with a control signal include a first conductivity type MOSFET having a high threshold and a second conductivity type MOSFET having a low threshold, a voltage amplitude of the control signal being larger than a power supply voltage. The semiconductor integrated circuit can be realized in that the high speed operation in the active mode and the low power consumption in the standby mode are compatible with each other, and it is sufficient if a power switch for the logic circuit is inserted at only either of the high level power supply voltage line side and the low level power supply voltage line side.