Circuit Having Only Two Stable States (i.e., Bistable) Patents (Class 327/199)
  • Patent number: 10505520
    Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: December 10, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Jun Koyama
  • Patent number: 10447251
    Abstract: The present invention relates to a combiner latch circuit for generation of one phase differential signal pair or two phase differential signal pairs. The combiner latch circuit comprises an input circuit configured to select a state of the output circuit from a group of: a fourth state comprising the differential output X=1, Y=0, a fifth state comprising the differential output X=0, Y=1. The input circuit is further configured to select the fourth state if the input A=0 and the input B=1 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fifth state, and select the fifth state if the input A=1 and the input B=0 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fourth state.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: October 15, 2019
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Reza Bagger
  • Patent number: 10438933
    Abstract: A semiconductor device includes: a first semiconductor die and a second semiconductor die connected on the first semiconductor die, in which the first semiconductor die includes buffers in a second-stage configuration to an Nth-stage configuration (N being an integer of 3 or more) in a clock tree structure, and the second semiconductor die includes a logic circuit electrically connected to the buffer in the Nth-stage configuration.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: October 8, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Hironori Kawaminami
  • Patent number: 10348300
    Abstract: A method for adiabatic charging of a capacitive load sequentially connects outer switches between a voltage VDD and ground and inner switches to at least one capacitance that self-balances between VDD and ground. A voltage waveform is provided to the capacitive load from a common node of the outer switches and the inner switches. An adiabatic charging circuit includes outer transistor switches between a voltage VDD and ground. Inner transistor switches are connected to at least one capacitance that self-balances between VDD and ground. A control signal generating circuit generates control signals for the inner and outer transistor switches that sequentially turn the inner and outer switches on and off to create a multi-level voltage staircase waveform at a common node of the inner and outer transistor switches.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: July 9, 2019
    Assignee: The Regents of the University of California
    Inventors: Loai Galal Bahgat Salem, Patrick Mercier
  • Patent number: 10333498
    Abstract: An integrated circuit includes a plurality of positive edge-triggered master-slave flip-flop circuits sharing a clock signal. At least one of the positive edge-triggered master-slave flip-flop circuits includes; an input stage that provides a first output signal generated from an input signal in response to the clock signal and an inverted clock signal, a first inverting circuit that generates the inverted clock signal by delaying the clock signal, a transmission gate that receives a second output signal and generates a final output signal, and a second inverting circuit that receives the first output signal and generates the second output signal from the first output signal. The clock signal is applied to an NMOS transistor of the transmission gate and a PMOS transistor of the input stage, and the inverted clock signal is applied to a PMOS transistor of the transmission gate and an NMOS transistor of the input stage.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: June 25, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Su Kim, Jong Woo Kim, Ji Kyum Kim
  • Patent number: 10333500
    Abstract: A circuit includes a latch configured to update a stored state of the latch in response to an input data signal and a pulsed clock signal. The circuit includes a pulse generator configured to generate the pulsed clock signal based on an input clock signal, the input data signal, and a feedback signal indicative of a stored state of the latch. The pulse generator may be configured to generate a pulse enable signal based on the input data signal, the input clock signal, and the feedback signal. The pulsed clock signal may be based on the pulse enable signal and the input clock signal. The pulse generator may generate the pulsed clock signal to have a pulse of a first signal level in response to an indication that the stored state of the latch needs to change and generates the pulsed clock signal to have a second signal level, otherwise.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: June 25, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David Scott Vickers, Patrick J. Shyvers
  • Patent number: 10320367
    Abstract: Disclosed is a method for synchronising at least one slave control circuit, controlled by a slave control signal having pulse width modulation, with a master control circuit, controlled by a master control signal having pulse width modulation, including the following steps: the master control circuit emitting a synchronisation signal indicating a master edge of an electrical quantity; the slave control circuit receiving the synchronisation signal; measuring a delay between a slave edge of the same electrical quantity and the master edge of the electrical quantity; time-shifting the slave control signal so as to reduce the delay; and repeating the measurement step until the delay is eliminated.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: June 11, 2019
    Assignees: CONTINENTAL AUTOMOTIVE FRANCE, CONTINENTAL AUTOMOTIVE GMBH
    Inventor: Angelo Pasqualetto
  • Patent number: 10283936
    Abstract: An apparatus that includes a gain chip assembly, an external cavity, and a controller is disclosed. The gain chip assembly includes first and second gain chips that are coupled optically such that light travels serially between the first gain chip and the second gain chip, each gain chip is electrically biased. The electrical bias of the first gain chip is independent of the electrical bias of the second gain chip. The external cavity has a tunable wavelength selective filter that is changed in response to a control signal. Light in the external cavity passes through the gain chip assembly. The controller determines the tunable wavelength selective filter, and the electrical bias of each of the gain chips so as to cause the apparatus to lase at a wavelength specified by a control signal to the controller.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: May 7, 2019
    Assignee: Agilent Technologies, Inc.
    Inventor: Guthrie Partridge
  • Patent number: 10268613
    Abstract: A control system is disclosed. The control system includes an input module (IM) configured to be detachably coupled to a connection plane, an output module (OM) configured to be detachably coupled to the connection plane, and a logic module (LM) configured to be detachably coupled to the connection plane. The IM, OM, and LM are devoid of any programmable devices in any electronic path from any input port to any output port of the IM, OM, and LM.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: April 23, 2019
    Assignee: Lockheed Martin Corporation
    Inventor: Richard A. Cobley
  • Patent number: 10270432
    Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes master switch circuitry made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region. The flip-flop also includes slave switch circuitry operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch perimeter resides within the flip-flop region and is non-overlapping with the master switch perimeter.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Shang-Chih Hsieh, Che Min Huang
  • Patent number: 10163465
    Abstract: A data receiver for a double data rate (DDR) memory includes a first stage circuit and a second stage circuit. The first stage circuit is deployed for receiving a single-ended signal from the DDR memory and converting the single-ended signal into a pair of differential signals. The second stage circuit, coupled to the first stage circuit, is deployed for receiving the differential signals from the first stage circuit and converting the differential signals into an output signal. Both of the first stage circuit and the second stage circuit are implemented in a core voltage domain.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: December 25, 2018
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Po-Yao Ko, Chien-Chung Chen, Hsu-Yu Huang, Chun-Po Huang
  • Patent number: 10036773
    Abstract: Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: July 31, 2018
    Assignee: UNIVERSITY OF SOUTH FLORIDA
    Inventors: Swaroop Ghosh, Cheng-Wei Lin
  • Patent number: 9985620
    Abstract: A fast latched comparator may include an amplifier portion and a latch portion. A switch activated by a reset pulse may short together outputs of the latched comparator.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: May 29, 2018
    Assignee: Endura Technologies LLC
    Inventor: Hassan Ihs
  • Patent number: 9971378
    Abstract: A clock phase detector circuit device and method. The device can include a first and second clock inputs connected to two pairs of transistors, each transistor having a first, second, and third terminal. The first pair includes a p-type transistor and n-type transistor configured such that the third terminals of each transistor are connected to form a first output node. Similarly, the second pair includes a p-type transistor and n-type transistor, the second p-type transistor and n-type transistor configured such that the third terminals of each transistor are connected to form a second output node. The first clock input is connected to the first terminals of the first p-type transistor and the second n-type transistor, while the second clock input is connected to the first terminals of the second p-type transistor and the first n-type transistor. As configured, the voltage outputs represent the phase difference between the clock inputs.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: May 15, 2018
    Assignee: INPHI CORPORATION
    Inventor: Amr Fahim
  • Patent number: 9958505
    Abstract: A voltage sensing circuit includes a difference voltage sensing circuit and a leakage cancelling circuit. The difference voltage sensing circuit includes two sensing capacitors, a first sensing switch, a second sensing switch, and a third sensing switch. A first group including the first sensing switch and the second sensing switch and a second group including the third sensing switch are complementally turned on and turned off. The leakage cancelling circuit includes two compensation capacitors, a first compensation switch, a second compensation switch, and a third compensation switch. A third group including the first compensation switch and the second compensation switch and a fourth group including the third compensation switch are complementally turned on and turned off.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: May 1, 2018
    Assignee: DENSO CORPORATION
    Inventor: Kazutaka Honda
  • Patent number: 9941867
    Abstract: One embodiment relates to a pulse latch that includes a latch control logic circuit and a pulse latch circuit. The latch control logic circuit generates a plurality of control signals and selects a control signal of the plurality of control signals to output to the pulse latch circuit. Each control signal of the plurality of control signals causes the pulse latch circuit to operate in a different operating mode. Another embodiment relates to a method of generating control signaling for a pulse latch. A clock signal and a shifted clock signal are received. A plurality of inputs to a multiplexor are generated using the clock signal and the shifted clock signal. An input of the plurality of inputs is selected as an output of the multiplexor. The input is selected by the multiplexor using a plurality of multiplexor configuration bits.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: April 10, 2018
    Assignee: Altera Corporation
    Inventor: Scott Weber
  • Patent number: 9906132
    Abstract: A DC-to-DC converting circuit includes a power switch unit, a second power switch, a phase node, a boosted circuit and a sensing circuit. The power switch unit includes a first power switch, a sensing element, a first end, a second end and a sensing end. The sensing element is connected to the sensing end and the first end. The first end is connected to an input voltage. The second power switch is connected to the first power switch. The phase node is located between the power switch unit and the second power switch and is connected to the second end. The boosted circuit boosts the input voltage to a first operation voltage and provides the first operation voltage to the sensing end. The first operation voltage is higher than the input voltage. The sensing circuit is connected to the boosted circuit and the sensing end to obtain a sensing voltage.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: February 27, 2018
    Assignee: uPI Semiconductor Corp.
    Inventor: Sheng-An Ko
  • Patent number: 9876488
    Abstract: A flip-flop circuit includes a D flip-flop and a gating controller. The D flip-flop generates an output signal according to a data signal and a gated clock signal. The gating controller receives an original clock signal. The gating controller further compares the output signal with the data signal. If the output signal is the same as the data signal, the gating controller will maintain the gated clock signal at a constant logic level. If the output signal is different from the data signal, the gating controller will use the original clock signal as the gated clock signal.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: January 23, 2018
    Assignee: MEDIATEK INC.
    Inventor: Rei-Fu Huang
  • Patent number: 9875328
    Abstract: An apparatus for storing data includes a latch circuit comprising a first set of transistors that propagate an input signal to an output signal and a second set of transistors that do not propagate the input signal of the latch circuit to the output signal wherein a gate pitch for the first set of transistors is substantially greater than a gate pitch for the second set of transistors. Also disclosed herein, a method for improving circuit performance includes receiving an electronic representation of a plurality of latching circuits associated with a design file and increasing transistor gate pitch for selected transistors of the plurality of latching circuits, wherein the selected transistors comprise transistors that propagate an input signal to an output signal. The method may also include fabricating a chip comprising the plurality of latching circuits. A computer program product corresponding to the method is also disclosed within.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: January 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Robert K. Montoye
  • Patent number: 9741401
    Abstract: Provided is a reception circuit provided in a chip, the reception circuit including a controller that generates a reception control signal which is activated for a preset time on a basis of a first control signal individually provided to a plurality of chips, a buffer that receives a second control signal commonly provided to the plurality of chips, and a delay circuit that receives the second control signal from the buffer in response to the reception control signal and provides the second control signal to other elements in the chip.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: August 22, 2017
    Assignee: SK hynix Inc.
    Inventor: Haeng Seon Chae
  • Patent number: 9729129
    Abstract: A circuit and method for reducing metastability of a CMOS SR flip flop is provided. The circuit comprises a first switching module and a second switching module that are operatively coupled to a first and second output terminal of the CMOS SR flip-flop. The method includes injecting current onto the first and second output terminals of the CMOS SR flip-flop at mutually opposite directions during permissible mid-range voltages of the output terminals. Further, the method includes driving the output terminals of the CMOS SR flip-flop into the predetermined state of zero and predetermined stable state of Vdd by utilizing the currents injected onto the output terminals. As a result, the metastable point of the CMOS flip-flop is diverted from the corresponding metastable voltage and thereby reduces the metastability of the CMOS SR flip-flop.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: August 8, 2017
    Inventor: Bhaskar Gopalan
  • Patent number: 9660620
    Abstract: Techniques are disclosed relating to dual-edge triggered clock gater circuitry. In some embodiments, an apparatus includes dual-edge triggered clock gater circuitry configured to generate an output signal based on an input clock signal and a control signal that indicates whether to gate the input clock signal. In some embodiments, the clock gater circuitry includes first and second storage elements. In some embodiments, the clock gater circuitry includes multiplexer circuitry that selects between outputs of the first and second storage elements to generate the output signal. In some embodiments, the clock gater circuitry includes a third storage element configured to store an indication of which of the first and second storage elements stores a first digital value and which stores an inverse of the first digital value when not gating.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: May 23, 2017
    Assignee: Apple Inc.
    Inventors: Victor Zyuban, Nimish Kabe
  • Patent number: 9536807
    Abstract: A stack package may include a first chip, a second chip, a through silicon via (TSV) and an interface circuit unit. The first chip may include a first internal circuit unit driven by an internal voltage. The second chip may be stacked over the first chip. The second chip may include a second internal circuit unit driven by the internal voltage. The TSV may be electrically coupled between the first chip and the second chip. The interface circuit unit may be arranged in the first chip and the second chip. The interface circuit unit may be coupled to the TSV. A portion of the interface circuit unit may be received a variable voltage different from the internal voltage as a driving voltage.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: January 3, 2017
    Assignee: SK HYNIX INC.
    Inventor: Kyung Whan Kim
  • Patent number: 9530010
    Abstract: A method including receiving energy usage data representative of energy usage of a customer during a particular time period. The energy usage data is sign with a digital signature of a utility. The method includes receiving input of a customer effective to select a data block of the energy usage data. The method includes redacting the selected data block from the energy usage data in response to the input. The method includes calculating a hash value for the redacted data block using a per-customer key that is unique to the customer, an initialization vector, and a counter. The method includes replacing in the energy usage data the redacted data block with the calculated hash value corresponding to the redacted data block.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: December 27, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Daisuke Mashima, Gaurav Lahoti
  • Patent number: 9508301
    Abstract: Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: November 29, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 9503067
    Abstract: A circuit includes first and second gated buffers, respectively receiving and outputting logic signals, including a delayed signal. A finite state machine receives the delayed signal and a clock signal and assumes first or second machine states. The first gated buffer is conditionally enabled based on a state of the finite state machine, while the second gated buffer is enabled regardless of the state of the finite state machine. A method includes receiving and generating logic signals via first and second gated buffers, including a delayed signal. The method includes receiving the delayed signal and a clock signal in a finite state machine. The method further includes enabling the first gated buffer depending on whether the state machine is in a first or a second machine state, and enabling the second gated buffer when the finite state machine is either in the first or the second machine state.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: November 22, 2016
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 9496854
    Abstract: An apparatus includes a latch circuit comprising a first set of transistors that propagate an input signal of the latch circuit to an output signal of the latch circuit and a second set of transistors that do not propagate the input signal of the latch circuit to the output signal of the latch circuit wherein a gate pitch for the first set of transistors is substantially greater than a gate pitch for the second set of transistors. Also disclosed herein, a method for improving circuit performance includes receiving an electronic representation of a plurality of latching circuits associated with a design file and increasing transistor gate pitch for selected transistors of the plurality of latching circuits, wherein the selected transistors comprise transistors that propagate an input signal of a latch to an output signal of a latch. The method also includes fabricating a chip comprising the plurality of latching circuits.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: November 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Robert K. Montoye
  • Patent number: 9479147
    Abstract: A synchronizer flip-flop is provided, which is able to better respond to input values that are not provided for the necessary setup or hold times. The flip-flop includes a latch that includes inverter circuitry for producing a first signal and a signal in dependence on a value of an input signal at a node. A clocked inverter includes a first switch that is connected between a first reference voltage supply and an intermediate node and a second switch, which is connected between the intermediate node and a second reference voltage supply. The first switch is controlled by the first signal and the second switch is controlled by the second signal to produce an output signal at the intermediate node.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: October 25, 2016
    Assignee: ARM Limited
    Inventors: Satheesh Balasubramanian, James Dennis Dodrill
  • Patent number: 9438211
    Abstract: An embodiment latch device includes a first stage having circuitry that receives a differential input and generates a clocked data signal according to a clock signal and the differential input, and a second stage connected to the first stage and having circuitry that generates differential outputs according to the clock signal and the clocked data signal. The second stage further has a reset circuit that resets a latch storage to a high value according to the clock signal.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: September 6, 2016
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Euhan Chong
  • Patent number: 9401711
    Abstract: A circuit of an output stage of a push-pull driver having dynamic biasing may include a stacked configuration of field effect transistors (PFETs) having a first PFET, a second PFET, and a third PFET, whereby the first PFET is connected to a first supply voltage, the third PFET is connected to an output of a switchable voltage bias generator circuit, and the second PFET is electrically connected between the first PFET and the third PFET. A transmission gate may be connected to a second supply voltage, whereby the transmission gate electrically connects the second supply voltage to an electrical connection between the first PFET and the second PFET based on a first operating state for preventing a voltage breakdown condition associated with the stacked configuration of PFETs. The third PFET is bias controlled via the switching of the output of the switchable voltage bias generator circuit.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: July 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Francis Chan, Bo Qu, Si Shi, Songtao Xu
  • Patent number: 9401700
    Abstract: An embodiment latch device includes a first stage having circuitry that receives a differential input and generates a clocked data signal according to a clock signal and the differential input, and a second stage connected to the first stage and having circuitry that generates differential outputs according to the clock signal and the clocked data signal. The second stage further has a reset circuit that resets a latch storage to a high value according to the clock signal.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: July 26, 2016
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Euhan Chong
  • Patent number: 9342259
    Abstract: A computing device includes a first set of non-volatile logic element arrays associated with a first function and a second set of non-volatile logic element arrays associated with a second function. The first and second sets of non-volatile logic element arrays are independently controllable. A first power domain supplies power to switched logic elements of the computing device, a second power domain supplies power to logic elements configured to control signals for storing data to or reading data from non-volatile logic element arrays, and a third power domain supplies power for the non-volatile logic element arrays. The different power domains are independently powered up or down based on a system state to reduce power lost to excess logic switching and the accompanying parasitic power consumption during the recovery of system state and to reduce power leakage to backup storage elements during regular operation of the computing device.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: May 17, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Steven Craig Bartling, Sudhanshu Khanna
  • Patent number: 9294075
    Abstract: To provide a semiconductor device which can perform a scan test and includes a logic circuit capable of reducing signal delay. The semiconductor device includes a combinational circuit, sequential circuits each holding first data supplied to the combinational circuit or second data output from the combinational circuit, first memory circuits each holding first data supplied to the corresponding sequential circuit and holding second data output from the corresponding sequential circuit, and second memory circuits electrically connecting the first memory circuits in series by supplying the first data or second data supplied from one of the first memory circuits to another one of the first memory circuits. The second memory circuit includes a first switch controlling supply of the first data or second data to the node, a capacitor electrically connected to the node, and a second switch controlling output of the first data or second data from the node.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 22, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Wataru Uesugi
  • Patent number: 9246489
    Abstract: The disclosure provides an ICG (integrated clock gating) cell that utilizes a low area and a low power latch. The ICG cell includes a first logic gate that receives an enable signal and generates a latch input. A latch is coupled to the first logic gate and receives the latch input and a clock input. The latch includes a tri-state inverter and an inverting logic gate. The tri-state inverter is activated by a control signal generated by the inverting logic gate. A second logic gate receives the control signal and generates a gated clock.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: January 26, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Suvam Nandi, Badarish Mohan Subbannavar
  • Patent number: 9041448
    Abstract: Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: May 26, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Yang Du, Jing Xie, Kambiz Samadi
  • Patent number: 9020084
    Abstract: Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: April 28, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Seid Hadi Rasouli, Animesh Datta, Saravanan Marimuthu, Ohsang Kwon
  • Patent number: 9018976
    Abstract: In an embodiment of the invention, a dual-port positive level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: April 28, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Steven C. Bartling, Sudhanshu Khanna
  • Patent number: 9013218
    Abstract: In an embodiment of the invention, a dual-port negative level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signal RET, the reset control signal REN and the control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: April 21, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Steven Craig Bartling, Sudhanshu Khanna
  • Patent number: 9013217
    Abstract: In an embodiment of the invention, a dual-port negative level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and the control signals SS and SSN. The signals CKT, CLKZ, RET, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: April 21, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Steven Craig Bartling, Sudhanshu Khanna
  • Patent number: 9013219
    Abstract: A flip flop circuit has a first stage and a second stage. The first stage and the second stage each have interleaved filters.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: April 21, 2015
    Assignee: The Boeing Company
    Inventors: Manuel F. Cabanas-Holmen, Ethan Cannon, Salim A. Rabaa
  • Patent number: 9007091
    Abstract: In an embodiment of the invention, a dual-port positive level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: April 14, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Steven C. Bartling, Sudhanshu Khanna
  • Publication number: 20150091626
    Abstract: A state retention power gated cell includes a logic cell arranged in two or more rows. The logic cell has an active layer including at least a first well and a second well disposed in first and second rows, respectively. In a normal operation mode, the first well is powered with a first bias voltage, the second well is powered with a second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered with VDD. In a standby mode, the first well preferably is powered down, the second well is powered with the second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered down.
    Type: Application
    Filed: May 15, 2014
    Publication date: April 2, 2015
    Inventors: Miaolin Tan, Zhihong Cheng, Juan Fu, Peidong Wang, Yali Wang
  • Patent number: 8994429
    Abstract: Embodiments of a flip-flip circuit are disclosed that may allow a reduction in data setup time and lower switching power. The flip-flop circuit may include an input circuit, an output circuit, a clock circuit, and a feedback circuit. The clock circuit may be operable to generate internal clocks dependent upon received data, and the generated internal clocks may enable the feedback and input circuits.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: March 31, 2015
    Assignee: Oracle International Corporation
    Inventors: Ha M Pham, Jin-uk Shin
  • Publication number: 20150070062
    Abstract: A flip flop circuit has a first stage and a second stage. The first stage and the second stage each have interleaved filters.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: The Boeing Company
    Inventors: Manuel F. Cabanas-Holmen, Ethan Cannon, Salim A. Rabaa
  • Patent number: 8957716
    Abstract: An integrated circuit cell includes a set of circuit elements associated with a logic function along a logical path between an input and an output of the integrated circuit cell. The set of circuit elements includes a first subset of circuit elements having a first width size and a first threshold voltage and configured to operate within a cycle of time. The set of circuit elements also includes a second subset of circuit elements having a second width size and a second threshold voltage and configured to operate within the cycle of time. The first subset and second subset of circuit elements are configured to toggle data between the input and the output. The second threshold voltage is less than the first threshold voltage when the second width size is less than the first width size.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: February 17, 2015
    Assignee: Broadcom Corporation
    Inventor: Paul Penzes
  • Patent number: 8952740
    Abstract: A pulsed latching apparatus and a method for generating a pulse signal are provided. The pulsed latching apparatus consists of a pulsed latch and a pulse signal generator. A data input terminal of the pulsed latch receives input data, the pulsed latch latches the input data according to a pulse signal, and transmits the latched input data through the data output terminal to serve as output data. The pulse signal generator duplicates a data transmission delay between the data input terminal and the data output terminal of the pulsed latch to obtain a duplicated delay. The pulse signal generator receives a clock signal, and processes the clock signal according to the duplicated delay to generate the pulse signal.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 10, 2015
    Assignee: Industrial Technology Research Institute
    Inventor: Shien-Chun Luo
  • Patent number: 8941426
    Abstract: A critical path monitor (CPM) is configured in an integrated circuit (IC). The IC includes a set of critical paths. The CPM includes a set of split paths, a split path in the set of split paths corresponding to a critical path in the set of critical paths, and a split path in the set of split paths including an edge detector. The edge detector is configured with a set of edge detector latches. A set of set-reset (SR) latches is configured such that an edge detector latch is associated with a corresponding SR latch. A reset signal is configured to reach the set of edge detector latches in an offset synchronization with a latch clock signal used in the set of edge detector latches. The CPM is configured to operate using a frequency of the latch clock signal such that the frequency is higher than a threshold frequency.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alan James Drake, Michael Stephen Floyd, Pawel Owczarczyk, Gregory Scott Still, Marshall Dale Tiner, Xiaobin Yuan
  • Publication number: 20150015316
    Abstract: An RFID transponder in one embodiment comprises a radio frequency (RF) transceiver, processing logic coupled to the RF transceiver, a switch coupled to the processing logic, a tunneling device coupled to the switch and a differential sensing circuit having a first input coupled to the tunneling device and a second input coupled to a predetermined reference voltage. In one embodiment, the tunneling device can discharge to a voltage below the predetermined reference voltage.
    Type: Application
    Filed: September 25, 2014
    Publication date: January 15, 2015
    Inventor: John Stephen Smith
  • Patent number: 8928377
    Abstract: A scannable fast dynamic register including a data and scan enable circuit, a precharge circuit, a select circuit, a store circuit, and a scan input enable circuit. The data and scan enable circuit pulls a first precharge node to a discharge node in response to the clock upon evaluation in normal mode. The precharge circuit precharges first and second precharge nodes high, in which one of the precharged nodes discharges depending upon whether a data block evaluates. The store circuit and an output gate are responsive to the second precharge node to provide the output. The select circuit is interposed before the store circuit to allow injection of scan data in a scan mode. In scan mode, the scan input enable circuit provides scan data to the select and store circuits. The scan input enable circuit also includes a store circuit which operates with the first store circuit in a master-slave configuration.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: January 6, 2015
    Assignee: VIA Technologies, Inc.
    Inventor: Imran Qureshi
  • Publication number: 20140354338
    Abstract: A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 4, 2014
    Inventors: Kashyap Ramachandra Bellur, HariKrishna Chintarlapalli Reddy, Martin Saint-Laurent, Pratyush Kamal, Prayag Bhanubhai Patel, Esin Terzioglu