Abstract: A comparator is described. The comparator may be used in several applications, including in digital-to-analog converters (ADC). The comparator may comprise a high-speed amplifier, a low-noise amplifier, a controller and a bi-stable circuit. The high-speed amplifier may be activated during a first period, for example when the comparator tends to exhibit a slow response. During this period, the comparator may sacrifice the noise performance. The low-noise amplifier may be activated during a second period, for example when the difference between the signals appearing as inputs to the comparator is small. The low-noise amplifier may have a gain that is large enough to limit decision errors. The bi-stable circuit, which may be implemented using a latch, may be configured to output a signal equal to one of the supply voltages, in response to receiving the input signal from one of the stages.

Abstract: The invention pertains to a latch circuit comprising a sensing arrangement with one or more sensing transistors adapted to sense an input signal and to provide a first signal based on the sensed input signal, and a sensing arrangement switch device connected or connectable to a first current source, the sensing arrangement switch device being adapted to switch on or off a current to the one or more sensing transistors based on a first clock signal.

Abstract: A semiconductor device has a first driving circuit inputting first data; a first gate circuit for the first data to pass therethrough; a first holding circuit holding the first data from the first gate circuit; a logic circuit carrying out a logic operation on the first data from the first holding circuit and outputting second data; a second driving circuit for inputting the second data from the logic circuit; a second gate circuit for the second data from the second driving circuit to pass therethrough; a second holding circuit holding the second data from the second gate circuit; and a power supply circuit supplying a first power supply voltage to the first and second gate circuits, the first and second holding circuits and the logic circuit, and supplying a second power supply voltage higher than the first power supply to the first and second driving circuits.

Abstract: A latch module comprising a sense pair of transistor elements coupled together for sensing a differential input signal at input terminals, a level-shift module for producing a differential output signal at output terminals, and a regenerative pair of transistor elements coupled together and with the input pair for holding the output signal through the level-shift module. The latch module also includes a pair of gate transistor elements connected in series respectively with the sense pair of transistor elements and with the regenerative pair of transistor elements and responsive to an alternating differential gate signal to activate alternately the sense pair during sense periods and the regenerative pair during store periods. A current injector provides asymmetric operation by injecting current between at least one of the gate transistors and the corresponding sense or regenerative pair of transistor elements so that the sense periods are of different duration from the store periods.

Abstract: In a phase compensation circuit having a resistance connected to the output side of an error amplifier, a capacitor, and a conductance amplifier functioning as a capacitance amplifier circuit, capacitance is amplified by the conductance amplifier and used, whereby an essentially required capacitance is ensured, even when the capacitance of the capacitor is small.

Abstract: A differential latch comprising a data holding transistor, the differential latch comprising: a resetting transistor that is connected to a gate electrode of the data holding transistor and is controlled by a reset signal; and a switching transistor that is connected to the gate electrode of the data holding transistor and is controlled by a switch signal, being an inverted version of the reset signal.

Abstract: For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch part that latches a data output signal from the data acquisition part when the click signal is an “L” level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an “L” level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit.

Abstract: A strip light is disclosed. The light comprises an illuminating unit including a plurality of illuminators (e.g., LEDs) directly and electrically coupled in series, and a constant current stabilization unit with temperature compensating capability for supplying a constant current to each illuminator. A number of embodiments of the constant current stabilization unit are made possible. The invention further has advantages of energy saving, even brightness of the illuminators, less heat generation, and durability.

Abstract: An S-R flip-flop circuit is provided using two stacks of gates 2, 6 with an internal signal Int stored therebetween. Feedback from the output O is used to switch the state of the internal signal Int in a manner that provides an edge-triggered response for at least one of the inputs.

Abstract: A data value is passed from a bus (50) to a receiver (40) without a propagation delay. A data latch (10) stores the data value while the data value is being generated by the bus (50). The data latch (10) then holds the data value and provides the data value to the receiver (40) after the data value is no longer present on the bus (50). The data latch (10) has a data storage circuit (11), a diode clamping circuit (12), and a current sourcing circuit (13). The data value is stored by the data storage circuit (11) by a feed-back loop circuit.

Abstract: A double edge triggered flip-flop is made up of six switches and four inverters. The input data is supplied to one end each of first and second ones of the six switches, the other ends of the first and second switches being separately connected to the inputs of a first and second of the four inverters. The outputs of the first and second inverters are separately connected to the input of the third and fourth inverters via the third and fourth switches. The third inverter serves as a common feedback inverter with the output of the third inverter is connected through the fifth and sixth switches to respective ends of the first and second switches, and the output of the fourth inverter forms the output of the present invention. The first, third, and fifth switches thus form the up-loop for the double edge triggered flip-flop and the second, fourth, and sixth switches forming the down loop, with the two loops sharing the third and fourth inverters.

Abstract: An assertive latching flip-flop circuit is provided which prevents the occurrence of metastable outputs. The circuit comprises a single flip-flop which is comprised of standard switching transistors which are switched by a clocking mechanism having no additionally introduced delay. The circuit includes an imbalancing element which is coupled to a latching portion of the circuit. The latching portion of the circuit comprises a pair of cross-coupled transistors, in current mode embodiments of the invention, or a pair of cross-coupled inverters, in voltage mode embodiments of the invention. The imbalancing element introduces an electrical disturbance on the input line to one of the latching transistors or inverters. The imbalancing element is a capacitor in voltage mode embodiments of the invention and an additional transistor in current mode embodiments.

Abstract: An output stage device for an enhanced differential current switch. The output stage receives a differential signal pair from a prior logic stage and must shift the output signals to the levels necessary for the next stage. The output stage has a differential pair of emitter followers that are capacitively cross coupled. Capacitors couple the collector of a first transistor to the emitter of the second. The capacitors can be formed from forward biased diodes or transistors. The result is a more rapid falling output transition while reducing power requirements.