Abstract: A single-wire communication system and a control method of the single-wire communication system are disclosed. A single-wire communication system includes a single-wire, a first communication module and a second communication module. The first communication module includes a plurality of current conveyors so as to communicate high-speed signals only with current freely from a capacitive load of the single-wire. The first communication module is connected to one side of the single-wire. The second communication module includes a plurality of current conveyors so as to communicate high-speed signals only with current freely from a capacitive load of the single-wire. The second communication module is connected to another side of the single-wire.

Abstract: The present disclosure presents various systems and methods for implementing a physical unclonable function device. One such method comprises providing an integrated circuit having a plurality of set/reset flip flop logic circuits, wherein each of the set/reset flip flop logic circuits enters a metastable state for a particular input sequence. The method includes varying circuit parameters for each of the plurality of set/reset flip flop logic circuits to account for manufacturing variations in the set/reset flip flop logic circuits and enable generating a stable but random output in response to the particular input sequence. Thus, by applying the particular input sequence to the integrated circuit, a unique identifier for the integrated circuit can be derived from an output response of the plurality of set/reset flip flop logic circuits.

Abstract: An active inductor modulator circuit is provided. The active inductor modulator circuit may include a circuit to receive an input signal and provide an output signal at an output terminal of the circuit based on a clock signal, a modulated active inductor coupled to the circuit to improve a time delay between the input signal and the provided output signal, and a modulation clock circuit to generate a delayed clock signal to enable the modulated active inductor prior to a transition of the output signal from a first logic state to a second logic state.

Abstract: A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.

Abstract: A flip-flop includes a first master latch in a first row, a second master latch in a second row, a first slave latch in the first row, and a second slave latch in the second row. The first master latch and the second master latch are adjacently disposed in the second direction, and the first slave latch and the second slave latch are adjacently disposed in the second direction.

Abstract: A system-on-chip includes: a dynamic power monitor configured to generate a power detection signal by calculating an amount of power consumed by a functional circuit in real time; a frequency controller configured to detect an idle period and a running period of the functional circuit in response to the power detection signal, and generate a clock control signal based on the power detection signal; and a clock controller configured to change a frequency of a clock signal provided to the functional circuit, based on the clock control signal. The running period includes: a first running period in which the frequency of the clock signal has a first value based on the clock control signal; and a second running period in which the frequency of the clock signal has a second value that is greater than the first value based on the clock control signal.

Abstract: Superconducting output amplifiers having return to zero to non-return to zero converters are described. An example superconducting output amplifier (OA) includes a first superconducting OA stage having a first DC-SQUID and a second DC-SQUID arranged in parallel to the first DC-SQUID. The superconducting OA includes an input terminal for receiving a single flux quantum (SFQ) pulse train. The superconducting OA includes a first splitter configured to split a first set of SFQ pulses corresponding to the SFQ pulse train into a first return to zero (RZ) signal and a second RZ signal. The superconducting OA includes a first return to zero to non-return to zero (RZ-NRZ) converter configured to convert the first RZ signal into a first non-return to zero (NRZ) signal for driving the first DC-SQUID, and a second RZ-NRZ converter configured to convert the second RZ signal into a second NRZ signal for driving the second DC-SQUID.

Abstract: The driver circuit includes a pull-up network having a first pull-up transistor controlled by a data signal, a second pull-up transistor coupled between the first pull-up transistor and a first power supply voltage, and a third pull-up transistor coupled in parallel with the second pull-up transistor. The third pull-up transistor is configured to turn on for at least one clock cycle responsive to a change in the logic level of the data signal being detected.

Abstract: In a sequential circuit, a first stage is configured to charge a voltage of a first node in response to a clock, and to discharge the voltage of the first node in response to the clock, a voltage of a second node, and data; a second stage is configured to charge the voltage of the second node in response to the clock, and to discharge the voltage of the second node in response to the clock and a logic signal; a combinational logic is configured to generate the logic signal based on the voltage of the first node, the voltage of the second node, and the data; and a latch circuit is configured to latch the voltage of the second node in response to the clock.

Abstract: An electronic circuit includes: a plurality of RS latch circuits each configured to enter a metastable state in accordance with a clock signal input to the RS latch circuit; a determination circuit configured to determine whether an output of each of the RS latch circuits is a random number or a fixed number; and a selector configured to select whether to maintain the clock signal input to the RS latch circuit, to change the clock signal input to the RS latch circuit to another clock signal having a different frequency, or to input a clock signal for fixing a signal output from the RS latch circuit, as the clock signal input to the RS latch circuit, in accordance with a result determined by the determination circuit.

Abstract: Embodiments of a latch circuit and a method of operating a latch circuit are described. In one embodiment, a latch circuit includes an input terminal configured to receive an input data signal, a switching unit configured to control application of the input data signal, a first inverter circuit connected to the switching unit, where the first inverter circuit includes a first cross-coupled pair of inverters, and a second inverter circuit connected to the first inverter circuit through the switching unit. The second inverter circuit includes a second cross-coupled pair of inverters and two transistor devices. Each inverter of the second cross-coupled pair of inverters is connected to a voltage rail through a corresponding transistor device. Each of the two transistor devices is connected to a node that is between the switching unit and the first inverter circuit or the second inverter circuit. Other embodiments are also described.

Abstract: A device comprises a coarse timing skew characterization circuit having a buffer chain and a coarse delay cell calibration circuit comprising a first flip-flop, a second flip-flop and a logic gate, wherein the coarse delay cell calibration circuit is configured to measure a delay between an input of the buffer chain and an output of the buffer chain.

Abstract: In an embodiment of the invention, a dual-port negative level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.

Abstract: A digital circuit portion comprises a flip-flop (20) having a clock input (22) and an output (data); a clock signal (ck); and a gate (24) between said clock signal (ck) and said clock input (22), said gate (24) being arranged selectively to couple the clock signal (ck) to the clock input (22) in dependence upon the output of the flip-flop (20).

Abstract: Configurable flip-flop cells for use in scan chain configurations include one or more multiplexers, a flip-flop, and one or more logic gates. The logic gates are configurable, through modification of different metallization or semiconductor layers, to operate as spare gates or to disable flip-flop cell outputs based selection signal switching between scan shift and capture mode. When disabling flip-flop cell outputs, the logic gates are configured to receive both a test signal and a data input signal and select one of the two to pass to the flip-flop based on the selection signal. When used as spare gates, the logic gates receive external inputs and provide spare gate outputs to circuitry on an integrated circuit that is external to the flip-flop cells.

Abstract: Configurable flip-flop cells for use in scan chain configurations include one or more multiplexers, a flip-flop, and one or more logic gates. The logic gates are configurable, through modification of different metallization or semiconductor layers, to operate as spare gates or to disable flip-flop cell outputs based selection signal switching between scan shift and capture mode. When disabling flip-flop cell outputs, the logic gates are configured to receive both a test signal and a data input signal and select one of the two to pass to the flip-flop based on the selection signal. When used as spare gates, the logic gates receive external inputs and provide spare gate outputs to circuitry on an integrated circuit that is external to the flip-flop cells.

Abstract: In accordance with an embodiment, a description is given of a storage circuit including an input stage configured to provide a value to be stored, a storage stage configured to store the value to be stored, an output stage configured to output a value stored by the storage circuit, and a control circuit, wherein the control circuit is configured to receive a signal from the output stage, which signal indicates the charge state of the output stage, and, if the charge state of the output stage is equal to a predefined precharge state, to output an activation signal to the storage stage, and wherein the storage stage is configured to store the value to be stored, provided by the input stage, in reaction to the activation signal.

Abstract: A first circuit is configured to communicatively couple to a second circuit including an analog circuit and a digital circuit. The first circuit comprises a lock unit and a sleep unit. The lock unit is configured to receive a lock enable signal and to lock a configuration signal of the digital circuit in response to the lock enable signal. The sleep unit is configured to receive a sleep triggering signal indicating to switch into sleep mode and to generate an off signal to switch off the digital circuit in response to the sleep triggering signal, while the analog circuit remains on.

Abstract: Provided is a semiconductor circuit. The semiconductor circuit includes a pulse generator which is enabled by a rising edge of a clock signal and generates a read pulse which varies depending on a voltage of a feedback node; and a sense amplifier which generates a voltage of a dynamic node and the voltage of the feedback node in accordance with a data value of an input signal using the read pulse.

Abstract: Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resulting from metastability in data synchronization. In one such example apparatus, a sampling circuit is configured to provide four samples of a data input signal. A first and a second of the four samples are associated with a first edge of a latching signal, and a third and a fourth of the four samples are associated with a second edge of the latching signal. A masking circuit is configured to selectively mask a signal corresponding to one of the four samples responsive to the four samples not sharing a common logic level. The masking circuit is also configured to provide a decision signal responsive to selectively masking or not masking the signal.

Abstract: A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop.

Abstract: A master-slave flip-flop circuit includes: a master circuit to receive input data in a first state of a reference clock and hold the input data in a second state of the reference clock to output intermediary data; and a slave circuit to receive the intermediary data in the second state and hold the intermediary data in the first state to output data, wherein the master circuit includes: a feedback two-input NOR gate to receive an output of the master circuit and a first clock; an input three-input NOR gate to receive the input data, a second clock, and a third clock; and a synthesis two-input NOR gate to receive an output of the input three-input NOR gate and an output of the feedback two-input NOR gate.

Abstract: One embodiment of the present invention sets forth a technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations, The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant, The output signal Q is set or reset at the rising clock edge using a single- trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

Abstract: A scan flip-flop may include a selector outputting a data signal or a scan input signal in response to a scan enable signal, and a flip-flop that latches an output signal of the selector or the data signal, based on a clock signal and a low voltage signal.

Abstract: An apparatus may include a storage circuit that may have a first terminal and a second terminal and may have two cross-coupled inverters. The apparatus may include a feedback circuit coupled to the first terminal. The feedback circuit may include electronic logic elements to determine if the storage circuit is in a metastable state. The feedback circuit may couple at least one of the first and second terminals to one of a voltage reference and a voltage source if determined that the storage circuit is in a metastable state.

Abstract: An inverter and an antenna circuit. The inverter that receives control signals including a first control signal, a second control signal, and a third control signal, inverts the first control signal, and outputs the inverted first control signal, includes: a first MOS transistor having a gate to which the first control signal is applied and a source that is grounded; a second MOS transistor having a gate to which the third control signal is applied and a source to which the second control signal is applied; and a third MOS transistor having a gate to which the second control signal is applied and a source to which the third control signal is applied, wherein drains of the first MOS transistor, the second MOS transistor, and the third MOS transistor are connected to an output terminal.

Abstract: A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop.

Abstract: Described is an apparatus comprising a plurality of logic units arranged in a ring, wherein an output terminal of each logic unit from the plurality of logic units is coupled to an input terminal of a next logic unit from the plurality of logic units, wherein the plurality of logic units includes a first multiple input logic unit having input nodes coupled to at least two output terminals of logic units from the plurality of logic units; and a plurality of latch units coupled to the output terminals of the plurality of logic units.

Abstract: A method and circuits for implementing power saving self powering down latch operation, and a design structure on which the subject circuit resides are provided. A master slave latch includes a virtual power supply connection. At least one connection control device is coupled between the virtual power supply connection and a voltage supply rail. A driver gate applies a power down signal driving the at least one connection control device to control the at least one connection control device during a self power down mode. The driver gate combines a self power down input signal and a latch data output signal to generate the power down signal.

Abstract: Signal synchronizers synchronize input signals with a clock signal. The input of each synchronizer is connected to a first input and the output of each synchronizer is connected to a second input of a respective first gate arrangement. The first gate arrangements provide an output signal only if there is an input signal on the first input and none on the second input or vice versa. The outputs of each of the first gate arrangements is connected to respective inputs of a second gate arrangement, which provides an output signal if there is a signal on any of its inputs. The output of the second gate arrangement is connected to a third gate arrangement which operates such that the clock signal to the synchronizers is only enabled when there is a change to the state of a signal received at the input of at least one of the synchronizers.

Abstract: A semiconductor integrated circuit includes a first retention flip-flop configured in a first type in which a retention flip-flop is able to retain data based on one of a low-level clock signal and a high-level clock signal, and unable to retain data based on another one of the low-level clock signal and high-level clock signal, and a second retention flip-flop configured in a second type in which a retention flip-flop is able to retain data based on the low-level clock signal and also able to retain data based on the high-level clock signal.

Abstract: A bit generation apparatus includes a glitch generation circuit that generates glitch signals which include a plurality of pulses, and T-FF bit generation circuits which input the glitch signals, and based on either rising edges or falling edges of the plurality of pulses included in the glitch signals, generate a bit value of either 0 or 1. Each of the T-FF bit generation circuits generates a respective bit value based on either the parity of the number of rising edges or the parity of the number of falling edges of the plurality of pulses. As a result of employment of the T-FF bit generation circuits, circuits that are conventionally required but not essential for the glitch become unnecessary. This serves to prevent expansion in circuit scale and increase in processing time of bit generation for the bit generation circuit.

Abstract: Disclosed herein are a delay latch circuit and a delay flip-flop circuit arranged to inhibit the increase in power consumption while preventing malfunction under low voltage conditions. An internal signal output circuit outputs as an internal signal an inverted signal of a data signal starting from an internal transparency start timing until an internal transparency end timing. From the internal transparency end timing until the internal transparency start timing, the internal signal output circuit outputs a fixed value signal as the internal signal. A transistor delays the output internal signal over a time period which ranges from a hold instruction delay timing to the issuance of a data transparency instruction and which includes the internal transparency end timing therebetween.

Abstract: A clock gating mechanism controls power within an integrated circuit device. One or more clock gating circuits are configured to couple a system clock to a different portion of the integrated circuit device. A logic circuit applies an enabling signal to one of the clock gating circuits to control whether the system clock passes through the clock gating circuit to a portion of the integrated circuit device associated with the clock gating circuit. A plurality of scan flip-flops is configured to provide a binary code to the logic circuit, where the binary code indicates to the logic circuit that the enabling signal should be applied to the clock gating circuit. One advantage of the disclosed technique is that power droop during at-speed testing of a device is reduced without significantly increasing the quantity of test vectors or reducing test coverage, resulting in greater test yields and lower test times.

Abstract: Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resulting from metastability in data synchronization. In one such example apparatus, a sampling circuit is configured to provide four samples of a data input signal. A first and a second of the four samples are associated with a first edge of a latching signal, and a third and a fourth of the four samples are associated with a second edge of the latching signal. A masking circuit is configured to selectively mask a signal corresponding to one of the four samples responsive to the four samples not sharing a common logic level. The masking circuit is also configured to provide a decision signal responsive to selectively masking or not masking the signal.

Abstract: A flip-flop circuit includes an input portion that receives a first external input signal through a first external input terminal, a storage portion that stores a signal transmitted from the input portion, and an output portion that outputs the signal stored in the storage portion through an external output terminal as a logic operation result with respect to a second external input signal received through a second external input terminal of the input portion. The output portion includes a logic gate directly connected to the external output terminal and an input terminal of the logic gate receives the signal stored in the storage portion.

Abstract: A scan flip-flop, which performs a normal operation latching a data input and a scan operation latching a scan input, includes a first circuit, a second circuit and a latch. The first circuit determines a voltage of an intermediate node based on a clock signal, one of the data input and the scan input, and data of a latch input node. The second circuit determines the data based on the clock signal, the voltage of the intermediate node and the data input during the normal operation, and determines the data based on the clock signal and the voltage of the intermediate node during the scan operation. The latch latches the data based on the clock signal.

Abstract: A semiconductor device according to one aspect of the present invention includes: a flip-flop; a clock control circuit that controls a clock signal supplied to the flip-flop; and a controller that supplies a data retention signal to the flip-flop and controls the clock control circuit. When the flip-flop is driven by a negative edge of the clock signal and retains data when the clock signal is at a high level, the controller controls the clock control circuit so as to supply a high-level clock signal to the flip-flop after the input clock signal is fixed and before the flip-flop retains data. This prevents the occurrence of unintended latching of data when the flip-flop having a retention function retains data.

Abstract: A latch circuit, such as a memory cell or a flip-flop, that is immune to single-event upset at any single node. The latch circuit includes two banks of four logic gates each. The output of each logic gate in the first bank is connected to inputs of two logic gates in the second bank, and the output of each logic gate in the second bank is connected to inputs of two logic gates in the first bank. Each logic gate includes a logic function receiving an input node and an enable signal, such as a load signal. The interconnection of the logic gates corrects single-event upset at any one of the nodes. In the memory cell arrangement, redundant data paths are used to produce two input nodes provides single-event upset immunity at those input nodes. A layout of the latch circuit that ensures that random ionization affects only a single node is also disclosed.

Abstract: A flip-flop circuit includes an input portion that receives a first external input signal through a first external input terminal, a storage portion that stores a signal transmitted from the input portion, and an output portion that outputs the signal stored in the storage portion through an external output terminal as a logic operation result with respect to a second external input signal received through a second external input terminal of the input portion. The output portion includes a logic gate directly connected to the external output terminal and an input terminal of the logic gate receives the signal stored in the storage portion.

Abstract: One embodiment of the present invention sets forth a technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. The output signal Q is set or reset at the rising clock edge using a single-trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

Abstract: A digital input buffer and method. The input buffer includes a voltage regulator configured for operating in weak inversion and outputting a regulated potential, an inverter having as its power source the regulated potential and configured for receiving an input signal, a first latch having its input coupled to the inverter input, and a second latch having its input coupled to the inverter's output, having its output coupled to the first latch's enable input, and having its enable input coupled to the first latch's output. A first latch output signal from the first latch output and a second latch output signal from the second latch output enable switching the first latch output signal to the complement of the input signal and switching the second latch output signal to that of the input signal.

Abstract: A semiconductor integrated circuit includes a first retention flip-flop configured in a first type in which a retention flip-flop is able to retain data based on one of a low-level clock signal and a high-level clock signal, and unable to retain data based on another one of the low-level clock signal and high-level clock signal, and a second retention flip-flop configured in a second type in which a retention flip-flop is able to retain data based on the low-level clock signal and also able to retain data based on the high-level clock signal.

Abstract: A high speed flip-flop circuit and a configuration method thereof are provided. A small number of transistors may be used to configure a flip-flop circuit, so that the flip-flop circuit may be operated at a high-speed. Additionally, an area occupied by the flip-flop circuit may be reduced, and power consumption may be reduced. Accordingly, the flip-flop circuit may be integrated together with a microwave frequency integrated circuit using a Gallium Arsenide (GaAs) compound semiconductor process.

Abstract: A gated-clock shift register including a series of clocked flip-flops with preceding outputs connected to subsequent inputs as a horizontal digital shift register. Each flip-flop (or other state holding device) includes a clock buffer between the respective flip-flop's clock, and the global clock. Each clock buffer propagates the clock signal when it determines the associated flip-flop will have a state change during that clock cycle (e.g., via an XOR of the flip-flops input and output signals). In the absence of a state change, that buffer does not propagate the clock signal, essentially only clocking the relevant flip-flops. Further, the clock buffer may be implemented with only NMOS devices (or alternatively, only PMOS devices), which offers power savings over an otherwise required CMOS implementation.

Abstract: Disclosed herein is a device that includes first and second current paths, first and second latch circuits electrically connected to the first and second current paths, respectively, a driver circuit supplying first data to the first latch circuit, and supplying second data representing a logical value opposite to a logical value of the first data to the second latch circuit, a control circuit controlling the driver circuit to be alternately and repeatedly in a first period in which the driver circuit supplies the first data to the first latch circuit and does not supply the second data to the second latch circuit, and in a second period in which the driver circuit supplies the second data to the second latch circuit and does not supply the first data to the first latch circuit, and a monitor circuit.

Abstract: The invention describes self-timed RS-trigger with the enhanced noise immunity. Declared effect is achieved due to that circuit containing storage unit (1), indication unit (2), paraphase data input (3, 4), paraphase data output (5, 6), and indication output (7), is modified by adding two inverters (8, 9) and preindication unit (10). Inverters increase output capability of the trigger's paraphase data output and provide an electric isolation of the outputs of the storage unit from an external environment that leads to increasing immunity of the data stored in the trigger to influence of noises at signal wires. The preindication unit provides the trigger's indicatability.

Abstract: A semiconductor device includes: an input node supplied with an input signal; an output node provided correspondingly to the input node; first and second input circuits coupled in parallel to each other between the input and output nodes; and a control circuit configured to control the first and second input circuits such that one of the first and second input circuits is switched over from an active state to an inactive state and the other of the first and second input circuits is switched over from an inactive state to an active state during the one of the first and second input circuits being still in the active state.

Abstract: A high frequency input signal comparator for optimizing group delay, reducing input frequency dependent offset and an offset auto-zeroing latch core are described. The comparator may include an isolation switch stage, and a latch core. The isolation switch stage may isolate latch core depending upon a control signal, thereby reducing input frequency dependent offset. The latch core may include a pair of inverters cross coupled via an impedance to one another. The latch core may include latch switches selected to attain a certain gain across the individual inverters comprising the latch core while resetting the latch core. The gain across the individual inverters during the acquire/reset phase may bootstrap the coupling impedances, thereby reducing loading and group delay at the input of the latch core. The coupling impedances may be designed to minimize or auto-zero statistical offset, thereby minimize input referred offset.

Abstract: A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state transition detection signal indicating that a current state of input data is stored in the latch. As such, two control conditions are used to shut down the latch. In one example, a condition generator detects when the latch has captured data correctly and outputs a signal to disable the input node. In addition, a variable delay circuit is used to adjust the width of the allowable input signal to set a worst case shutoff time. If data is latched early, a feedback latch state transition detection signal causes the input node to be disabled. If data is not latched early, the maximum allowable latch time is set by the variable delay circuit.